|Publication number||US7880179 B2|
|Application number||US 12/623,323|
|Publication date||Feb 1, 2011|
|Filing date||Nov 20, 2009|
|Priority date||Aug 24, 2001|
|Also published as||CN1547778A, CN100578816C, CN101714516A, EP1419534A2, EP2287916A2, EP2287916A3, US6911392, US7700957, US7821106, US8349707, US20030113979, US20050042786, US20080150063, US20100065883, US20110021002, US20130137259, WO2003019653A2, WO2003019653A3|
|Publication number||12623323, 623323, US 7880179 B2, US 7880179B2, US-B2-7880179, US7880179 B2, US7880179B2|
|Inventors||Dipl.-Ing. Florian Bieck, Jürgen Leib|
|Original Assignee||Wafer-Level Packaging Portfolio Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (46), Non-Patent Citations (16), Referenced by (4), Classifications (81), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation application of U.S. application Ser. No. 10/947,974 filed on Sep. 22, 2004, now U.S. Pat. No. 7,700,957, which is a divisional application of U.S. application Ser. No. 10/228,699, filed on Aug. 26, 2002, which issued as U.S. Pat. No. 6,911,392, which claims the benefit of German Application No. DE 10141558.3-33 filed on Aug. 24, 2001, German Application No. DE 10141571.0-33 filed on Aug. 24, 2001, and German Application No. DE 10225373.0 filed on Jun. 6, 2002.
1. Technical Field
The present disclosure relates to a device with contact connections that comprises at least one component integrated in a substrate material.
2. Description of Related Art
There are known processes in which components or integrated circuits on a semiconductor chip or still joined to a semiconductor wafer are provided with a housing and electrical terminal contacts. If the mounting of the chip or of the integrated circuit and the connection of the contact regions of the chip to the contacts of the housing which lead to the outside takes place while the arrangement is still joined to the wafer, a mounting process of this type is generally known as a “wafer level package process”.
A number of such processes are to be found in the prior art. These processes are generally based on it being possible for the connections to the contact regions on the chips or in the integrated circuits to be produced directly, as is the case without problems, for example, in the case of memory chips.
However, this takes no account of the fact that the optically active surface has to be left clear in the mounted state, for example on a printed circuit board, as is the case, for example, in chips with an integrated sensor or optical component.
To this extent, WO 99/40624 has disclosed a process in which it is attempted to ‘overcome the problem outlined above by leading the terminal contacts which lie at the active component from the active side to the opposite underside of the wafer or of the chip. Further contact can then be made with the terminal contacts which have been led downward in a known way. Moreover, a similar process is described in “Wafer Level Chip Scale Packaging: Benefits for Integrated Passive Devices”, Clearfield, H. M.; Young, J. L.; Wijeyesekera, S. D.; Logan, E. A.; IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, pp. 247-251.
The above-mentioned process is distinguished by the fact that, after a glass covering has been applied to the optically active front surface of a wafer, trenches are produced along the * underside of the wafer, dividing the wafer into individual chip regions. As part of the production of the trenches, the terminal contact locations which are located on the active side of the wafer, in each case at the transition region between two chips, are split and thereby uncovered in the trenches. After the trenches have been produced, to completely house the wafer or the chips, a pane of glass is adhesively bonded over the trenches and is cut into in an appropriate way, such that the trenches in the wafer and the terminal contact locations are once again freely accessible. Then, contact tracks are deposited in the trenches which have been produced, as a result of which it is supposed to be possible to make contact with the terminal contact locations and to lay the contact location on the back surface of the housed chip.
Although the proposed process leads to through-contact being made with the terminal contacts from the active front surface of the chip or wafer to the passive back surface, a number of significant drawbacks arise in the process, so that chips which have been produced using the claimed process are disproportionately expensive. This results, inter alia, from the fact that the trenches which are to be produced in the known process are significantly wider than would normally be encountered during standard division or dicing of a wafer. As a result, this means that the distances between the chips or the integrated circuits have to be relatively great, so that there is space for fewer chips on a wafer. If only for this reason, the known process provides only a relatively low chip yield from a semiconductor wafer. Furthermore, the production process as proposed is also relatively slow. On the one hand, this is in particular because the trenches have to be ground in sequentially, and secondly this is because during production of the trenches, what is known as the dicing saw can only operate at a relatively slow advance rate. Apart from all this, the dicing saws which have to be used are very expensive. A further significant problem of the process described in WO 99/40624 is that the terminal contacts are uncovered by dividing them when the trenches are being ground open. Dividing the terminal contacts in this way requires a very high level of dimensional accuracy, since otherwise at least part of the contact may be destroyed. However, even if accurate cutting of the terminal contact is achieved, it is not easy to produce a contact connection with the terminal contacts which have been uncovered in this way. The reasons for this are in particular that in accordance with the prior art contact is to be made by depositing contact tracks on the walls of the trenches, which are inclined in the wafer, but uniform and therefore targeted deposition is only possible perpendicular to the deposition direction. Further processes for making through-contact with chips are also described in “Future Systems-on-Silicon LSI Chips”, Koyanagi, M; Kurino, H; Lee, K. W.; Sakuma, K, IEEE Micro, July-August 1998, pp. 17-22, WO98/52225 and DE 197 46 641. However, these processes are unsuitable for the packaging of optical chips.
In view of this background, the present invention is based on the object of avoiding the above-mentioned drawbacks of the prior art, in order in this way to provide a less expensive and simpler process for producing electrical contact connections during the packaging in particular of optical chips.
Very surprisingly, this object is achieved by a process for producing electrical contact connections for at least one component which is integrated in a substrate material, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, wherein an optically transparent covering is applied to the first surface region, and at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region is produced, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages, wherein before the at least one contact passage or the at least one contact location is produced, the covering is applied, and wherein the provision of the second surface region comprises the step of thinning the substrate material, and in particular the contact passages, starting from the second surface region, substantially directly adjoining the terminal contacts.
Furthermore, the invention also is achieved by a process for mounting at least one component in a housing comprising the steps of: fabricating at least one semiconductor component in a substrate material which comprises a first surface region, which lies opposite a second surface region, at least one terminal contact being arranged at least partially in the first surface region for each integrated circuit, carrying out the process as claimed in one of the preceding claims for producing a substrate material which is provided with a first covering on the first surface region and has at least one contact location in the second surface region, applying a second covering to the second surface region. A device which can be produced in particular using one of the inventive processes, comprises an integrated circuit arrangement, comprising a chip, which includes a substrate, at least one terminal contact and, on one side, an active layer which comprises the circuits of the chip, wherein a covering of glass or transparent plastic is secured to one side of the chip, and the substrate is thinned on the opposite side, and the chip has a conductive passage which is introduced from a second side, which is opposite to the side which includes the active layer, of the first chip, and the covering having been secured before the thinning and introduction of the passage, there being an electrical contact between at least one terminal of the circuits of the chip and the conductive passage.
The invention advantageously proposes a process for producing electrical contact connections for at least one component which is integrated in a substrate material, the substrate material having a first surface region, at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, or in a direction which is substantially perpendicular to this region, in which process, in order to form at least one contact location in a second surface region which is to be provided, above the respective contact passages, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced.
Very advantageously, it is in this way possible for a contact location to be produced on the to the terminal contact and therefore a contact location which is electrically connected to the terminal contact can be produced on that side of the substrate material which is remote from the active surface, it being possible to dispense both with trenches which run along the substrate material and with a lateral contact which leads around the component in accordance with the prior art.
According to an advantageous refinement of the process, the substrate material, in which the components are integrated, is divided into chip regions which are to be defined, on the basis of the arrangement of the components. According to the invention, the contact passages which are provided for the contact connection can be introduced into the substrate material in various ways. Firstly, there is provision for contact passages to be arranged in the substrate material, in such a manner that they are introduced into the substrate material substantially adjacent to the terminal contacts. Secondly, however, the invention provides for the contact passages to be introduced into the substrate material in such a manner that, in particular starting from the second surface region, they substantially directly adjoin the terminal contacts. The latter variant offers the advantage in particular that there is no need to relay the terminal contacts on the first surface region. In this context, relaying means that a contact track, which produces an electrical connection between the terminal contact and the contact passage, is produced on the first surface region. Introducing the contact passage next to the terminal contact may be advantageous in particular if parts of active regions of the component integrated in the substrate material are located, for example, beneath the terminal contact.
According to a further advantageous embodiment of the invention, the contact passages or at least parts thereof are introduced into the substrate material at locations where, in a subsequent process step, the substrate material is cut into different chip regions. Since, according to the invention, it is possible to use a contact passage to produce more than just one electrical contact connection, it is therefore possible, in a simple manner, to construct a contact connection to a plurality of terminal contacts on, for example, different chip regions or for different components via the individual contact passages.
According to the invention, it is extremely advantageously possible to produce the contact passages in various ways. By way of example, according to one embodiment of the invention, the contact passage is provided by doping the substrate material. In this case, it is preferable to use chemical elements from the third and fifth main groups of the periodic system, with ion implantation or thermal diffusion of the elements into the substrate material preferably being used as doping processes for production of the contact passages.
According to a further preferred embodiment of the invention, the production of the contact passages comprises in particular the provision of openings. Holes have the advantage in particular that not just one contact connection can be laid through them, but rather—depending of course on the size of the opening—a plurality of contact tracks can be laid in the opening. It is advantageous for the openings or the contact passages to be in particular electrically insulated in the lateral direction with respect to the substrate material during production, but also in general during the production of contact passages.
In the context of the invention, a very wide range of processes can advantageously be used to produce the contact passages or the openings. For example, the passages for the contacts to lead through the semiconductor material or substrate material may preferably be produced either with the aid of a dry-etching process and/or a wet-etching process.
According to the invention, the dry-etching process generally comprises photolithographic patterning of the surface which is to be processed and an anisotropic dry etch. The “ASE (Advanced Silicon Etching) Process”, which is based on SFe radicals, or the “Bosch Process” is preferably used. A suitable wet-etching process is etching by means of KOH solution. The latter process in particular has cost benefits.
As has been stated, within the context of the invention it is possible for the contact passages which are to produce a through-con tact engagement from one surface region to the other surface region of the substrate material or of the wafer to be arranged at various locations in the substrate material or in the chip or in the wafer. Accordingly, according to the invention it may be necessary, in order to produce the electrical contact connection or contact connections, for the terminal contacts which have been laid in the surface region to be relayed to the associated contact passages. The relaying may in this case be effected by standard photolithographic patterning and corresponding etching and the deposition of electrically conductive material. According to the invention, it is advantageously possible to use a very wide range of known deposition or coating processes. Examples of these are sputtering, CVD and/or PVD deposition and/or electroless deposition of preferably aluminum, copper or nickel.
If the contact passages according to the invention are produced, for example, by openings, these openings can also be filled, using the above-mentioned processes, with electrically conductive materials, such as for example aluminum and/or copper and/or nickel and/or similar metals, in order, in this way, to produce a contact connection from the first surface region to the second surface region. At the same time, contact locations are produced in the second surface region as a result of the production of contact passages, it being possible for at least one soldering bead to be applied to the contact location in order to produce in particular external, i.e. outwardly directed contact connection. As a result, it is possible, in a simple way, for example to produce a terminal contact for a printed-circuit board.
Depending on the connection locations of said printed-circuit board or the like, it is advantageously also possible to provide for relaying of the contact location created on the second surface region.
Particularly if a plurality of conductor tracks are laid through only one contact passage, the process according to the invention offers the possibility of filling the remainder of the contact passage or of the openings which have been provided with conductor tracks with insulant, in order to insulate the contacts from one another. If the openings which have been filled in this way are subsequently divided into individual chips as part of the division of the wafer, it is in this way already possible to ensure lateral insulation of the individual chips.
In an advantageous refinement to the process according to the invention, the covering is preferably provided in the form of a glass or a comparable plastic. A glass or a plastic is recommended in particular if optically active components are to be covered. According to one embodiment of the invention, the connection between the covering and the first and/or second surface region takes place with the aid of an adhesion promoter. However, particular mechanical or optical properties can also be achieved, for example, with a covering which comprises a glass-plastic composite material or a layered material.
According to the invention, the term surface region is to be understood as meaning a substantially planar surface or a region of the substrate material which comprises the terminal contacts which are arranged on the semiconductor material of the substrate material or may project out of this material and which may lie at least in part on the inter alia one passivation layer which adjoins the substrate or semiconductor material of the substrate material.
The adhesion promoters used may advantageously be epoxy resins and/or waxes and/or sol-gels. The use of wax offers the advantage in particular that the connection created in this way can be removed again without the substrate material being destroyed. The production of a connection between the covering, which is preferably made from glass, and the substrate material on the basis of a sol-gel has proven advantageous in particular since the gel has a relatively high transparency, and furthermore forms a highly temperature-stable connection with glass in particular. Since the sol-gel is itself vitreous, i.e. can be spoken of as itself being glass, it has particularly good matching or transition properties with respect to glass in particular.
A further embodiment of the invention which is advantageous in this context consists in replacing the adhesion promoter for joining the covering to the substrate material by a process known as bonding. Anodic bonding is preferably advantageously suitable. In general, bonding requires a substantially planar surface or a planar surface region of the substrate material. Therefore, it is advantageously recommended, if the topographic differences on the substrate material or wafer are too great, for an oxide layer to be deposited on the wafer surface or the surface regions of the substrate material first of all. Examples of processes which can be used for this purpose are the “LTO (Low Temperature Oxide)” and the “TEOS (Tetraethyl Orthosilicat)” processes. Furthermore, as part of the bonding of the covering to the substrate material, the deposited oxide layer is planarized with the aid of a chemical-mechanical polishing process, in such a manner that the microplanarity and macroplanarity for the bonding are provided. Depending on whether the contact passages are produced starting from the first surface region or from the second surface region which is to be provided, the sequence of process steps “application of a covering” and “production of at least one contact passage” varies according to the invention.
In an advantageous variant of the process according to the invention, before the contact passages are introduced into the substrate material, first of all the covering is applied to the first surface region of the substrate material, the active modules preferably being located in the first surface region. The application of the covering offers the advantage that the components located in the substrate material are protected and the arrangement acquires additional stability. The substrate material or the semiconductor wafer can then be thinned on the back surface, for example mechanically by means of a grinding process, without losing its mechanical stability, which is ensured by the covering. The through-contact making, i.e. the production of at least one contact passage in the thinned substrate material, then takes place in accordance with one of the possibilities described above on the basis of the production of doping passages or with the aid of openings provided with conductive material. It should be noted that, particularly in the procedure described above, through-contact can be made with the terminal contacts, which lie on the active upper side, starting directly from the second surface region which has been provided via the respective contact passages, therefore, as it were, from behind.
A further variant of the process for producing contact passages or contact connections according to the invention consists in the fact that blind passages can be produced in the substrate material even before the covering has been applied and the substrate material or wafer has been thinned on the back surface, these blind passages starting from the front surface or from a first surface region. The term blind passages has been selected because these passages do not generally extend as far as the second surface region. If the blind passages are formed in the form of blind openings, i.e. in the form of openings whose depth is initially less than the thickness of the substrate material, an insulator for electrically insulating the hole with respect to the substrate material is generally applied to the walls of the blind holes and laid or deposited on these contact tracks, and/or the blind holes are then filled with a conductive material. Following this, a covering is applied to the first surface region of the wafer or substrate material. On account of in particular the stabilizing action of the covering with respect to the substrate material, it is now possible, starting from the passive side of the substrate material and with the aid of a preferably mechanical grinding process, to thin the substrate material. The thinning continues at least as far as the region of the blind hole, until the conductor tracks or conductive materials which have been introduced into this hole are uncovered, so that through-contact is formed in the substrate material or wafer or chip or substrate.
A corresponding procedure is also employed if the contact passages are produced on the basis of doping passages which do not initially penetrate all the way through the substrate material.
As has already been stated in the introduction, a process for mounting at least one component in a housing also lies within the scope of the invention. In this process, first of all at least one semiconductor component is produced or provided in a substrate material, which comprises a first surface region which lies opposite to a second surface region, at least one terminal contact being at least partially arranged in the first surface region for each integrated circuit. Furthermore, a substrate material which is provided with a first covering on the first surface region and has at least one contact location is produced in the second surface region using the process proposed above, and then a second covering is applied to the second surface region. With the aid of the second covering, it is advantageously possible for the semiconductor component to be protected against damage from the outside. Furthermore, the second covering also makes it possible, if the first covering has been applied to the first surface region, for example using a wax, for this first covering to be removed again for further processing steps without the chip or wafer, which if possible has been thinned, losing stability.
In an advantageous refinement of the subject matter of the invention, openings are introduced into the second covering in particular at locations where the terminal contacts of the semiconductor component, which have been laid on the second surface region, are located. Of course, it is possible for the openings which penetrate through the covering to be introduced into the covering layer even before the actual application. In a similar manner to the openings in the substrate material, the openings in the covering may also be filled with conductive material, such as for example aluminum, copper or nickel, in order in this way to produce a connection between the terminal contacts which have been laid and the outside.
According to the invention, it is, of course, advantageously also possible by suitable measures to lay the contact locations which are situated on the second surface region in such a way that they match the position of the openings passing through the second covering. In a corresponding way, the contact locations which have been laid through the covering openings can be laid further on the uncovered side of the covering.
Furthermore, a further development of the process according to the invention, if the substrate material or the semiconductor wafer comprises a plurality of components or integrated circuits, relates to the formation of isolation trenches between the components or integrated circuits. These trenches are preferably used to electrically decouple or isolate the individual components on the various chip regions. For this purpose, the trenches which have been created may furthermore be filled with an insulant. An example of a possible insulant is epoxy resin or BCB (benzocyclobutene). During the process, the isolation trenches are arranged on the semiconductor wafer in such a manner that, by means of a substantially symmetrical distribution of the isolation trenches, the wafer is divided into various chip regions of substantially identical size. In this way, it is very advantageously possible for the components lying on the chips also to be laterally sealed or insulated with respect to the outside.
As is already apparent from the above description, both the laying of the terminal contacts and the mounting of the components in a housing can, according to the invention, take place while still part of the wafer assembly.
Furthermore, it is also within the scope of the invention to provide a process for fabricating integrated circuits which is also suitable in particular for the fabrication of integrated circuits which are of multilayer structure. The process is in particular also suitable for the fabrication of multilayer integrated circuits or for the mounting of circuits which have been fabricated in accordance with the invention on suitable bases.
In many cases, integrated semiconductor circuits which, alone or together with other circuit components or other circuits, are applied to dedicated semiconductor substrates or semiconductor wafers, are used to miniaturize electronic components. A semiconductor substrate of this type having an electronic component or preferably at least one electronic circuit constituent is to be referred to in the text which follows as a chip for the sake of simplicity. Particularly in the fields of optoelectronics and micro-op to-electromechanical systems (“MOEMS”), there are numerous possible applications for circuit arrangements of this type. For example, optical or sensor components of this type and non-optical components can be stacked on top of one another. In particular, numerous possibilities result from the combination of CMOS and CCD chips.
Furthermore, CMOS technology is generally used for logic and processor applications. However, with CMOS chips of this type it is difficult to produce optical or sensor components. By joining an optical CCD chip with a CMOS chip it is possible, for example, for a large-scale integrated memory circuit to be advantageously integrated in the imaging unit. It is also possible for the CCD chip to be combined with a processor module for data compression, so that then only compressed data have to be processed in the further electronics of the appliance.
A range of processes for mounting electronic modules on associated bases are known from the prior art, as described, for example, in U.S. Pat. No. 6,171,887. In these processes, the chip is mounted with its active side facing toward the base. In the process which is disclosed in U.S. Pat. No. 6,171,887, soldering beads are applied to the contact surfaces of the chip. This side of the chip is then covered with an insulating protective layer, the thickness of which is such that even the soldering beads are completely covered. The protective layer is ground and polished in a further step, until the contacts are partially uncovered. The chip which has been treated in this way is then joined to the base by partial melting of the electrodes and of the protective film, the electrodes making contact with associated contact surfaces of the base. This process cannot generally be used to produce stacked components, which on account of their ability to be handled independently are also referred to below as electronic modules, with optoelectronic elements, since the side which has an optical or sensor activity has been covered by the base or the element joined to the optical component.
Accordingly, the invention provides a process for fabricating integrated circuits in which a wafer which has a substrate, at least one terminal contact and, on a first side, an active layer which comprises the circuits of a chip, is used. The process comprises the following steps:
Securing a transparent covering to the first side of the wafer, thinning the wafer on an opposite side from the side which includes the active layer, introducing at least one conductive passage, which extends substantially perpendicular to the surface of the first side, from a second side of the wafer, which second side is the opposite side to the side which includes the active layer, into the wafer, and producing an electrical contact between at least one terminal of the circuits of the wafer and the conductive passage.
In this way, this process can also advantageously be further developed for the fabrication of integrated circuits which are of multilayer structure with at least two chips, each of which has at least one terminal contact and, on a first side, an active layer which comprises the circuits of the chip. For this purpose, the process provides for a covering to be secured to one side of a first one of the at least two chips. To produce a contact from one side of the chip to the other, a conductive passage, which extends in a direction which is substantially perpendicular to the surface of the chip or to the first side of the chip, is introduced into the substrate. On the other side of the chip, a contact surface is produced, which is electrically connected to the conductive passage. Likewise, at least one terminal of the circuits of the first chip is connected to the conductive passage on the first side. Then, the first chip and at least one further chip are secured onto one another in such a manner that an electrical contact is produced between the electrically conductive passage of the first chip and at least one corresponding terminal surface of the other chip.
Referring to the German patent application bearing the title “Process for making contact with and housing integrated circuits”, the subject matter of this application is hereby incorporated in the present invention. This reference applies in particular to the production of a conductive passage through a wafer or a chip.
The at least one conductive passage can be produced in various ways. According to one embodiment of the process, the passage is produced by introducing a hole which is then filled with a conductive material, such as for example a metal or a conductive epoxy.
It is also possible to produce the passage by introducing a suitable doping. The doping may be carried out, for example, by ion implantation or thermal diffusion.
According to an advantageous refinement of the process, the first chip is thinned on the second side, which is the opposite side from the first side including the active layer. If the hole is produced with a depth which is initially less than the thickness of the substrate, a blind hole is formed. Likewise, under certain circumstances the penetration depth of the doping may not be sufficient to produce a conductive passage extending from one side to the other side of the substrate. According to the refinement, the thickness of the substrate, at least in the region of the hole or the doping, is made less than the depth of the hole or the penetration depth of the doping atoms by the thinning step, so that a through-contact is formed through the substrate. In this case, the holes are preferably produced by means of etching and therefore form etching pits in the substrate.
Features of further advantageous configurations of the process according to the invention are also given herein.
The process according to the invention allows a chip to be joined to a base, in particular a further chip, in such a way that the base faces the back surface of the chip and, in addition, electrical connections are produced between the top side or active side of the chip and the base. For this purpose, the chip is provided with conductive passages which extend from the top side to the underside. The passages are provided with a conductive layer or filled with a conductor, in order to produce a through-contact.
Alternatively, a surface region of the chip can be doped, so that the doping forms a conductive region which can extend as far as the opposite side and thereby forms a conductive passage. The contacts which have been led through the chip with the aid of the conductive passages can then be provided with soldering beads, by means of which the chip is joined to the base. The joining of the chips may be carried out, for example, in a similar manner to that described in U.S. Pat. No. 6,171,887. Alternatively, the contacts may, of course, also be applied to the other chip or to both.
The passages which are used to lead the contacts through the semiconductor material may inter alia be produced by means of a dry-etching process. In particular an anisotropic dry-etching process, such as for example the “ASE process” based on SF6 radicals, is suitable for this purpose. In this context, an inexpensive alternative is anisotropic etching using KOH solution, which is recommended for Si wafers with a (100) orientation. Of course, combinations of the above-mentioned processes can also be used to produce the passages. Furthermore, these processes can also be employed to produce isolation trenches, in which case the isolation trenches can, for example, be etched in one step together with the passages. However, it is also possible, inter alia, in each case to use a different one of the above-mentioned processes or a different combination of these processes to etch the isolation trenches and to etch passages.
The module which is to be connected to the optical or sensor chip for its part requires through-contacts for connection to the circuit board or to a further chip. Therefore, this chip is prepared in a similar way to the optical or sensor chip above, the module having two sets of contact surfaces. In terms of orientation and position, one set of contact surfaces fits together with the corresponding through-contacts of the optical chip, while the second set is used to produce through-contacts to the circuit board or the next module down.
During the process steps according to the invention, the modules are preferably still joined to the wafer, i.e. have not yet been separated from the wafer during production.
According to a preferred embodiment of the invention, the wafer is adhesively bonded on the optical side to a transparent covering, for example a thin pane of glass. In this way, the modules on the wafer are protected and the arrangement acquires additional stability. The adhesive used may be a suitable epoxy resin. The wafer can then be mechanically thinned on the back surface by a grinding process, the mechanical stability continuing to be ensured by the transparent covering. The through-contacts can in this case be produced in two different ways. In a first variant of the process, the top side of the optical chip is photo lithographically patterned and the etching pits are introduced. In this variant, the conductive passages are located next to the contact surfaces or bonding pads for connection of the chip. The etching pits are then filled with a conductor and a conductor track is applied from the etching pit to the bonding pad. The transparent covering can then be applied, and after this the wafer is thinned on the back surface until the conductive fillings of the etching pits emerge on the back surface.
According to another alternative, the covering is applied in advance and the wafer is thinned. The photolithographic patterning and the etching in this case take place from the underside of the chip, the etching pits being located beneath the bonding pads situated on the top side and being etching until the bonding pads are uncovered.
The non-optical chips are prepared in a similar way; in this case too, the process may be carried out while the chips still form part of the wafer assembly. The non-optical chips, to which the optical chips are applied, initially, as mentioned above, have two sets of contact surfaces or bonding pads which are used for through-contact or for connection of the optical chip or a chip above it. The wafer with the non-optical chips is likewise thinned, but without endangering the stability. The thinned wafer is then photolithographically patterned and etched through at the locations at which through-contact is to be made. As in the case of the optical chips, these process steps of patterning and etching can be carried out both from the top side or active side and from the underside. The passages through the wafer which are formed by the etching pits are then metallized or filled with a conductor. If the passages are located next to the associated contact surfaces, the contact surfaces are connected to the filled passages by conductor tracks. The contact surfaces are provided with soldering beads on both sides. If appropriate, it is also possible to dispense with the step of applying these contacts which are intended for connection of the optical chip or chips above it, provided that fusible contacts of this type are already located on the associated contacts of the chip above.
The chips which have been prepared in this way can then be connected to one another. If the chips are arranged in the same way on the wafers, so that the corresponding contacts come to lie above one another when the wafers are placed on top of one another, the chips can be connected while they are still joined to the wafer. Otherwise, the wafer with the smaller chips is sawn up by means of a dicing saw and the chips are then placed onto the other wafer. Then, the two wafers or the chips are joined to the wafer by melting or reflow of the solder of the soldering beads, so as to produce contacts between the chips. To join the wafers or chips to one another, it is preferable to use a high-melting solder which has a higher melting point than the solder used to connect the circuit board. This prevents the connections between the chips of the chip stack from being broken again during connection to the circuit board. By way of example, pure tin can be used to connect the chips to one another. In a final step, the chips are cut up using a dicing saw.
During the preparation of the chips on the wafers, after application of the transparent covering they can be packed using various wafer-level packaging processes.
The process according to the invention also allows more than two layers of components or chips to be joined, in which case the correspondingly prepared parts are joined to one another either simultaneously or in succession.
If the elements of the multilayer integrated semiconductor arrangement are successively secured to one another in accordance with one exemplary embodiment, the mechanical stability which is additionally imparted to the wafer or chip which was in each case attached last on account of the assembly of the elements allows it to be thinned further in relative terms. This exemplary embodiment is therefore based on the wafers or chips being successively secured to one another, then being thinned. The consequence of this is that the holes or etching pits in the chips have to be etched through in relative terms a thinner substrate, and therefore their diameter remains smaller.
Furthermore, it should be noted that the top chip of the stack produced using the process does not have to be an optical chip. Rather, the invention can be used to join any desired semiconductor modules to one another to form compact three-dimensional stacks. By way of example, the process is particularly suitable for stacking memory modules which can be joined to one another without an insulating interlayer between the chips. It is also possible for integrated circuits on different substrates, such as Ge, Si and GaAs, to be advantageously combined with one another in a space-saving manner. It is also possible for a very wide range of sensor chips to be combined with further modules using the process. The sensor chips may, for example, include radiation, pressure, temperature or moisture sensors. It is also possible to use chemically sensitive sensors which respond to certain gases or liquid constituents.
A transparent covering may also advantageously be patterned. In this way, by way of example, optical elements, such as prisms, gratings or optical filters, can be integrated in the covering.
If transparent coverings are not supposed to be or do not have to be present on the top chip, for example if the top chip is not an optical chip, the chip can also be secured to a base by means of a detachable wax, which imparts additional strength during the production process, in particular during the thinning. Alternatively, the covering may also be fixed, for example, by means of an epoxy resin during the production process, and this epoxy resin can be detached again under the action of UV light.
According to the processes of the invention, the invention also covers a multilayer integrated circuit arrangement which comprises at least two chips arranged above one another, which in each case have a substrate, at least one terminal contact and, on one side, an active layer which comprises the circuits of the chip. At least one of the chips of the circuit arrangement advantageously has a conductive passage, there being electrical contact between at least one terminal of the circuits of the chip which has the passage and the conductive passage, on the one hand, and a terminal surface of the further chip having the conductive material, on the other hand.
The fully assembled multilayer integrated semiconductor arrangement may additionally be provided with a protective housing. A multilayer integrated circuit arrangement of this type, which has been produced using the process according to the invention and has been provided with an advantageous protective housing during production, forms a housed multipackage comprising at least two chips which are arranged above one another and, one side, each have at least one terminal contact and an active layer which comprises the circuits of the chip and are at least partially surrounded by a housing, wherein a covering is secured to one side of a first one of the chips, the substrate of the chip is thinned on the opposite side from the side which includes the active layer, and the chip has a conductive passage which is introduced from this side of the first chip, which is the opposite side to the side which includes the active layer, and the covering having been secured before the thinning and the introduction of the passage, there being an electrical contact between at least one terminal of the circuits of the chip, which includes the passage and the conductive passage, on the one hand, and the terminal surface of a further chip having the conductive passage, on the other hand.
According to the inventive processes, the invention also covers a device which preferably includes a component which has a sensor or optical or corresponding external activity, the component being protected or insulated with respect to the outside by means of two coverings on its first and second surfaces and a lateral insulation.
The present invention is described in detail below with reference to individual exemplary embodiments. In this context, reference is made to the appended drawings; in the individual drawings, identical reference numerals denote identical components, and in the drawings:
In connection with the following detailed description of preferred embodiments, reference is made first of all to an exemplary embodiment which is illustrated in
The optical chip or sensor chip shown in
After the wafer has been prepared, first of all, in a subsequent step of the process, as “shown with reference to
In a subsequent etching procedure, etching pits or blind openings 17 are etched into the substrate, the passivation layer 13 protecting the substrate from being etched outside the openings 16. For further processing, a depth in the range from approx. 50 to 200 urn is sufficient for the blind openings, given an overall substrate thickness of approx. 500 jam. One suitable process for producing the etching pits is anisotropic etching of an Si(100) substrate using KOH, during which process etching pits with an aperture angle of approximately 70° are formed, the diameter or cross section of the pits on the active surface being dependent on the etching depth and/or the aperture angle.
Then, contact is made between the etching pits and the bonding pads.
Then, contact is made between the etching pits and the bonding pads.
As an alternative to what is illustrated in
As the next step, the top side 14 of the chip 1 is provided with an optically transparent covering 20 in order to protect the optically sensitive layer 11. The result of this production phase is shown in
To produce a contact through the chip, the underside or inactive side 22 of the chip is ground down until the conductive fillings 19 of the etching pits 17 are reached and, as a result, contact locations or contact surfaces 23 are formed on the underside 22 of the chip. In this case, the contact location may, according to one of numerous possible embodiments, have a width, for example, of approx. 50 μm. The assumption in this case is that the wafer has a total thickness of, for example, approx. 500 μm and the blind opening has a penetration depth of slightly more than 200 μm, so that after the substrate has been thinned, the tip of the blind hole is uncovered up to a width of 50 μm. This production state is shown in
In this context, it should be noted that it is advantageous if the wafer is thinned until it is as thin as possible, in particular even thinner than in the above example, since as a result in particular the cross section of the opening and the hole depth can be kept very small, the stability of the wafer being ensured by the covering or the glass 20.
The wafer is now in a form which is such that the bonding pads lie on the passive side of the wafer. It can then be processed further in the same way as a non-sensor chip, e.g. using all known wafer level packaging (WLP) processes.
Therefore, this process allows the range of WLPs for non-sensor chips to be widened considerably. The chips which have been provided in this way with laid contact locations (23) can then, in the housed or open state, be made contact with by conventional SMT (Surface Mounted Technology) on a board or on a printed-circuit board.
To this extent,
For possible joining of the chips to a further module below them, it is expedient, for example, to apply soldering beads which are joined to the contact surfaces. In the most simple form, which is shown in
To move one step closer to the housing of the chip or mounting of the chip in a housing while still joined to the wafer, a further covering 27 is applied to the underside 22 of the chip. A chip of this type, which is “sandwiched” between two coverings 20 and 27, is shown in
If the substrates of the chips which are to be fitted together have different coefficients of thermal expansion or are at different temperatures in operation, it is also recommended to use an interlayer between the chips, which interlayer, on account of its flexibility, can reduce the temperature stresses which are produced between the substrates. The embodiment shown in
By way of example, in the case of the flexible covering shown in
In accordance with the exemplary embodiment described below, the top side 14 of the chip 1 which has been prepared as shown in
Accordingly, the top side 14 of the chip 1 which has been prepared as shown in
As has already been mentioned, after the etching and/or grinding, the thickness of the wafer should be as low as possible.
Then, as shown in
The edges or walls of the etching pits or openings 30 are then insulated with respect to the substrate 1 by means of conformal plasma oxide deposition. The insulating layer is denoted by 32. An insulation 32 of this type is in principle optional. However, in many cases it is required if the substrate is highly doped, in order to avoid short circuits. To this extent, suitable processes are the LTO (Low Temperature Oxide) process based on SiH4 or a process based on TEOS oxide (TEOS, tetraethyl orthosilicate). The plasma oxide deposition is generally followed by an etch-back step, in order, inter alia, to uncover the back surface of the bonding pads 12 again. Then, as can be seen from
With the fillings 31 produced in the substrate in this way, the procedure can then continue in a similar manner to that described in the previous exemplary embodiment. Therefore, the soldering beads 24 may, as shown in
As an alternative to filled etching pits, the regions 31 in the figures may also represent conductive doped regions which likewise form a through-contact through the substrate.
Likewise, in the same way as for the production of the etching pits for the conductive passages, the trenches 35 can also be produced using an anisotropic dry-etching process, for example by means of an ASE process or by anisotropic etching with KOH solution. In general, the etching of the etching pits and of the isolation trenches 35 can also be carried out by a combination of various etching processes. For example, an etching pit or an isolation trench may, for example, be produced in a first step by means of wet-etching and then further by means of anisotropic dry-etching. In general terms, it is possible to use both the same etching process and different etching processes or combinations of the etching processes to produce trenches and etching pits. For example, one possible embodiment provides for wet-chemical pre-etching of the isolation trenches, followed by the joint etching of surface regions for isolation trenches and conductive passages by means of anisotropic dry-etching. Therefore, the combination of various etching processes allows the shape, for example the steepness of the walls, and also the size and depth of the etched structures to be advantageously controlled.
The modules below are prepared in a similar manner to the preparation of the upper chip described above. Possible embodiments are shown in the cross-sectional views presented in
For this purpose, the chip is thinned on the passive side as much as is allowed by the stability constraints during the production process. If the chips are still joined to the wafer, an unsupported wafer can be thinned to approximately 200 urn to 300 μm.
In accordance with the embodiment shown in
If there is to be no further level of the chip stack, i.e. the chip 2 is the bottom chip in the stack, the solder used for the soldering beads 33 may advantageously have a lower melting point than the material used for the other soldering beads 24. As a result, the assembled chip stack can be secured to a circuit board or some other base by melting the soldering beads 33 without the other soldering beads 24 melting.
In this case too, the passages 28 are filled with a conductive filling 29 in order to make contact through the passages 28 located in the covering 27 all the way down to the underside of the covering. In this arrangement, it may be expedient for the redistribution of the contacts to be carried out in such a way that the lateral positions of the contacts lying on the underside and top side of the chips match one another. In this way, it is possible for a plurality of chips 2 to be combined with one another in any desired way with regard to the order and number in a chip stack. This may be advantageous, for example, if a chip stack of this type comprises a plurality of memory modules. Furthermore, in this way a plurality of different variants which differ only with regard to the number of stacked memory modules can be produced from the same individual modules without unnecessarily high outlay.
Starting from an optical chip as illustrated, for example, in
Then, the layer 45 is ground down until the soldering beads 24 project and are ground flat together with the layer, so that, as illustrated in
Moreover, when the chips are placed onto one another, a self-aligning effect results from the surface tension of the molten solder. On account of the surface tension, the chips are drawn in one direction, such that the lateral spacing of the contact surfaces 25, which have been connected to one another by means of the solder, between the chips is minimized.
A further exemplary embodiment of the process according to the invention is explained below with reference to the diagrammatic cross sections shown in
In accordance with
Then, in a further step, through-contacts are produced in the chip 2 which has been fitted on, as described with reference to
These steps can be repeated with any desired number of components individually or joined to the wafer, resulting in the formation of a chip stack as diagrammatically depicted in
All the steps which have been described hitherto can be carried out while the chips still form part of the wafer. Therefore, it is additionally possible to integrate various wafer level packaging processes, at least partially or in individual steps, in the process according to the invention.
Furthermore, the bonding or bonding-together or connection of the chips to form a stack can also be carried out while they are still joined to the wafer. A precondition for this to take place is for the chips to be arranged in the same way in the lateral direction on various wafers, so that the chips of a stack come to lie on top of one another when the wafers are placed s onto one another.
The chips joined to the wafer which have been stacked on top of one another can then be separated using a dicing saw.
By contrast, the chips 2 and 3 below it have through-contacts which have been produced using the process according to the invention. The conductive fillings 31 of the through-contacts of the chips 2 and 3 are connected to corresponding bonding pads 25 of the chip * 1 or 2 which respectively lies above them via soldered joints 39. Between the chips there are interlayers 45 which connect the chips to one another and can serve as flexible compensation layers in order to reduce thermal stresses produced between the chips.
On the other hand, in this embodiment the underside of the bottom chip 3 of the chip stack 6 is not sealed. Consequently, the chip stack 6 can be used further as in what is known as flip-chip technology and can be connected to contact surfaces of the substrate provided, for example to a circuit board, by melting the soldering beads 24. After the chip stack which has been assembled while still joined to the wafer has been separated from the stack of wafers, the multilayer integrated module or chip stack 6 formed in this way can be sealed with an epoxy resin cladding 40.
In this case, the optical chip 1 is prepared in accordance with the process steps shown in
In this exemplary embodiment, the underside of the chip stack is also provided with a covering, which serves as a flexible interlayer or compensation layer between the bottom chip of the stack and the base, on the one hand, and/or as a protective packaging, on the other hand.
The multilayer integrated circuit arrangements which are described with reference to
The contacts are redistributed on the underside 22, as shown in
After completion, a chip stack produced using one of the exemplary embodiments described above can be processed further using a known process. For example, the chip stack or the multilayer semiconductor arrangement can be joined directly to a circuit board using SMD technology processes or may be cast into a suitable housing for SMD processes or through-hole techniques.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5244817||Aug 3, 1992||Sep 14, 1993||Eastman Kodak Company||Method of making backside illuminated image sensors|
|US5254868||Jul 22, 1991||Oct 19, 1993||Seiko Instruments Inc.||Solidstate image sensor device|
|US5330918||Aug 31, 1992||Jul 19, 1994||The United States Of America As Represented By The Secretary Of The Navy||Method of forming a high voltage silicon-on-sapphire photocell array|
|US5468681||Jun 15, 1994||Nov 21, 1995||Lsi Logic Corporation||Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias|
|US5610431||May 12, 1995||Mar 11, 1997||The Charles Stark Draper Laboratory, Inc.||Covers for micromechanical sensors and other semiconductor devices|
|US5682062||Jun 5, 1995||Oct 28, 1997||Harris Corporation||System for interconnecting stacked integrated circuits|
|US5695933||May 28, 1993||Dec 9, 1997||Massachusetts Institute Of Technology||Direct detection of expanded nucleotide repeats in the human genome|
|US5766979||Nov 8, 1996||Jun 16, 1998||W. L. Gore & Associates, Inc.||Wafer level contact sheet and method of assembly|
|US5807783||Oct 7, 1996||Sep 15, 1998||Harris Corporation||Surface mount die by handle replacement|
|US5814889||Jun 5, 1995||Sep 29, 1998||Harris Corporation||Intergrated circuit with coaxial isolation and method|
|US5965933||May 28, 1996||Oct 12, 1999||Young; William R.||Semiconductor packaging apparatus|
|US6114191||Dec 3, 1998||Sep 5, 2000||Intersil Corporation||Semiconductor packaging method|
|US6171887||May 4, 1999||Jan 9, 2001||Kabushiki Kaisha Toshiba||Semiconductor device for a face down bonding to a mounting substrate and a method of manufacturing the same|
|US6338284||Feb 12, 1999||Jan 15, 2002||Integrated Sensing Systems (Issys) Inc.||Electrical feedthrough structures for micromachined devices and methods of fabricating the same|
|US6384353||Feb 1, 2000||May 7, 2002||Motorola, Inc.||Micro-electromechanical system device|
|US6393183||Aug 17, 1999||May 21, 2002||Eugene Robert Worley||Opto-coupler device for packaging optically coupled integrated circuits|
|US6448168||Apr 14, 2000||Sep 10, 2002||Intel Corporation||Method for distributing a clock on the silicon backside of an integrated circuit|
|US6461888||Jun 14, 2001||Oct 8, 2002||Institute Of Microelectronics||Lateral polysilicon beam process|
|US6489675||Apr 13, 2000||Dec 3, 2002||Infineon Technologies Ag||Optical semiconductor component with an optically transparent protective layer|
|US6501182||Jun 25, 2001||Dec 31, 2002||Murata Manufacturing Co., Ltd.||Semiconductor device and method for making the same|
|US6503793||Aug 10, 2001||Jan 7, 2003||Agere Systems Inc.||Method for concurrently forming an ESD protection device and a shallow trench isolation region|
|US6515355||Sep 2, 1998||Feb 4, 2003||Micron Technology, Inc.||Passivation layer for packaged integrated circuits|
|US6541987||Aug 30, 1999||Apr 1, 2003||Advanced Micro Devices, Inc.||Laser-excited detection of defective semiconductor device|
|US6580858||Apr 30, 2001||Jun 17, 2003||Xerox Corporation||Micro-opto-electro-mechanical system (MOEMS)|
|US6703689||Jul 10, 2001||Mar 9, 2004||Seiko Epson Corporation||Miniature optical element for wireless bonding in an electronic instrument|
|US6911392||Aug 26, 2002||Jun 28, 2005||Schott Glas||Process for making contact with and housing integrated circuits|
|US20020028537||Aug 6, 2001||Mar 7, 2002||Farnworth Warren M.||Hermetic chip and method of manufacture|
|US20020135069||Mar 23, 2001||Sep 26, 2002||Wood Robert L.||Electroplating methods for fabricating microelectronic interconnects|
|US20030001240||Jul 2, 2001||Jan 2, 2003||International Business Machiness Corporation||Semiconductor devices containing a discontinuous cap layer and methods for forming same|
|US20030092243||May 4, 2001||May 15, 2003||New Mexico Tech Research Foundation||Method for anodically bonding glass and semiconducting material together|
|DE4314907C1||May 5, 1993||Aug 25, 1994||Siemens Ag||Method for producing semiconductor components making electrically conducting contact with one another vertically|
|DE19746641A1||Oct 22, 1997||Apr 1, 1999||Fraunhofer Ges Forschung||Verdrahtungsverfahren für Halbleiter-Bauelemente zur Verhinderung von Produktpiraterie und Produktmanipulation, durch das Verfahren hergestelltes Halbleiter-Bauelement und Verwendung des Halbleiter-Bauelements in einer Chipkarte|
|DE19846232A1||Oct 7, 1998||Mar 9, 2000||Fraunhofer Ges Forschung||Back face contacted semiconductor device, e.g. an ion-sensitive FET, is produced by metabolizing a back face contact hole for contacting a connection region or metallization level of a front face circuit structure|
|DE19918671A1||Apr 23, 1999||Nov 2, 2000||Giesecke & Devrient Gmbh||Vertikal integrierbare Schaltung und Verfahren zu ihrer Herstellung|
|DE19958486A1||Dec 4, 1999||Dec 7, 2000||Fraunhofer Ges Forschung||Verfahren zur vertikalen Integration von elektrischen Bauelementen mittels Rückseitenkontakt|
|EP0810659A2||May 9, 1997||Dec 3, 1997||Harris Corporation||Semiconductor packaging apparatus and method|
|JP2000195861A||Title not available|
|JP2001177081A||Title not available|
|JP2001351997A||Title not available|
|JPH0321859A||Title not available|
|JPH06113214A||Title not available|
|JPH10335337A||Title not available|
|WO1994017557A1||Jan 10, 1994||Aug 4, 1994||Hughes Aircraft Company||Thermally matched readout/detector assembly and method for fabricating same|
|WO1998052225A1||May 13, 1998||Nov 19, 1998||Chipscale, Inc.||An electronic component package with posts on the active surface|
|WO1999040624A1||Feb 3, 1999||Aug 12, 1999||Shellcase Ltd.||Integrated circuit device|
|WO2001080285A2||Apr 12, 2001||Oct 25, 2001||Honeywell International Inc.||Top illuminated opto-electronic devices integrated with micro-optics and electronic integrated circuits|
|1||"ShellCase Ultrathin Chip Size Package," 1999 International Symposium on Advanced Packaging Materials, Jerusalem, Israel, pp. 236-240.|
|2||A Plated Through Interconect Tecnology in Silicon. By Maha A. S. Jaafar and Denice D. Denton. Jul. 7, 1997.|
|3||Clearfield, et al., "Wafer-level Chip Scale Packaging: Benefits for Integrated passive Devices," May 2, 2000.|
|4||European Office Action dated Nov. 7, 2006.|
|5||European Search Report dated Feb. 23, 2010 for corresponding European Patent Application No. 02796172.1 (w/ translation).|
|6||Future Sytem-On-Silicon LDI Chips. By Mitsumasa Koyanangi et al. 1998.|
|7||Influence of the Grain Boundries and Intagrain Defects on the Performance of Poly-Si Thin Film Transistors. By Yoshihiro Morimoto et al. Jul. 7, 1997.|
|8||International Preliminary Exam Report dated Mar. 31, 2004 corresponding to International Patent Application No. PCT/EP02/09498.|
|9||Office Action dated Aug. 25, 2006 corresponding to Chinese Patent Application No. 02816578.0.|
|10||Office Action dated Feb. 23, 2006 corresponding to Korean Patent Application No. 7002747/2004.|
|11||Office Action dated Jul. 17, 2008 corresponding to Japanese Patent Application No. 2003-523003.|
|12||Office Action dated May 8, 2009 corresponding to Japanese Patent Application No. 2003-523003.|
|13||Office Action dated Sep. 26, 2007 corresponding to Japanese Patent Application No. 2003-523003.|
|14||Packaging of VCSEL Arrays for Cost-Effective Interconnects at <10 Meters; Hibbs et al., 1999.|
|15||Vertical Integration of Silicon Allows Packaging of Extremely Dense System Memory in Tiny Volumes Memory-Chip Stackes Send Destiny Skyward. By David Maliniak. Aug. 22, 1994.|
|16||Wafer-Level Processing Cuts Chip-Scale packaging Cost. By David Morrison. Oct. 18, 1999.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8188604 *||Mar 2, 2009||May 29, 2012||Oki Semiconductor Co., Ltd.||Semiconductor device incorporating preventative measures to reduce cracking in exposed electrode layer|
|US8564141 *||Mar 2, 2011||Oct 22, 2013||SK Hynix Inc.||Chip unit and stack package having the same|
|US20090230563 *||Mar 2, 2009||Sep 17, 2009||Shigeru Yamada||Semiconductor device and method of manufacturing the same|
|US20110272798 *||Mar 2, 2011||Nov 10, 2011||Hynix Semiconductor Inc.||Chip unit and stack package having the same|
|U.S. Classification||257/82, 257/E31.058, 257/777, 257/723, 257/81, 257/432|
|International Classification||H01L21/00, H01L27/15, H01L, H01L23/00, H01L21/44, H01L31/02, H01L25/16, H01L21/76, H01L31/0203, H01L21/3205, H01L23/12, H01L21/768, H01L23/52, H01L27/146, H01L23/485, H01L23/31|
|Cooperative Classification||H01L2224/0401, H01L25/0657, H01L27/14683, H01L2225/06541, H01L2224/13025, H01L2221/68363, H01L2225/06572, H01L27/14636, H01L2924/01039, H01L2225/06582, H01L2924/01013, H01L2924/01019, H01L2924/14, H01L2924/01006, H01L2924/01082, H01L2924/3025, H01L21/76877, H01L2924/0102, H01L2924/01068, H01L21/76898, H01L2924/01015, H01L2924/0106, H01L27/14634, H01L2924/01032, H01L23/3114, H01L27/14618, H01L31/0203, H01L24/13, H01L27/1469, H01L2924/3511, H01L2924/01005, H01L2924/01004, H01L24/14, H01L2924/01074, H01L2224/16, H01L2225/06513, H01L2224/13099, H01L24/94, H01L2924/01023, H01L2924/014, H01L2924/01058, H01L2924/01029, H01L2924/01078, H01L2924/01033, H01L2924/10329, H01L2924/01075, H01L2924/01057, H01L2224/13024, H01L2224/02372|
|European Classification||H01L21/768T, H01L23/31H1, H01L24/10, H01L24/13, H01L27/146A6, H01L27/146V, H01L31/0203, H01L24/94, H01L25/065S, H01L24/14|
|Sep 30, 2010||AS||Assignment|
Owner name: SCHOTT ELECTRONIC PACKAGING ASIA PTE. LTD., SINGAP
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHOTT AG;REEL/FRAME:025066/0719
Effective date: 20070725
|Oct 1, 2010||AS||Assignment|
Owner name: WAFER-LEVEL PACKAGING PORTFOLIO LLC, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHOTT ELECTRONIC PACKAGING ASIA PTE. LTD.;REEL/FRAME:025077/0418
Effective date: 20080722
|Jul 2, 2014||FPAY||Fee payment|
Year of fee payment: 4