Publication number | US7882464 B1 |

Publication type | Grant |

Application number | US 11/354,280 |

Publication date | Feb 1, 2011 |

Filing date | Feb 13, 2006 |

Priority date | Feb 14, 2005 |

Fee status | Paid |

Also published as | US8365125, US8370778, US8370779, US8381151 |

Publication number | 11354280, 354280, US 7882464 B1, US 7882464B1, US-B1-7882464, US7882464 B1, US7882464B1 |

Inventors | Steffen Rochel, David Overhauser, Gregory Steele, Kung Hsu |

Original Assignee | Cadence Design Systems, Inc. |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (6), Non-Patent Citations (9), Referenced by (8), Classifications (5), Legal Events (3) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 7882464 B1

Abstract

Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

Claims(19)

1. A computer implemented, vector-independent method for calculating time-dependent current consumption, comprising:

using at least one processor that is programmed for performing:

determining which electrical components are switching simultaneously at which point in time in which direction by calculating a time-dependent simultaneous switching probability function; and

calculating an instance specific, time-dependent current consumption by using at least a result of the act of calculating the time-dependent simultaneous switching probability function without performing functional verification to approximate a worst-case impact on a power distribution system, wherein

the act of calculating the instance specific, time-dependent current consumption provides multi-hierarchical level verification with transistor level resolution for an electronic circuit design, and

the electronic circuit design comprises a plurality of hierarchical levels.

2. The computer implemented method of claim 1 , in which the act of calculating the time-dependent simultaneous switching probability function comprises:

defining and calculating a timing probability;

defining and calculating a transition density; and

defining and calculating a normalized IR probability.

3. The computer implemented method of claim 2 , in which the act of defining and calculation said timing probability is based on one or more discrete switching time points obtained from a static timing analysis.

4. The computer implemented method of claim 2 , in which the act of defining and calculating said timing probability comprises taking switching time variations due to process variations in account by using a statistical timing analysis.

5. The computer implemented method of claim 2 , in which the act of defining and calculating said normalized transition density comprises defining and calculating an actual transition density derived from a functional simulation or a probabilistic propagation or a combination thereof.

6. The computer implemented method of claim 2 , in which the act of defining and calculating the normalized IR probability comprises:

calculating sensitivity of voltage fluctuation; and

calculating load current changes based on a resistive network representing a plurality of DC characteristics of said power distribution system.

7. The computer implemented method of claim 6 , in which the sensitivity of voltage fluctuation of the calculation of said normalized IR probability comprises one or more statistical variations of one or more DC characteristics caused by process variations.

8. The computer implemented method of claim 6 , in which the resistive network representing a plurality of DC characteristics comprises one or more parasitic resistive elements each of which being described by a mean value and a distribution function.

9. The computer implemented method of claim 1 , in which the act of determining which electrical components are switching simultaneously at which point in time in which direction by calculating a time-dependent simultaneous switching probability function is based on one or more static timing analyses.

10. The computer implemented method of claim 1 , in which the act of calculating the instance specific, time-dependent current consumption further comprises:

using a stochastic method based on said time-dependent simultaneous switching probability calculating said time-dependent current consumption across multiple clock cycles; and

using a switching current waveform for each of one or more individual instances.

11. A computer program product that includes a computer usable storage medium having a sequence of instructions which, when executed by at least one processor, causes the at least one processor to execute a process for calculating realistic, vector-independent, time-dependent current consumption, the process comprising:

determining which electrical components are switching simultaneously at which point in time in which direction by calculating a time-dependent simultaneous switching probability function; and

calculating a realistic, instance specific, time-dependent current consumption by using a result of the act of calculating the time-dependent simultaneous switching probability function without performing functional verification to approximate a worst-case impact on a power distribution system, wherein

the act of calculating the instance specific, time-dependent current consumption provides multi-hierarchical level verification with transistor level resolution for an electronic circuit design, and

the electronic circuit design comprises a plurality of hierarchical levels.

12. The computer product of claim 11 , in which said sequence of instructions causes said processor to execute a process for determining which electrical components are switching simultaneously at which point in time in which direction by calculating a time-dependent simultaneous switching probability function is based upon one or more static timing analyses.

13. The computer program product of claim 11 , in which the act of calculating the time-dependent simultaneous switching probability function comprises:

defining and calculating a timing probability;

defining and calculating a transition density; and

defining and calculating a normalized ER probability.

14. The computer program product of claim 13 , in which the act of defining and calculating the normalized IR probability comprises:

calculating sensitivity of voltage fluctuation; and

calculating load current changes based on a resistive network representing a plurality of DC characteristics of said power distribution system.

15. The computer program product of claim 11 , in which the act of calculating the instance specific, time-dependent current consumption further comprises:

using a stochastic method based on said time-dependent simultaneous switching probability calculating said time-dependent current consumption across multiple clock cycles; and

using a switching current waveform for each of one or more individual instances.

16. A system for calculating realistic, vector-independent, time-dependent current consumption, comprising:

a computer system which comprises at least one processor and is programmed for performing:

determining which electrical components are switching simultaneously at which point in time in which direction by calculating a time-dependent simultaneous switching probability function; and

calculating a realistic, instance specific, time-dependent current consumption by using a result of the act of calculating the time-dependent simultaneous switching probability function without performing functional verification to approximate a worst-case impact on a power distribution system, wherein

the act of calculating the instance specific, time-dependent current consumption provides multi-hierarchical level verification with transistor level resolution for an electronic circuit design, and

the electronic circuit design comprises a plurality of hierarchical levels.

17. The system of claim 16 , in which the computer system that is programmed for calculating the time-dependent simultaneous switching probability function is further programmed for performing:

defining and calculating a timing probability;

defining and calculating a transition density; and

defining and calculating a normalized IR probability.

18. The system of claim 17 , in which the computer system that is programmed for defining and calculating the normalized IR probability is further programmed for performing:

calculating sensitivity of voltage fluctuation; and

calculating load current changes based on a resistive network representing a plurality of DC characteristics of said power distribution system.

19. The system of claim 16 , in which the computer system is further programmed for performing:

using a stochastic method based on said time-dependent simultaneous switching probability calculating said time-dependent current consumption across multiple clock cycles; and

using a switching current waveform for each of one or more individual instances.

Description

This application claims the benefit of U.S. Provisional Application No. 60/652,919 filed Feb. 14, 2005, which is hereby incorporated by reference in its entirety.

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files and records, but otherwise reserves all other copyright rights.

The present invention relates to power integrity verification for electrical designs. In particular, embodiments of the present invention provide methods, systems, and methodologies to validate electrical characteristics of power distribution systems (PDSs) in electrical (e.g., IC chip) designs. This type of verification can, for example, ensure that each cell and transistor in the design receive sufficient voltage to operate functionally correct.

Some embodiments of the invention provide a methodology, method, and system for multi-level hierarchical, vector-independent dynamic verification of PDS in Systems on Integrated Circuit or Systems-on-a-Chip (hereinafter SoC) with transistor level resolution. Examples of SoC include small electronic devices made out of semiconductor materials which contain various functional components such as memory, digital and analog blocks made out of passive and active electronic devices. Examples of PDS include physical wiring composed of electrical conductive segments providing electrical connection between the pins of a SoC to all active and passive devices on a SoC.

Examples of systems and methods having multi-level hierarchical verification include systems and methods having the ability to validate the PDS for a cell, macro, or block of a SoC, to extract the physical and electrical characteristic of the cell, macro or block, and to generate a model. Such a model is defined as a PDS model. A PDS model can be used for the verification of PDS at the next hierarchy level. The next hierarchy level can be a macro, a block, or the complete SoC. This methodology is called the bottom-up multi-level hierarchical verification.

Other examples for multi-level hierarchical verification include systems and methods having the ability to perform PDS verification at a specific hierarchy level using PDS models and to capture boundary conditions for each component described by a PDS model and used in the hierarchical levels of investigation. The captured boundary conditions can than be used for PDS verification at a lower hierarchical level. This methodology is called the top-down multi-level hierarchical verification.

Dynamic verification of PDS in SoC includes, for example, the capability to calculate the time-dependent voltages and currents for all segments of PDS. Static verification of PDS in SoC includes, for example, the capability to calculate the time-independent (also called average or peak) voltages and currents for all segments of PDS.

Vector-independent dynamic verification of PDS in SoC includes, for example, the capability to calculate the time-dependent power or current consumption of the components of a SoC independent of functional stimuli for the components of a SoC. Transistor level resolution includes, for example, the ability to calculate the time-dependent fluctuations of the voltages at all segments of PDS from the external connections of the SoC (power and ground pins) through all wire segments of PDS to terminals to active and passive semiconductor devices such as transistors and capacitors for all types of components of SoC.

Prior approaches for implementing power distribution analysis all suffer significant functional drawbacks. For example, systems that perform dynamic verification at transistor level require user provided functional stimuli to calculate the time-dependent current consumption. Moreover, systems that perform dynamic verification at transistor or gate level do not allow for multi-level hierarchical PDS verification. Systems that perform dynamic verification at gate level also require either user provided definitions of switching probabilities for each signal net between the components of SoC or user provided functional stimuli for primary inputs of the SoC or the components thereof. Furthermore, vector-independent dynamic verification at gate level does not provide transistor level resolution for PDS verification. In addition, prior approaches also lack the ability to calculate realistic approximation of worst-case time-dependent current consumption for SoC without user specified power constraints. Finally, prior approaches also lack means for sending effective feedback to the users about the electrical characteristic of PDS and decoupling capacitors.

Some embodiments of the present invention overcomes the limitations of prior solutions by enabling dynamic verification at the gate level requiring neither user provided definitions of switching probabilities for each signal net between the components of SoC nor user provided functional stimuli for primary inputs of SoC as well as a statistical approach to determine locally simultaneously switching components and creating worst case voltage fluctuations. Some embodiments of the instant invention are directed to both a dynamic top-down and a dynamic bottom-up multi-level hierarchical PDS verification with transistor level resolution. In addition, some embodiments of the present invention teach a vector-independent dynamic verification at gate level with transistor level resolution for PDS verification and enable the use of static PDS verification techniques to build PDS models for components of SoC and the use of these models for multi-level hierarchical dynamic PDS verification. Furthermore, some embodiments of the instant invention provide a methodology to measure the effectiveness of explicit decoupling capacitors for placement optimization as well as graphical representation. In addition, some embodiments of the present invention teach a methodology to take into account the variation of the electrical circuit behavior due to manufacturing process variations for the vector-independent calculation of current consumption for SoC.

Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.

The accompanying drawings are included to provide a further understanding of the invention and, together with the Detailed Description, to serve to explain the principles of the invention.

Embodiments of the present invention provide methods, systems, and methodologies to validate electrical characteristics of power distribution systems (PDSs) in an electrical (e.g., IC chip) designs. As noted above, some embodiments of the invention provide a vector-independent methodology, method, and system for multi-level hierarchical, dynamic verification of PDS in Systems on Integrated Circuit (SoC) with transistor level resolution. Some embodiments of the invention contain several components which are described in the following description.

PDS Model

One of the purpose of the PDS models is to capture the physical as well as electrical characteristics of the PDS to serve, for example, as the basis for multi-level, hierarchical PDS verification. The PDS model captures the information used for PDS verification as well as time-varying, vector-independent gate level current consumption calculation. Both components facilitate multi-level hierarchical PDS verification, both in the bottom-up and the top-down approach. Additionally, this enables embodiments of the invention to measure, report, and optimize the effectiveness of decoupling capacitors as integral part of PDS.

According to one embodiment of the present invention, a PDS model comprises some or all of the following information for a component as shown in

Physical information **102** about the segments of PDS used to connect the component within a SoC. These sets of segments are usually referred as ports of a component, and the physical information includes size, location, and layer information.

For each segment a terminal point is determined, which further defines the connection of the electrical model for a component.

An electrical network **104** describing the electrical characteristics of the PDS internal to the component. The electrical model can be as simple as a parasitic resistor network and is connected to the terminal points of the PDS model. Moreover, the parasitic network can be described by one or more RLC model or one or more subsets thereof. The electrical model can also be directly extracted from the layout information of the internal PDS. Furthermore, the size of the electrical model can be decreased by applying network reduction techniques.

Location of current sinks **106**. Current sinks are in general active or passive electrical devices which are consuming current due to active operation or leakage through the semiconductor devices.

An electrical model **108** for the current sinks within the component. An electrical model can be as simple as a constant or a time-dependent current source. The model can also be described as a function of the supply voltages and the electrical environment of the component. The model can describe the absolute current for each sink or relative current strength between the sinks in a component.

Netlist connectivity information **110**. The netlist connectivity information can be at the transistor level or an abstraction thereof. The netlist connectivity information includes as well electrical models describing the electrical behavior of the signal interconnect between components of the netlist. The electrical model can be as simple as a capacitor describing the parasitic signal net capacitor.

Vector-Independent Calculation of the Time-Dependent Gate Level Current Consumption

The problem being addressed by a vector-independent calculation of the time-dependent gate level current consumption methodology is to calculate the switching situation which causes the worst-case transient IR drop without the need to perform functional verification, i.e., to determine which components are switching simultaneously at which point in time in which direction based on design constraints used for and results of static timing analysis. An example of a vector-independent calculation is a calculation that is performed in a vector-less manner. An example time-dependent gate level current consumption waveform is shown in

Other proposed approaches are focused solely on the determination of the worst case or peak power consumption and its associated transient current consumption waveform. While the knowledge of the peak power consumption waveform is certainly a good measure, it doesn't necessarily correlate with current consumption waveform causing the worst-cast transient IR drop.

For example, one proposed approach is a methodology to calculate the so called switching scenarios, i.e. to calculate which component is switching at which time and in which direction. The calculation in this approach is based on the timing window calculated by static timing analysis, the transition density under consideration of local logic satisfiability as well as under peak-average ratio constraints. While the proposed methodology can be used to calculate switching situations, the approach does not provide the ability to determine the transient peak power consumption. Therefore a peak-average ratio constraint is introduced as an artificial constraint to mask the deficiency of the proposed methodology. It can be easily shown that the peak-average ratio varies for different SoC as well as between different blocks of a SoC. More importantly, the method does not take into account the impact of locally simultaneously switching components causing large voltage fluctuations.

In other proposed approaches, genetic algorithms are used to calculate worst case vector sets within a given confidence range based on seed sequence(s) in combination with gate level functional simulation algorithms. One drawback of this methodology is that seed sequence needs to be provided by the user of the system, the choice of the seed sequence has strong impact on the convergence behavior of the proposed methodology. Moreover, several, usually resource intensive, functional verification cycles are required until a vector sequence approximating the worst case situation is determined in the defined confidence range. In addition, this approach is only applicable to calculate the worst-case power consumption, and is therefore not applicable to determine the worst-case transient IR drop.

Some embodiments of the present invention include a methodology that provides the ability to calculate realistic time-dependent current consumption to approximate the worst-case impact on the power distribution system. As shown in the flowchart of **300** is calculated based on a time-dependent simultaneous switching probability function P_{SSO}(t) **310**. The time-dependent simultaneous switching probability function P_{SSO}(t) **310** is calculated based on the switching current signature **308**, the timing probability P_{T}(t) **302**, the normalized transition density P_{TD } **304**, normalized IR probability P_{IR } **306**, which are described in further details in the subsequent paragraphs.

One component of the time-dependent simultaneous switching probability function is the timing probability P_{T}(t) **302**, e.g. the probability that a specific instance will switch in a certain direction at specific point in time. One approach is to define the timing probability **302** as an uniform distribution function with P_{T}(t)=1 within the timing window and P_{T}(t)=0 outside. However, discrete switching time points are calculated during static timing analysis, and this information can be used to model the timing probability function **302** more realistically. In addition, statistical static timing analysis will enable the consideration of switching time variations due to process variations. The concept of timing probabilities P_{T}(t) **302** used in this invention is the basis to take the process variations into account for the vector-independent calculation of the current consumption **300**.

Another component of the time-dependent simultaneous switching probability function is the normalized transition density P_{TD } **304**, which can be calculated based on the actual transition density for a given signal net, derived either from functional simulation or through probabilistic propagation or a combination thereof, as described in “Full-chip vector-less dynamic power integrity analysis and verification against 100 uV/100 ps-resolution measurement”, Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, 3-6 Oct. 2004, which is hereby incorporated by reference in its entirety.

Another component of the time-dependent simultaneous switching probability function is the normalized IR probability P_{IR } **306**, i.e., sensitivity of voltage fluctuation versus load current changes based on the resistive network representing DC characteristic of the PDS. The sensitivity of voltage fluctuations may include statistical variation of the DC characteristic caused by the process variation, and each parasitic resistive element is described by a mean value and distribution function. Therefore, the time-dependent simultaneous switching probability function P_{SSO}(t) **310** can be expressed in the following equation:

*P* _{SSO}(*t*)=*f*(*P* _{T}(*t*),*P* _{TD} *,P* _{IR})) Equation 1

Stochastic techniques such as the Monte-Carlo method based on the time-dependent simultaneous switching probability P_{SSO}(t) **310** are used together with the switching current waveform for each individual instance to calculate the time dependent current consumption across multiple clock cycles.

Multi-Level Hierarchical Bottom-Up And Top-Down PDS Verification

**402** provide the input data into the PDS verification system **404** (which comprises transistor level PDS verification system **408** and cell-based PDS verification system **410** described in more detail with respect to **406**.

The PDS verification methodology can be applied to complete or partial design data **402**. The design data **402** in one embodiment of the invention include some or all of the following information such as the design layout information, the cell library information, the environment constraints and models, and/or pre-extracted layout parasitic data. Moreover, the cell library information may comprise information such as the timing libraries, the power libraries, the PDS model libraries, the physical abstractions, and/or the transistor level description of cell contents. Finally, the environment constraints and models may comprise information such as the SoC package model data, the design operation constraints, and/or the PDS boundary conditions.

The transistor level PDS verification system **408** is described in further details in **408** can be applied to verification and characterization of standard cells, I/O cells, analog, digital, and mixed signal custom design blocks. Furthermore, **408**, and simplifications are possible to reduce the amount of data to be analyzed as well as captured in the PDS models. The cell-based PDS verification system **410** is described in further details in

Referring to **408** performs the transistor level PDS verification **508** based upon the input of the design data **402**. The PDS verification results are further processed in the PDS verification output processing **406**. In addition, in some embodiments of the present invention, the transistor level PDS verification system further performs the transistor level parasitic extraction **504** and one or more transistor level circuit analyses **506** to achieve the desired transistor level accuracy.

**410** in one embodiment of the invention. In this cell-based PDS verification **410**, the design data **402** provide the input data into the cell-based PDS verification system **410**. This flow is typically applied to designs and blocks generated by place & route tools. The steps of cell-based parasitic extraction **604** and the cell-based static and/or time-dependent power consumption calculation **608** are performed at the cell level and therefore, this flow can be referred to as cell based PDS verification. Moreover, transistor level accuracy is achieved by merging the contents of PDS models for the cells with the parasitic data **606** generated in step **604** and **608**. The results of the cell based PDS verification will be further processed in **406** of the PDS verification flow. The PDS verification output processing **406** contains the PDS model generation of the block or chip verified.

Referring to **406** contains the generation of user consumable data and PDS verification results **704** as well as the consolidation of verification output, data compression, and data processing to build PDS models for the cell or block analyzed **706** with the transistor level PDS verification system **408**. The consolidated verification output, the PDS model generated, and compressed data in **706** may be further utilized to merge with the PDS model library **708** or to establish the instance based boundary conditions **710**.

The PDS model generated in this step can then be used at the next design hierarchical level to represent a block or partition within a specific design hierarchy level up to the complete SoC. The methodologies of employing the transistor level PDS verification system **408** and the cell-based PDS verification system **410** enable a bottom-up multi-level hierarchical PDS verification.

Top-down PDS verification is enabled with the methodology described herein by capturing PDS boundary conditions **710** for individual design instances. A design instance can be, for example, a partition, a block, a macro, or a cell. The instance based boundary conditions **710** are considered as environment constraints as part of the design data and can be applied at various hierarchical levels. The instance specific PDS boundary conditions **710** enable a methodology to perform PDS verification on a specific design instance taking into account the interaction between different design instances without having to perform PDS verification on the complete SoC. This methodology can be referred to as the top-down PDS verification.

Decoupling Capacitor Effectiveness and Graphical Representation of Decoupling Capacitor Effectiveness

Textual and numerical data are used to analyze the results of PDS verification in detail. However, due to the amount of data to be handled during block and full-chip PDS validation, this it is not an efficient way to provide insight about the characteristics of the PDS from a global perspective. Some embodiments of the invention provide a graphical approach to provide feedback about the effectiveness of decoupling capacitors from a global perspective. A global perspective is important in understanding the effectiveness of explicit decoupling capacitors under consideration of parasitic, embedded, and natural decoupling capacitors as well as in allowing the optimization of the placement of explicit decoupling capacitors.

Referring to **806** can therefore be measured as the ratio of the device switching delay variation Δτ **802** due to transient PDS variations versus the device switching delay τ **804** at local supply voltages determined by static PDS validation. As the switching delay is a function of the local supply voltages during the switching event, the effectiveness of explicit decoupling capacitors can therefore be approximated as a function of the ratio of the transient supply voltage variation vs. the static supply voltage at the switching cells:

*I=f*(Δτ,τ)≈*f*(Δ*V*(*t*),Δ*V* _{s}) Equation 2

Furthermore, in one embodiment of the present invention, a developed methodology includes the mapping of the effectiveness of explicit decoupling capacitor, I, into a color index **808** as shown in

Optimization of the Placement of Decoupling Capacitors

In one embodiment of the instant invention, the developed methodology to measure the effectiveness of explicit decoupling capacitors as defined in Equation 2 can be used as well as cost function together with placement optimization techniques during the placement optimization of explicit decoupling capacitors:

Φ′=Φ+Σ*I* ^{2} Equation 3

Φ is the original placement optimization cost function, Φ′ is the modified cost function capturing the effectiveness of decoupling capacitors. An embodiment of a decoupling capacitor aware optimization methodology is shown in **904** for the initial instance placement **902** is first calculated; then the modified optimization cost function Φ′ **906** is evaluated by taking into account the effectiveness of decoupling capacitors. This embodiment of the invention further defines a threshold value for a convergence criterion and determines whether the convergence criterion is met in **910**. If the convergence criterion is met the current placement is thus determined to be the final placement **912**. If the convergence criterion is not met this embodiment of the invention, calculates new placement and its associated optimization cost function Φ′, and repeat the above iterative process until the convergence criterion is met in **910**.

**1400** suitable for implementing an embodiment of the present invention. Computer system **1400** includes a bus **1406** or other communication mechanism for communicating information, which interconnects subsystems and devices, such as processor **1407**, system memory **1408** (e.g., RAM), static storage device **1409** (e.g., ROM), disk drive **1410** (e.g., magnetic or optical), communication interface **1414** (e.g., modem or Ethernet card), display **1411** (e.g., CRT or LCD), input device **1412** (e.g., keyboard), and cursor control.

According to one embodiment of the invention, computer system **1400** performs specific operations by processor **1407** executing one or more sequences of one or more instructions contained in system memory **1408**. Such instructions may be read into system memory **1408** from another computer readable/usable medium, such as static storage device **1409** or disk drive **1410**. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions to implement the invention. Thus, embodiments of the invention are not limited to any specific combination of hardware circuitry and/or software. In one embodiment, the term “logic” shall mean any combination of software or hardware that is used to implement all or part of the invention.

The term “computer readable storage medium” or “computer usable storage medium” as used herein refers to any medium that participates in providing instructions to processor **1407** for execution. Such a medium may take many forms, including but not limited to non-volatile media and volatile media. Non-volatile media includes, for example, optical or magnetic disks, such as disk drive **1410**. Volatile media includes dynamic memory, such as system memory **1408**.

Common forms of computer readable media includes, for example, floppy disk, flexible disk, hard disk, magnetic tape, any other magnetic medium, CD-ROM, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, RAM, PROM, EPROM, FLASH-EPROM, any other memory chip or cartridge, or any other medium from which a computer can read.

In an embodiment of the invention, execution of the sequences of instructions to practice the invention is performed by a single computer system **1400**. According to other embodiments of the invention, two or more computer systems **1400** coupled by communication link **1415** (e.g., LAN, PTSN, or wireless network) may perform the sequence of instructions required to practice the invention in coordination with one another.

Computer system **1400** may transmit and receive messages, data, and instructions, including program, i.e., application code, through communication link **1415** and communication interface **1414**. Received program code may be executed by processor **1407** as it is received, and/or stored in disk drive **1410**, or other non-volatile storage for later execution.

In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, the above-described process flows are described with reference to a particular ordering of process actions. However, the ordering of many of the described process actions may be changed without affecting the scope or operation of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.

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Classifications

U.S. Classification | 716/113 |

International Classification | G06F17/50 |

Cooperative Classification | G06F17/5036, G06F2217/78 |

European Classification | G06F17/50C4 |

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May 9, 2006 | AS | Assignment | Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROCHEL, STEFFEN;STEELE, GREGORY;HSU, KUNG;SIGNING DATES FROM 20060329 TO 20060407;REEL/FRAME:017602/0101 Owner name: CADENCE DESIGN SYSTEMS, INC., CALIFORNIA |

Jun 30, 2006 | AS | Assignment | Effective date: 20060626 Owner name: CADENCE DESIGN SYSTEMS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OVERHAUSER, DAVID;REEL/FRAME:018046/0332 |

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