|Publication number||US7888202 B1|
|Application number||US 12/558,756|
|Publication date||Feb 15, 2011|
|Priority date||Mar 31, 2005|
|Also published as||US7619298|
|Publication number||12558756, 558756, US 7888202 B1, US 7888202B1, US-B1-7888202, US7888202 B1, US7888202B1|
|Inventors||Firas N. Abughazaleh, Brian T. Brunn|
|Original Assignee||Xilinx, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (1), Referenced by (2), Classifications (13), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates in general to integrated circuits, and more particularly to method and apparatus for reducing parasitic capacitance.
The transmission of multi-gigabit data rates in wired broadband communication systems pose a big challenge to system design. Part of the challenge lies in the design of the communication channel and interfacing to it. Typical issues that need to be dealt with are channel impedance matching and channel losses of the high frequency components of the signal due to channel parasitic impedances manifested in inductive, capacitive and skin loss among other effects.
Of a particular interest is matching of impedance between the data channel and the receiving end. In an ideal scenario, a termination resistance is placed on chip at the front end of the receiver with a resistance value that matches the channel impedance. Matching of impedance at the channel/receiver interface helps reduce the reflected signal energy back to the transmitter thus reducing noise and timing jitter of the signal and improving the return loss (RL).
Typically in a data channel, a terminated signal is AC coupled through a relatively large capacitance to an input buffer to condition the signal for further processing. Ideally, the AC coupling capacitance does not affect the termination impedance because it connects to an (ideally) infinite impedance buffer. In reality, however, there are parasitic capacitances that are on-chip, e.g., the terminal and Electrostatic Discharge (ESD) capacitance on one end of the AC coupling capacitor and the input buffer gate capacitance and AC coupling capacitance to ground that alter the termination impedance magnitude and phase.
These parasitic capacitances causes the high frequency components of the received digital signal to have a larger reflection magnitude thus worsening the return loss (RL). The parasitic capacitances must be reduced as much as possible while minimizing any change to the termination impedance to minimize the reflection and improve the RL figure.
It can be seen that there is a need for a method and apparatus for reducing parasitic capacitance.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method and apparatus for reducing parasitic capacitance, which in an exemplary embodiment provides for on-chip reduction of return loss.
An embodiment of the present invention solves the above-described problems by providing a P-well blocked layer directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.
These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention.
Referring now to the drawings in which like reference numbers represent corresponding parts throughout:
In the following description of the embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration the specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized because structural changes may be made without departing from the scope of the present invention.
An embodiment of the present invention provides a method and apparatus for on-chip reduction of return loss. A P-well blocked layer is provided directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.
In some FPGAs, each programmable tile includes a programmable interconnect element (INT 211) having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA. The programmable interconnect element (INT 211) also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top of
For example, a CLB 202 can include a configurable logic element (CLE 212) that can be programmed to implement user logic plus a single programmable interconnect element (INT 211). A BRAM 203 can include a BRAM logic element (BRL 213) in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as four CLBs, but other numbers (e.g., five) can also be used. A DSP tile 206 can include a DSP logic element (DSPL 214) in addition to an appropriate number of programmable interconnect elements. An 10B 204 can include, for example, two instances of an input/output logic element (IOL 215) in addition to one instance of the programmable interconnect element (INT 211). As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element 215 are manufactured using metal layered above the various illustrated logic blocks, and typically are not confined to the area of the input/output logic element 215.
In the pictured embodiment, a columnar area near the center of the die (shown shaded in
Some FPGAs utilizing the architecture illustrated in
Configuration logic 205 allows configuration data values to be loaded into the FPGA architecture 200. In accordance with an embodiment of the present invention, the configuration data takes into consideration the actual location of a circuit in the package, which can result in increased circuit performance. Placement based information is provided to the FPGA architecture 200 that will optimize its performance.
The highest series resistance is measured from the geometric center of the capacitor 1272 and decreases toward the capacitor periphery 1270 and beyond. However, the resistance of the P-well blocked layer 1286 extending beyond the capacitor periphery 1270 is easier to calculate. Thus, a minimum required resistance 1286 to ground can be calculated by identifying the capacitor periphery 1270 and extending the P-well blocked layer a predetermined distance to provide a desired P-well blocked delta R for the portion of the P-well blocked layer extending beyond the periphery of the AC coupling capacitor. The unaccounted distributed resistance underneath the capacitor 1282, 1284 comes as a bonus resistance that is added on top of the precisely calculated portion 1286.
While an AC coupling capacitor has been discussed with respect to the invention, those skilled in the art will recognize that the present invention is not meant to be limited to use with a capacitor. Rather, embodiments of the present invention may be used with other devices to prevent or minimize parasitic capacitance at an input of a data channel. Furthermore, those skilled in the art will recognize that the present invention, when implemented with a capacitor for reducing return loss, is not meant to be limited to any particular capacitor configuration, i.e., the capacitor may take the form of a finger capacitor, a parallel plate capacitor, etc.
The foregoing description of the exemplary embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not with this detailed description, but rather by the claims appended hereto.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5059548||Apr 2, 1990||Oct 22, 1991||Hyundai Electronics Industries Co., Ltd.||Method of making a semiconductor memory device having a double stacked capacitor|
|US5162248||Mar 13, 1992||Nov 10, 1992||Micron Technology, Inc.||Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing|
|US5608258 *||Mar 16, 1995||Mar 4, 1997||Zilog, Inc.||MOS precision capacitor with low voltage coefficient|
|US5793074 *||Jul 19, 1996||Aug 11, 1998||Samsung Electronics Co., Ltd.||Metal oxide semiconductor capacitors having uniform C-V characteristics over an operating range and reduced susceptibility to insulator breakdown|
|US6137153 *||Feb 13, 1998||Oct 24, 2000||Advanced Micro Devices, Inc.||Floating gate capacitor for use in voltage regulators|
|US6285052 *||Sep 26, 1997||Sep 4, 2001||Advanced Micro Devices, Inc.||Integrated capacitor|
|US6288604||Feb 3, 1999||Sep 11, 2001||Broadcom Corporation||CMOS amplifier providing automatic offset cancellation|
|US6933551||Apr 4, 2003||Aug 23, 2005||Zarlink Semiconductor Limited||Large value, compact, high yielding integrated circuit capacitors|
|US6972436 *||Jun 11, 2001||Dec 6, 2005||Cree, Inc.||High voltage, high temperature capacitor and interconnection structures|
|US7130182||Apr 22, 2004||Oct 31, 2006||Texas Instruments Incorporated||Stacked capacitor and method for fabricating same|
|US7541652||May 5, 2004||Jun 2, 2009||Xilinx, Inc.||Substrate coupled noise isolation for integrated circuits|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US9245828 *||Jul 11, 2013||Jan 26, 2016||Mindspeed Technologies, Inc.||High speed signal conditioning package|
|US20140021597 *||Jul 11, 2013||Jan 23, 2014||Mindspeed Technologies, Inc.||High Speed Signal Conditioning Package|
|U.S. Classification||438/253, 257/532, 438/396|
|Cooperative Classification||H01L27/0676, H01L21/76, H01L28/40, H01L27/0629, H01L27/0805|
|European Classification||H01L27/08C, H01L21/76, H01L27/06D6V, H01L28/40|
|Sep 14, 2009||AS||Assignment|
Owner name: XILINX, INC., CALIFORNIA
Effective date: 20050329
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ABUGHAZALEH, FIRAS N.;BRUNN, BRIAN T.;REEL/FRAME:023225/0227
|Aug 15, 2014||FPAY||Fee payment|
Year of fee payment: 4