|Publication number||US7907456 B2|
|Application number||US 11/931,098|
|Publication date||Mar 15, 2011|
|Priority date||Oct 31, 2007|
|Also published as||US20090109785, WO2009058991A1|
|Publication number||11931098, 931098, US 7907456 B2, US 7907456B2, US-B2-7907456, US7907456 B2, US7907456B2|
|Inventors||Theodore W. Houston, Andrew Marshall|
|Original Assignee||Texas Instruments Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Referenced by (4), Classifications (11), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to semiconductor memory devices and more particularly integrated circuits having memory devices which include SRAM or other memory cells that use voltage differentials to improve device performance.
Current trends in the semiconductor and electronics industry require memory devices to be made smaller, faster and require less power consumption. One reason for these trends is that more personal devices are being manufactured that are relatively small and portable, thereby relying on battery power. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller, faster, and lower power dissipation memory cells and transistors used to provide the core functionality of these memory devices.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (e.g. SRAM) or dynamic (e.g. DRAM), differing mainly in the manner by which they store a state of a bit. Several types of DRAM memory cells are used commonly, including a single capacitor memory cell (1T1C) and a dual capacitor memory cell (2T2C). As illustrated in
Ferroelectric RAM (FeRAM or FRAM) is a type of non-volatile memory that uses a ferroelectric layer to achieve non-volatility. As shown in
Magnetic random access memory (MRAM) is a type of non-volatile memory.
The basic CMOS SRAM cell generally includes two n-type or n-channel (NMOS) pull-down or drive transistors and two p-type (PMOS) pull-up or load transistors in a cross-coupled inverter configuration, with two additional NMOS select or pass-gate transistors added to make up a standard double-sided or differential six-transistor memory cell (a DS 6T SRAM cell, a 6T SRAM cell, or simply a 6T cell). 8 transistor, 9 transistor, 5 transistor and 4 transistor SRAM cells are also known. Additionally, application specific SRAM cells can include an even greater number of transistors. A plurality of transistors are utilized in SRAM requiring matched electrical characteristics to provide predictable cell switching characteristics, reliable circuit performance, and minimize array power dissipation.
Respective inverters 142, 144 comprise a p-type MOS (PMOS) pull-up or load transistor Q1 150, Q2 152 and an n-type (NMOS) pull-down transistor Q3 154, Q4 156. Pass gates (e.g., transistors) Q5 146, Q6 148 are n-channel as well, which generally supply higher conductance as compared to p-channel transistors. Pass transistors 146, 148 are enabled by wordline 164 and accessed by bitlines 160, 162 to set or reset the SRAM latch 130.
In general, SRAM cells are more stable and have better data retention where the respective pMOS (150, 152) and nMOS (154, 156) transistors are balanced and matched within the two inverters (142, 144). However, as dimensions are reduced to scale down devices, it becomes increasingly difficult to achieve a balance in the relative strengths of the pass gate, drive, and load transistors over the desired range of temperature, bias conditions, and process variations, as well as achieving matched transistor characteristics. As a result, SRAM cells formed as such can be adversely affected by varying operating characteristics and may be unstable and may not retain the desired bit state, during read or write operations.
During conventional read or write operations, bitlines 160 and 162 are initially precharged to a high or “1” state as illustrated. A read voltage is asserted to wordline WL 164 during a read or a write operation to activate (turn-on) pass transistors Q5 146 and Q6 148 into conduction, whereby latch 132 may be accessed by bitlines 160 and 162, respectively. With the prior data states as shown in
The intrinsic stability of a conventional SRAM cell is known to correspond to a noise-margin of a cross-coupled inverter loop of the cell when it is disconnected from the bit-lines, referred to commonly as the static noise margin (SNM). In contrast, the read stability of the cell corresponds to the noise-margin of the inverter loop with the word-line being active and the cell internal nodes being connected to the bit-lines. The read stability is usually worse than the intrinsic stability. As a result, the power supply can drop to a far lower value than when the cell is read-out. Vmin refers to the lowest power supply voltage at which an SRAM array still functions properly.
With scaling, it is increasingly difficult to design and operate an SRAM cell to be both stable and to be writeable across process variation, such as threshold variation, and across supply voltage variation. Supply voltage variation is often associated with use of a battery as the power supply source for the SRAM. Concurrently maintaining adequate read current (Iread) is also a problem.
For minimizing SRAM and other memory power consumption, as with other non-memory circuits, it is generally desirable for the total power supply voltage to be as low as possible. In the conventional case Vss is held at ground, Vdd needs to be minimized. Vdd for the array is generally referred to as VDDM. It is noted that VDDM is only set by the user within certain limits, since for most applications VDDM changes over time, such as a function of battery charge level as well as other factors that are known to affect VDDM. A low VDDM is known to degrade writeability and Iread. As noted above, process variation which can be significant even across a given die, can also be a factor in determining stability, writeability (Vtrip) and read current. What is needed is a memory circuit that is capable of compensating for process variation, such as threshold variation, in the case of SRAM and across supply voltage variation to relax the SNM/Vtrip/read current tradeoff to allow further scaling of SRAM cells.
This Summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. The memory array can comprise SRAM, or other memory such as MRAM or FeRAM, or a DRAM that uses VDDM that may be developed.
A voltage differential generating circuit is operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein the differential is a function of the array supply voltage. Through control of the voltage differential between the supply voltage, such as the high supply for the array (VDDM) and VWL, in the case of SRAMs, it has been found by the present inventors that the memory becomes more stable and writable across process variation and across supply voltage variation, and adequate read current generally becomes easier to maintain.
In one embodiment the differential is also a function of a process related device parameter or a temperature during operation of the IC. Process related device parameter can be selected from Vtn, Vtp, gm, Idsat, and Idlin.
In one embodiment the supply voltage comprises a high supply for the array (VDDM). In another embodiment, the IC further comprises trend selection storage circuitry on the IC coupled to the voltage differential generating circuitry operable to select a trend which relates VWL as a function of the array supply voltage from a plurality of different trends. The storage circuitry can be programmable.
The IC can further comprise trend selection circuitry coupled to the voltage differential generating circuitry. In one embodiment, the trend selection circuitry consists of a single global trend selection circuit. In another embodiment, the trend selection circuitry comprises a plurality of local trend selection circuits.
In one embodiment, the voltage differential generating circuitry consists of a single global voltage differential generating circuit. In another embodiment, the voltage differential generating circuitry comprises a plurality of independent local voltage differential generating circuits. The plurality of local voltage differential circuits can include a MOS strength or a parameter related thereto as an input. The plurality of local voltage differential generating circuits can include an op-amp or other differential input amplifier, wherein a gain of the amplifier is determined by the MOS strength parameter or a parameter related thereto.
In one embodiment the voltage differential generating circuitry is operable to set VWL=VDDM for VDDM less than a voltage level and VWL<VDDM for VDDM above the voltage level. The VWL level can be clamped at a level above the voltage level.
An integrated circuit (IC) comprises at least one memory array comprising a plurality of SRAM memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. The memory cells each including first and second cross-coupled inverters comprising PMOS loads and NMOS pull up devices, the first inverter having a first latch node and the second inverter having a second latch node; and one or more NMOS pass transistor coupled to the first latch node and to the second latch node, one of the word lines being connected to a gate of the pass transistor and one of the bit lines being connected to a source or drain of the pass transistor. A low supply voltage for the array (VSSM) is coupled to a low voltage supply terminal of the cross-coupled inverters, and a high voltage supply for the array (VDDM) coupled to a high voltage supply terminal of the cross-coupled inverters. At least one voltage differential determining circuit operable for dynamically controlling a voltage differential between VDDM and a word line voltage (VWL) coupled to the plurality of word lines, wherein the voltage differential is based on VDDM and at least one process related parameter associated with the array. The at least one voltage differential determining circuit can comprise a plurality of voltage differential determining circuits.
A method of operating an integrated circuit comprising at least one memory array, the memory array comprising a plurality of memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells is provided. The method comprises the step of automatically setting a voltage differential between a supply voltage for the array and a word line voltage (VWL) coupled to the plurality of word lines based on at least the supply voltage.
The method can comprise the step of selecting a trend from of a plurality trends which relate VWL as a function of the array supply voltage, wherein VWL is based on the trend selected and the supply voltage. The selecting can comprise programmable selection. The selecting can comprise on-chip selecting.
In one embodiment the selecting consists of a single global selection for the IC. In another embodiment, the selecting comprises a plurality of localized selecting. The setting step can comprise dynamically setting, wherein the voltage differential is automatically updated during operation of the IC. In one embodiment, the voltage differential can comprises VWL=VDDM for VDDM less than a voltage level and VWL<VDDM for VDDM greater than the voltage level. In this embodiment, VWL can be clamped at a level above the voltage level. In another embodiment, VWL>VDDM for VDDM less than a voltage level and VWL<VDDM for VDDM greater than the voltage level.
The present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout. The present invention is a new integrated circuit (IC) design comprising an SRAM or other memory (e.g. FeRAM or MRAM) and related method that can compensate the SRAM or other memory for process variation, such as threshold variation and/or supply voltage variation and/or drift over time and/or temperature. The present invention uses a differential between the WL high voltage (VWL) and the array supply voltage, such as the array high voltage VDD (VDDM), for compensation of one or more of such variations to improve the SNM/Vtrip/read current tradeoff which in one embodiment supports current SRAM designs and permits further scaling of SRAM cells. Although generally described below relative to SRAMs, the present invention is also applicable to other memories including FeRAM or MRAM. The differential can be in one embodiment programmable, and in another embodiment dynamically programmable.
It has been found that a relatively higher VWL generally decreases stability and increases writeability, while a relatively lower VWL does the opposite. Raising or lowering VWL relative to VDDM is used by the present invention to compensate for process and power supply variation, and can be used to compensate for other factors such as temperature and age related drift. Generally, applied to SRAMs, for cells having NMOS pass and pull-down devices and PMOS loads, such as for the 6T cell shown in
The IC may have multiple instance of separate memory, such as multiple SRAMs or other memories. The present invention can include the differential being generated globally (i.e. once for the IC) or locally at each SRAM instance, or some combination of local and global. The differential may have different “tracks” or “trends” which define a relation between VWL and the array supply voltage (e.g. VDDM) that can be selected either centrally (see
In another embodiment of the invention, a central selection control circuit provides trend selection data, such as in the form of binary control signals, to a plurality of local differential generating circuits.
To implement IC 206, in one embodiment, at least one component strength parameter generally determined during wafer probe or final (package) test, is generally obtained. Component strength parameters can be threshold voltage (Vtn or Vtp), transconductance (gm for nMOS or pMOS), Idsat, Idlin (for NMOS or PMOS), for example. In another embodiment, at least one measurement of an SRAM cell characteristic (e.g. Vtrip) is obtained. As described above, in one embodiment of the present invention, central controller 280 comprises a fuse ROM. The fuse ROM can be set at wafer probe to provide a binary (e.g. 3 bits) or analog (current or voltage) control signal to indicate which of a plurality of VWL voltage trends will be followed, such as one of the two trends shown in
Thus, IC 206 sets the WL/VDDM differential locally, but with central controller 280. As noted above, it has been found that an optimized VWL/VDDM differential provides a strong knob on memory with reduced area/power overhead. The distribution of binary signals or distribution of an analog signal (e.g. reference voltage) from controller 280 to high impedance inputs (such as to an inverter or to a follower) relaxes routing requirements compared to distributing a supply voltage from a centralized controller.
As shown above, the differential can thus be applied globally across one or more memory instance, centrally determined but generated locally, or determined and generated locally in a plurality of portions for each memory instance. The local embodiment generally permits further efficiency by better customizing the VDDM/VWL differential to local conditions in the memory. The differential in any of these embodiments can be dynamically modifiable. It is noted that during certain periods of time or under certain conditions, the VDDM/VWL differential can be zero or essentially zero (e.g. <0.01 volts).
In a typical embodiment of the invention, VWL is derived from VDDM with VWL being≦VDDM. However, in another embodiment, VWL is derived from a voltage>VDDM, such as when an I/O supply is also available, for example an I/O supply of 1.8 volts Alternatively, VWL>VDDM can be derived from VDDM, e.g. with a charge pump. Whether VWL is >VDDM, VWL=VDDM, or VWL<VDDM, VWL can be derived from VDDM, from a supply from which VDDM is derived, or from a supply independent of VDDM. Thus, VWL can be controlled to be greater or less than VDDM. VWL>VDDM is desirable when the parameters are such that SNM is robust (stable cell) and Vtrip inadequate (difficult to write) or the Iread is inadequate. Typically, this condition is present when Vtn is high and/or |Vtp| is low, and/or VDDM is low. In yet another embodiment, VDDM is derived from VWL, such as when VWL is set by a band gap reference (providing an output voltage around 1.25 V), and VDDM is ≦VWL.
In one embodiment of the present invention, a programmable differential between VDDM and VWL is provided. Taking the differential to be VDDM−VWL, for SRAMs having NMOS pass and pull-down devices and PMOS loads, the differential is generally larger (less negative or more positive) when one or more of:
(i) VDDM is higher (e.g. above some predetermined threshold),
(ii) Vtn is low (e.g. below some predetermined threshold voltage) and
(iii) Vtn/Vtp (in absolute value ratio) is low.
Vtn is generally a more sensitive parameter as compared to Vtp for use in the invention for SRAMs which have nMOS pass gates and pull-down devices and only pMOS loads, such as conventional 6T SRAMs. However, in other SRAM arrangements, Vtp can be a more important parameter as compared to Vtn and the relationship of the desired differential to the threshold voltages may be different.
Statistical simulations can be performed to predict the stability and write-ability margins as a function of the local transistor variability, the global transistor parameters about which the local variation occurs, VDDM, VWL, and the bit line voltage (VBL). Based on such simulations, a differential between VDDM and VWL can be identified that can optimize the margins as a function of the magnitude of the local variation, and the values of the global parameters, VDDM, and VBL. Generally, it is found that the margins are optimized by having a relatively lower VWL for higher VDDM. Moreover, it is also generally found that margins are optimized with a more negative differential (VWL<VDDM) for lower Vtn or for a lower ratio of Vtn to magnitude of Vtp. Thus, it may be desirable to select a different differential as a function of VDDM for different global parameters. As described above, off-chip equipment or on-chip circuits and sensors can be used to characterize the global parameters. Once the relation of the differential to VDDM for optimum margin is determined, a differential generating circuit is designed that will provide a trend that is essentially optimized within the restrictions of size, performance, and power.
In one embodiment, the selection of the differential between VDDM and VWL is relative to the value of a process dependent variable such as Vtn, and can be fixed by fuse, such as storage of trend selection circuit 210 shown in
The VDDM/VWL differential can also be selected dynamically to permit periodic or continual updating (with a circuit responsive to a given variable, such as Vtn, VDDM, or the temperature (T). If the differential is dynamic, the circuit can respond by changing the VDDM/VWL differential responsive to parameter variations including temperature (T) and changes in various cell performance impacting device characteristics that can occur over product lifetime (e.g. threshold shift). In this case, fuse-based programming is not generally used. Dynamic programming arrangements can include, for example, defining an initial VDDM/VWL differential at start-up or another time during operation by doing an internal self test and then dynamically updating the VDDM/VWL differential at a plurality of later times during circuit operation based on the condition or performance of one or more cell components (e.g. Vtn), the performance of the array, or based on external factors such as temperature. Alternatively, the circuit setting the differential, such as VWL differential generator 230 shown in
In one embodiment of the invention a memory array according to the present invention comprises a plurality of SRAM memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. The memory cells each include first and second cross-coupled inverters, the first inverter having a first latch node and the second inverter having a second latch node; and one or more pass transistor coupled to the first latch node and to the second latch node, one of the word lines being connected to a gate of the pass transistor and one of the bit lines being connected to a source or drain of the pass transistor. The array generally includes at least one controller for driving the plurality of word lines to a word line voltage (VWL) and for driving the plurality of bit lines to a bit line voltage (VBL). A low supply voltage for the array (VSSM) is coupled to a low voltage supply terminal of the cross-coupled inverters, and a high voltage supply for the array (VDDM) is coupled to a high voltage supply terminal of the cross-coupled inverters. In another embodiment, the memory array comprises a 5T SRAM memory cell. The array includes at least one voltage differential generating circuit according to the present invention operable for setting a relationship between VDDM and VWL based on VDDM compared to some reference or the differential can be compared to Vtn. Thus, in one embodiment, the voltage differential generating circuit may be programmable.
Particularly when across chip parametric variability is small, a centralized controller arrangement, such as shown for IC 202 in
Since small variations in VWL relative to VDDM (e.g. on the order of 10s of mv) have been found to generally have a large impact on SRAM performance, it is desirable to have the differential generated local to the memory array cells, so as to avoid voltage offsets due to distribution from a central controller, e.g. IR drops. With multiple arrays, such as a 4 M SRAM having 4×1 M arrays on a single chip, multiple circuits on the chip can be used to locally determine and locally set the VWL/VDDM differential. In this embodiment, there is motivation to have the differential circuit small in area and low in power.
In one embodiment, the measured parameter(s) obtained at wafer probe or final test includes a parameter predictive of the SRAM cell stability and write margins, e.g. Vtn. Setting VWL essentially equal to VDDM when VDDM=Vmin, and selectively, based on the measured parameter predictive of SRAM cell margins (such as when Vtn is high), introducing a differential when VDDM>Vmin so that VWL<VDDM when VDDM>Vmin relaxes the SNM/Vtrip/Iread trade-off as a function of VDDM and will allow further scaling of SRAM cells. Vmin may be a characteristic of the device design or may be programmed as specified by the application. Alternatively, Vmin may be determined by characterization of the chip.
In one embodiment, implementing one of the trends according to the invention as shown in
In one embodiment, the VDDM-VWL differential that is selected will be minimal (including zero and slightly negative so the VWL>VDDM) when VDDM is at its minimum value, and will be larger (generally ≧0) when VDDM is near its maximum value.
As noted above, rather than a digital signal, central controller can distribute an analog signal comprising a reference voltage to the local differential generating circuits. As noted above, the reference voltage may go to high impedance (transistor gates) inputs so as to reduce IR drops. Alternatively currents could be propagated around the SRAM die to eliminate the problems associated with local voltage drops. In this embodiment, a current can be generated at one port of the device. This current is sent around the die as required, terminating in a local current-to-voltage converter to generate the designated differential.
For example, in one embodiment of the invention, as shown in
Although an SRAM cell has generally been discussed in accordance with the arrays and method of the present invention, as described above the present invention is applicable to certain other memories, such as FeRAM and MRAM, and DRAM that may develop that use VDDM.
Moreover, it is appreciated by the inventors that cell and transistor technology variations, including array, bitline, or wordline orientation variations are contemplated in the context of the present invention.
The invention is also not limited to the use of silicon wafers, and may be implemented in association with the manufacture of various semiconductor devices, SRAM memory devices, or other memory devices, wherein the design and optimization of an SRAM cell, potential data upsets, and power consumption is an issue, where cell access is to be limited only to the memory area being used, and wherein the various aspects thereof may be applied.
Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and/or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the following claims.
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|U.S. Classification||365/189.09, 365/227, 365/154|
|International Classification||G11C11/00, G11C5/14|
|Cooperative Classification||G11C8/08, G11C11/413, G11C5/14|
|European Classification||G11C8/08, G11C5/14, G11C11/413|
|Nov 5, 2007||AS||Assignment|
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOUSTON, THEODORE W.;MARSHALL, ANDREW;REEL/FRAME:020071/0277;SIGNING DATES FROM 20070817 TO 20070820
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOUSTON, THEODORE W.;MARSHALL, ANDREW;SIGNING DATES FROM20070817 TO 20070820;REEL/FRAME:020071/0277
|Aug 25, 2014||FPAY||Fee payment|
Year of fee payment: 4