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Publication numberUS7915167 B2
Publication typeGrant
Application numberUS 11/240,440
Publication dateMar 29, 2011
Filing dateSep 29, 2005
Priority dateSep 29, 2004
Fee statusPaid
Also published asCN101027763A, CN103560150A, CN103560150B, DE112005002302B4, DE112005002302T5, US7332439, US8344452, US20060068590, US20060068591, US20080142840, US20110156145, US20160308014, WO2006039597A2, WO2006039597A3
Publication number11240440, 240440, US 7915167 B2, US 7915167B2, US-B2-7915167, US7915167 B2, US7915167B2
InventorsMarko Radosavljevic, Amlan Majumdar, Suman Datta, Jack Kavalieros, Brian S. Doyle, Justin K. Brask, Robert S. Chau
Original AssigneeIntel Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Fabrication of channel wraparound gate structure for field-effect transistor
US 7915167 B2
A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
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1. A method for fabricating a transistor comprising:
forming a dummy gate over a semiconductor body where the body is disposed on a first dielectric layer;
forming source and drain regions in the body thereby defining a channel region in the body between the source and drain regions;
forming a second dielectric layer over the first dielectric layer;
removing the dummy gate;
seeding the first dielectric layer under the channel region with ions which enhance the etching of the first dielectric layer;
subsequently etching the first dielectric layer to define an opening under the channel region in the first dielectric layer; and
forming a gate insulation and a conductive gate surrounding the channel region.
2. The method defined by claim 1, wherein the seeding of the first dielectric layer comprises implanting ions at angle of θ angle with respect to normal from a wafer on which the fabrication is occurring.
3. The method defined by claim 2, wherein one of the angles 0 is obtained by rotating the wafer by 180.
4. The method defined by claim 3, wherein the ions are electrically inactive with respect to the operation of the transistor.
5. The method defined by claim 4, including annealing the transistor after the seeding of the first dielectric layer.
6. The method defined by claim 5, including forming a high-k dielectric layer on the channel regions of the body following the etching of the first dielectric layer.
7. The method defined by claim 1, wherein atomic layer deposition is used for forming the gate insulation and conductive gate.
8. The method defined by claim 7, wherein the gate has a work function between 3.9 to 5.2 eV.
9. The method defined by claim 8, including:
using a first ion implantation of electrically active ions in alignment with a dummy gate to form a tip source and a tip drain region;
forming spacers on sides of the dummy gate;
using a second ion implantation of electrically active ions in alignment with the spacers to form a main source region and a main drain region.
10. A method comprising:
using a replacement gate process to expose a channel region of a transistor body disposed on a dielectric layer;
implanting ions which enhance the etching of the dielectric layer into the dielectric layer underlying the channel region;
subsequent to the implanting ions, etching the dielectric layer; and
forming a gate insulation and gate substantially surrounding the channel region including underlying the channel region.
11. The method defined by claim 10, wherein the ions are implanted at the angles of θ.
12. The method defined by claim 11, wherein the ions are electrically inert with respect to the operation of the transistor.
13. The method defined by claim 10, wherein the metal gate has a work function of between 3.9 to 5.2 eV.
14. The method defined by claim 10, wherein the replacement gate process includes a polysilicon dummy gate which is removed to expose the channel region.
15. The method defined by claim 14, wherein the ions are implanted at the angles of θ.
16. The method defined by claim 10, including the annealing of the transistor following the implanting of the ions used to enhance the etching.
17. The method defined by claim 10, wherein the dielectric layer comprises a buried oxide of a silicon-oxide-insulative substrate.
18. The method defined by claim 10, wherein the implanted ions are electrically inert.
19. The method defined by claim 18, wherein the ions are silicon.
20. The method defined by claim 19, wherein the work function of the gate is between 3.9 to 5.2 eV.

The invention is in the field of Field-Effect Transistors.


The continuing trend in the fabrication of complementary metal-oxide-semiconductor (CMOS) transistors is to scale the transistors. Examples of transistors having reduced bodies along with tri-gate structures are shown in U.S. 2004/0036127. Other small transistors are delta-doped transistors formed in lightly doped or undoped epitaxial layers grown on a heavily doped substrate. See, for instance, “Metal Gate Transistor with Epitaxial Source and Drain Regions,” application Ser. No. 10/955,669, filed Sep. 29, 2004, assigned to the assignee of the present application.

The ability to continue scaling CMOS transistors to even smaller geometries is hindered by the off-state leakage current. Off-state current reduces the switching efficiency and robs system power. This is particularly significant in planar CMOS transistors, where substrate leakage paths account for most of the current flow in the off state. While three-dimensional structures such as tri-gates and fin-FETs are more scalable, since they have more effective electrostatic control, there still remains a leakage path in the channel.

One structure for providing a more completely wrapped around gate is described in “Nonplanar Semiconductor Device with Partially or Fully Wrapped Around Gate Electrode and Methods of Fabrication,” U.S. patent application Ser. No. 10/607,769, filed Jun. 27, 2003.


FIG. 1 is a cross-sectional, elevation view of a silicon-on-insulator (SOI) substrate.

FIG. 2 is a perspective view of the structure of FIG. 1, after the formation of a silicon body, sometimes referred to as a fin.

FIG. 3 illustrates the structure of FIG. 2, after a dummy gate is fabricated and during a first ion implantation step.

FIG. 4 illustrates the structure of FIG. 3, after spacers are fabricated and during a second ion implantation step.

FIG. 5 illustrates the structure of FIG. 4, after forming a dielectric layer and after the removal of the dummy gate.

FIG. 6 is a cross-sectional, elevation view of the structure of FIG. 5 through section line 6-6 of FIG. 5.

FIG. 7 illustrates the structure of FIG. 6 during an ion implantation step.

FIG. 8 illustrates the structure of FIG. 7 after an etching step which removes the BOX under the channel region. This view is generally through section line 8-8 of FIG. 5.

FIG. 9 is an enlarged view of the region beneath the gate after the formation of a gate dielectric layer and a gate metal.

FIG. 10 is a cross-sectional, elevation view taken through the same plane as FIG. 6, this view illustrates the formation of the gate encircling the entire channel region of a semiconductor body.


A process for fabricating CMOS field-effect transistors and the resultant transistors are described. In the following description, numerous specific details are set forth, such as specific dimensions and chemical regimes, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as cleaning steps, are not described in detail, in order to not unnecessarily obscure the present invention. Also, in the description below, the fabrication of a single transistor is described. As will be appreciated in the typical integrated circuit, both n and p channel transistors are fabricated.

In one embodiment, transistors are fabricated on a buried oxide layer (BOX) 20 which is disposed on a silicon substrate 21 shown in FIG. 1. Transistor bodies are fabricated from a monocrystalline, silicon layer 24 disposed on BOX 20. This silicon-on-insulation (SOI) substrate is well-known in the semiconductor industry. By way of example, the SOI substrate is fabricated by bonding the oxide layer 20 and silicon layer 24 onto the substrate 21, and then planarizing the layer 24 until it is relatively thin. Other techniques are known for forming an SOI substrate including, for instance, the implantation of oxygen into a silicon substrate to form a buried oxide layer. Other semiconductor materials, other than silicon, may also be used such as gallium arsenide.

As will be seen, the BOX is seeded through ion implantation beneath the channel region of a transistor to make the oxide more readily etchable than the overlying silicon body. An electrically inactive species is implemented so as to not alter the electrical characteristics of the semiconductor body. Then, after removal of the BOX beneath the channel, a gate insulator and gate are formed entirely around the channel.

Referring to FIG. 1, the layer 24 may be selectively ion implanted with a p type dopant in regions where n channel transistors are to be fabricated, and with an n type dopant in those regions where p channel devices are to be fabricated. This is used to provide the relatively light doping typically found in the channel regions of MOS devices fabricated in a CMOS integrated circuit.

A protective oxide is disposed on the silicon layer 24 followed by the deposition of a silicon nitride layer (both not shown). The nitride layer acts as a hard mask to define silicon bodies such as the silicon body 25 of FIG. 2. By way of example, the body 25 may have a height and width of 20-30 nm.

An oxide (not shown) which subsequently acts as an etchant stop is formed over body 25. A polysilicon layer is formed over the structure of FIG. 2 and etched to define a dummy gate 30 which extends over the body 25 as seen in FIG. 3. The region of the body 25 below the dummy gate 30, as will be seen, is the channel region in this replacement gate process. Once the dummy gate 30 has been defined, phosphorous or arsenic may be implanted into the body 25 for an n channel transistor, or boron for a p channel transistor in alignment with the dummy gate, as illustrated by the ion implantation 26. This ion implantation defines the tip or extension source and drain regions frequently used in CMOS transistors.

Now, a layer of silicon nitride is conformally deposited over the structure of FIG. 3 to fabricate the spacers 38 shown in FIG. 4. Ordinary, well-known, anisotropic etching is used to fabricate the spacers. In one embodiment, a carbon-doped nitride, doped with 5-13% carbon concentration is used for the spacers. After the spacer formation, the main part of the source and drain regions are formed through ion implantation 35 shown in FIG. 4. For the n channel transistor, arsenic or phosphorous is used with an implant dose of up to 11019-11020 atoms/cm3. A similar dose range of boron may be used for a p channel transistor.

Following the implantation of the main source and drain region, the silicon body 25, to the extent that it extends beyond the spacers 38, receives a silicide or salicide layer 39 as is often done on exposed silicon in field-effect transistors.

An annealing step to activate the source and drain dopant is used, also commonly used cleaning steps common in the fabrication of a field-effect transistor are not shown.

A dielectric layer 40 is now conformally deposited over the structure of FIG. 4, as shown in FIG. 5. This may comprise a silicon dioxide layer which will become an interlayer dielectric (ILD) in an integrated circuit or a low-k ILD may be used. Alternatively, a sacrificial dielectric layer may be used. In any event, the layer 40 typically has the mechanical strength to withstand a planarization process such as chemical mechanical polishing (CMP) so that it may be polished level with the top of the spacers 38.

After the deposition and planarization of the dielectric layer 40, a wet etch is used to remove the dummy polysilicon gate 30, leaving the opening 45, as shown in FIG. 5. (A dummy gate oxide (not shown) may also be removed.) The cross-sectional view of FIG. 6, taken through section line 6-6 of FIG. 5, also shows the body 25. This view is a better reference for the ion implantation of FIG. 7.

Referring to FIG. 7, the wafer having the structure of FIG. 6 is now ion implanted at an angle of θ relative to the normal of the wafer with the wafer at two different angles of rotation. These angles of rotation are in the plane of the wafer and are referred to below as the wafer rotation angle. The angle between the normal to the wafer and the ion beam is referred to below as the ion implantation angle θ.

First, for instance, the wafer is ion implanted at the angle θ with the wafer rotated to an angle of 90. Then, implantation occurs again at the angle θ with the wafer rotated to an angle of 270. The wafer rotation angles of 90 and 270, shown in FIG. 2 are perpendicular to the body 25. Since 90 and 270 are 180 apart, the net effect is the same as implanting at θ, as shown in FIG. 7. The implanted ions are implanted into the dielectric 40, in the exposed portions of the BOX 20, as well as under the channel region of the body 25 and in the channel region of body 25. θ may be in the range of 30-60, the angle is selected so as to insure that the ions are implanted into all the BOX 20 under the body 25.

Ions seeded into the upper portion of BOX 20, shown as region 20 a, cause BOX 20 to be more readily etched and to provide better selectivity between the region 20 a versus the body 25 and the non-implanted regions of BOX 20. The ions alter the crystalline nature of BOX 20, in effect, amorphizing or modifying the structure making it less resistant to selected chemistry without making body 25 or non-implanted regions of the BOX 20 more readily etched. More specifically, by selecting suitable ions and a suitable wet etchant, the implanted region 20 a is etched more readily in the presence of the wet etchant compared to the body 25 or unexposed portions of the BOX 20, allowing the implanted portion of the BOX 20 (region 20 a), including beneath the body 25 to be removed without substantially affecting the dimensions of the body 25. A discussion of pre-etch implantation may be found in U.S. 2004/0118805. Wet etchant discrimination ratio of 6-1 between implanted silicon dioxide and non-implanted silicon dioxide are achievable.

Ions selected for the implantation shown in FIG. 7 are electrically inactive in the BOX 20 and the semiconductor body 25. For example, silicon can be implanted where the body 25 is a silicon body, to disrupt the structure of the silicon dioxide without altering the electrical properties of the body 25. In subsequent annealing, the additional silicon ions implanted in body 25 are re-crystallized and have substantially no impact on the transistor characteristics. Further, electrically inactive species such as nitrogen or halogens (fluorine, chlorine, etc.) may be implanted to create structural alteration with the resultant modification of the wet etch rate without adversely effecting the electrical behavior of the transistor. These species remain in the silicon without altering the electrical characteristics of the transistor which is subsequently formed.

Relatively low implantation energies and dose levels are adequate to sufficiently seed the BOX 20 beneath the body 25 to allow removal of the oxide below the body. For example, energy levels for implanting silicon in the range of 0.5-2.0 KeV, to a dose of 11018 atoms/cm2 are sufficient for a silicon body having dimensions of approximately 2020 nm.

Following the implantation, a wet etch is used to remove the region 20 a including the region 20 a under the body 25. Many wet chemical etchants are known to be effective and controllable on such thin film materials. As would be apparent to one skilled in the art, they may be appropriately matched with substrate and thin film materials, such as those above, to provide desirable selective etching. Suitable etchants include but are not limited to phosphoric acid (H3PO4), hydrofluoric acid (HF), buffered HF, hydrochloric acid (HCl), nitric acid (HNO3), acetic acid (CH3COOH), ammonium hydroxide (NH4OH), alcohols, potassium permanganate (KMnO4), ammonium fluoride (NH4F), and others, as would be listed in known wet chemical etching references such as Thin Film Processes, Academic Press (1978), edited by John L. Vossen and Werner Kern. Mixtures of these and other etchant chemicals are also conventionally used.

The wet etchant of the region 20 a of layer 20 defines a trench aligned with the opening 45 which extends beneath the body 25. This trench is best seen in FIG. 8 as trench 50. Note, this view is taken through the section lines 8-8 of FIG. 5. In this view the source and drain regions 55 are visible. The trench 50 is encircled with the circle 60, and enlarged in FIG. 9, as will be subsequently discussed.

A gate dielectric 62 may now be formed on exposed surfaces which includes the sides, top and bottom of the body 25. The gate dielectric has a high dielectric constant (k), such as a metal oxide dielectric, for instance, HfO2 or ZrO2 or other high k dielectrics, such as PZT or BST. The gate dielectric may be formed by any well-known technique such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Alternately, the gate dielectric may be a grown dielectric. For instance, the gate dielectric 62, may be a silicon dioxide film grown with a wet or dry oxidation process to a thickness between 5-50 Å.

Following this a gate electrode (metal) layer 63 is formed over the gate dielectric layer 62. The gate electrode layer 62 may be formed by blanket deposition of a suitable gate electrode material. In one embodiment, a gate electrode material comprises a metal film such as tungsten, tantalum, titanium and/or nitrides and alloys thereof. For the n channel transistors, a work function in the range of 3.9 to 4.6 eV may be used. For the p channel transistors, a work function of 4.6 to 5.2 eV may be used. Accordingly, for substrates with both n channel and p channel transistors, two separate metal deposition processes may need to be used. Only approximately 100 Å of the metal needs to be formed through ALD to set the work function. The remainder of the gate may be formed of polysilicon.

Standard processing is now used to complete the transistor of FIG. 10.

The formation of the gate beneath the body 25 may not be as well defined as the gate on the sides and top of the body 25. For instance, as shown in FIG. 9, a void 64 may occur. Such a void, however, will not affect the performance of the transistor. Moreover, some of the BOX 20 (not shown) may remain directly under the body 25 in the trench 50. This oxide, which is subsequently covered with both the high-k dielectric 62 and the metal 63, will not meaningfully impact transistor performance.

The above described method may also be used on other three dimensional (3D) semiconductor bodies such as semiconducting carbon nanotubes, Group 3-5 nanowires and silicon nanowires. The surface upon which the 3D semiconductor nanostructure rests is ion implanted to alter its etching rate to make it more etchable than the nanostructure.

Thus, a method has been described for forming a gate entirely around a silicon body in a replacement gate process. Ion implantation damages the insulation beneath the semiconductor body in the channel region allowing it to be more readily etched. ALD is then used to form a dielectric and gate entirely around the semiconductor body for one embodiment.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4487652Mar 30, 1984Dec 11, 1984Motorola, Inc.Slope etch of polyimide
US4818715Jul 9, 1987Apr 4, 1989Industrial Technology Research InstituteMethod of fabricating a LDDFET with self-aligned silicide
US4906589Feb 6, 1989Mar 6, 1990Industrial Technology Research InstituteInverse-T LDDFET with self-aligned silicide
US4907048Nov 23, 1987Mar 6, 1990Xerox CorporationDouble implanted LDD transistor self-aligned with gate
US4994873Dec 26, 1989Feb 19, 1991Motorola, Inc.Local interconnect for stacked polysilicon device
US4996574Jun 30, 1989Feb 26, 1991Fujitsu LimitedMIS transistor structure for increasing conductance between source and drain regions
US5124777Jan 3, 1991Jun 23, 1992Samsung Electronics Co., Ltd.Dielectric medium for capacitor of semiconductor device
US5179037Dec 24, 1991Jan 12, 1993Texas Instruments IncorporatedIntegration of lateral and vertical quantum well transistors in the same epitaxial stack
US5216271Sep 27, 1991Jun 1, 1993Kabushiki Kaisha ToshibaBiCMOS device with low bandgap CMOS contact regions and low bandgap bipolar base region
US5308999Feb 24, 1993May 3, 1994Fujitsu LimitedMOS FET having a thin film SOI structure
US5338959Mar 30, 1993Aug 16, 1994Samsung Electronics Co., Ltd.Thin film transistor with three dimensional multichannel structure
US5346839Jan 8, 1993Sep 13, 1994Texas Instruments IncorporatedSidewall doping technique for SOI transistors
US5391506Jan 27, 1993Feb 21, 1995Kawasaki Steel CorporationManufacturing method for semiconductor devices with source/drain formed in substrate projection.
US5466621Oct 25, 1993Nov 14, 1995Hitachi, Ltd.Method of manufacturing a semiconductor device having silicon islands
US5482877Feb 16, 1994Jan 9, 1996Samsung Electronics Co., Ltd.Method for making a semiconductor device having a silicon-on-insulator structure
US5514885Jan 13, 1995May 7, 1996Myrick; James J.SOI methods and apparatus
US5521859Jan 17, 1995May 28, 1996Fujitsu LimitedSemiconductor memory device having thin film transistor and method of producing the same
US5543351Oct 31, 1994Aug 6, 1996Matsushita Electric Industrial Co., Ltd.Method of producing electrically insulated silicon structure
US5545586May 13, 1994Aug 13, 1996Nec CorporationMethod of making a transistor having easily controllable impurity profile
US5563077Jun 20, 1995Oct 8, 1996Hyundai Electronics Industries Co., Ltd.Method of fabricating a thin film transistor having vertical channel
US5578513Apr 20, 1995Nov 26, 1996Mitsubishi Denki Kabushiki KaishaMethod of making a semiconductor device having a gate all around type of thin film transistor
US5658806Oct 26, 1995Aug 19, 1997National Science CouncilMethod for fabricating thin-film transistor with bottom-gate or dual-gate configuration
US5682048May 17, 1996Oct 28, 1997Nissan Motor Co., Ltd.Groove-type semiconductor device
US5698869Sep 13, 1995Dec 16, 1997Kabushiki Kaisha ToshibaInsulated-gate transistor having narrow-bandgap-source
US5701016Nov 24, 1995Dec 23, 1997Kabushiki Kaisha ToshibaSemiconductor device and method for its manufacture
US5716879Jan 13, 1997Feb 10, 1998Goldstar Electron Company, Ltd.Method of making a thin film transistor
US5739544Dec 12, 1995Apr 14, 1998Matsushita Electric Industrial Co., Ltd.Quantization functional device utilizing a resonance tunneling effect and method for producing the same
US5770513May 2, 1995Jun 23, 1998Mitsubishi Denki Kabushiki KaishaMethod for producing semiconductor device with heat dissipation structure
US5804848Oct 31, 1997Sep 8, 1998Sony CorporationField effect transistor having multiple gate electrodes surrounding the channel region
US5811324Feb 28, 1997Sep 22, 1998Lg Semicon Co., Ltd.Method for manufacturing thin film transistor
US5814895Dec 19, 1996Sep 29, 1998Sony CorporationStatic random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate
US5821629Jul 12, 1995Oct 13, 1998United Microelectronics CorporationBuried structure SRAM cell and methods for fabrication
US5827769Nov 20, 1996Oct 27, 1998Intel CorporationMethod for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
US5844278Sep 13, 1995Dec 1, 1998Kabushiki Kaisha ToshibaSemiconductor device having a projecting element region
US5880015Oct 14, 1994Mar 9, 1999Sgs-Thomson Microelectronics, Inc.Method of producing stepped wall interconnects and gates
US5888309Dec 29, 1997Mar 30, 1999Taiwan Semiconductor Manufacturing Company, Ltd.Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma
US5889304Jun 27, 1997Mar 30, 1999Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device
US5899710Feb 25, 1998May 4, 1999Sony CorporationMethod for forming field effect transistor having multiple gate electrodes surrounding the channel region
US5905285Feb 26, 1998May 18, 1999Advanced Micro Devices, Inc.Ultra short trench transistors and process for making same
US5908313Dec 31, 1996Jun 1, 1999Intel CorporationMethod of forming a transistor
US5952701Aug 18, 1997Sep 14, 1999National Semiconductor CorporationDesign and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
US5965914Dec 23, 1997Oct 12, 1999Mitsubishi Denki Kabushiki KaishaThin film transistor having a branched gate and channel
US5976767Oct 9, 1997Nov 2, 1999Micron Technology, Inc.Ammonium hydroxide etch of photoresist masked silicon
US6013926Apr 18, 1997Jan 11, 2000Mitsubishi Denki Kabushiki KaishaSemiconductor device with refractory metal element
US6018176Sep 8, 1997Jan 25, 2000Samsung Electronics Co., Ltd.Vertical transistor and memory cell
US6054355Jun 29, 1998Apr 25, 2000Kabushiki Kaisha ToshibaMethod of manufacturing a semiconductor device which includes forming a dummy gate
US6066869Oct 6, 1997May 23, 2000Micron Technology, Inc.Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US6087208Mar 31, 1998Jul 11, 2000Advanced Micro Devices, Inc.Method for increasing gate capacitance by using both high and low dielectric gate material
US6093621Apr 5, 1999Jul 25, 2000Vanguard International Semiconductor Corp.Method of forming shallow trench isolation
US6117741Jan 5, 1999Sep 12, 2000Texas Instruments IncorporatedMethod of forming a transistor having an improved sidewall gate structure
US6120846Dec 23, 1997Sep 19, 2000Advanced Technology Materials, Inc.Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor deposition
US6153485Nov 9, 1998Nov 28, 2000Chartered Semiconductor Manufacturing Ltd.Salicide formation on narrow poly lines by pulling back of spacer
US6163053Nov 5, 1997Dec 19, 2000Ricoh Company, Ltd.Semiconductor device having opposite-polarity region under channel
US6165880Jun 15, 1998Dec 26, 2000Taiwan Semiconductor Manufacturing CompanyDouble spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
US6174820Feb 16, 1999Jan 16, 2001Sandia CorporationUse of silicon oxynitride as a sacrificial material for microelectromechanical devices
US6218309Sep 30, 1999Apr 17, 2001Lam Research CorporationMethod of achieving top rounding and uniform etch depths while etching shallow trench isolation features
US6251729Dec 15, 1999Jun 26, 2001U.S. Philips CorporationMethod of manufacturing a nonvolatile memory
US6251763Jun 29, 1998Jun 26, 2001Kabushiki Kaisha ToshibaSemiconductor device and method for manufacturing same
US6252284Dec 9, 1999Jun 26, 2001International Business Machines CorporationPlanarized silicon fin device
US6261921Sep 14, 1999Jul 17, 2001Taiwan Semiconductor Manufacturing Co., Ltd.Method of forming shallow trench isolation structure
US6294416May 7, 1999Sep 25, 2001Texas Instruments-Acer IncorporatedMethod of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
US6317444Jun 12, 1998Nov 13, 2001Agere System Optoelectronics Guardian Corp.Optical device including carbon-doped contact layers
US6335251Apr 3, 2001Jan 1, 2002Kabushiki Kaisha ToshibaSemiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US6359311Jan 17, 2001Mar 19, 2002Taiwan Semiconductor Manufacturing Co., Ltd.Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same
US6376317Jun 28, 2000Apr 23, 2002Micron Technology, Inc.Methods for dual-gated transistors
US6391782Jun 20, 2000May 21, 2002Advanced Micro Devices, Inc.Process for forming multiple active lines and gate-all-around MOSFET
US6396108Nov 13, 2000May 28, 2002Advanced Micro Devices, Inc.Self-aligned double gate silicon-on-insulator (SOI) device
US6403981Aug 7, 2000Jun 11, 2002Advanced Micro Devices, Inc.Double gate transistor having a silicon/germanium channel region
US6407442Oct 26, 1995Jun 18, 2002Canon Kabushiki KaishaSemiconductor device, and operating device, signal converter, and signal processing system using the same semiconductor device
US6413802Oct 23, 2000Jul 2, 2002The Regents Of The University Of CaliforniaFinfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6413877Dec 22, 2000Jul 2, 2002Lam Research CorporationMethod of preventing damage to organo-silicate-glass materials during resist stripping
US6424015Nov 16, 2001Jul 23, 2002Hitachi, Ltd.Semiconductor integrated circuit device
US6437550Dec 27, 2000Aug 20, 2002Ricoh Company, Ltd.Voltage generating circuit and reference voltage source circuit employing field effect transistors
US6459123Apr 30, 1999Oct 1, 2002Infineon Technologies Richmond, LpDouble gated transistor
US6472258Nov 13, 2000Oct 29, 2002International Business Machines CorporationDouble gate trench transistor
US6475869Feb 26, 2001Nov 5, 2002Advanced Micro Devices, Inc.Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6475890Feb 12, 2001Nov 5, 2002Advanced Micro Devices, Inc.Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6483156Mar 16, 2000Nov 19, 2002International Business Machines CorporationDouble planar gated SOI MOSFET structure
US6495403Oct 5, 2000Dec 17, 2002Stmicroelectronics S.A.Gate-all-around semiconductor device and process for fabricating the same
US6498096Mar 8, 2001Dec 24, 2002International Business Machines CorporationBorderless contact to diffusion with respect to gate conductor and methods for fabricating
US6506692May 30, 2001Jan 14, 2003Intel CorporationMethod of making a semiconductor device using a silicon carbide hard mask
US6525403Sep 24, 2001Feb 25, 2003Kabushiki Kaisha ToshibaSemiconductor device having MIS field effect transistors or three-dimensional structure
US6534807Aug 13, 2001Mar 18, 2003International Business Machines CorporationLocal interconnect junction on insulator (JOI) structure
US6537862Dec 18, 2001Mar 25, 2003Samsung Electronics Co., Ltd.Method of forming semiconductor device having a GAA type transistor
US6537885May 9, 2002Mar 25, 2003Infineon Technologies AgTransistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US6537901Jun 25, 2001Mar 25, 2003Hynix Semiconductor Inc.Method of manufacturing a transistor in a semiconductor device
US6562665Oct 16, 2000May 13, 2003Advanced Micro Devices, Inc.Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US6583469Jan 28, 2002Jun 24, 2003International Business Machines CorporationSelf-aligned dog-bone structure for FinFET applications and methods to fabricate the same
US6605498Mar 29, 2002Aug 12, 2003Intel CorporationSemiconductor transistor having a backfilled channel material
US6610576Dec 13, 2001Aug 26, 2003International Business Machines CorporationMethod for forming asymmetric dual gate transistor
US6611029Nov 8, 2002Aug 26, 2003Advanced Micro Devices, Inc.Double gate semiconductor device having separate gates
US6630388Mar 13, 2002Oct 7, 2003National Institute Of Advanced Industrial Science And TechnologyDouble-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US6635909Mar 19, 2002Oct 21, 2003International Business Machines CorporationStrained fin FETs structure and method
US6642090Jun 3, 2002Nov 4, 2003International Business Machines CorporationFin FET devices from bulk semiconductor and method for forming
US6642114Sep 19, 2001Nov 4, 2003Fujitsu LimitedSemiconductor device and method for fabricating the same
US6645797Dec 6, 2002Nov 11, 2003Advanced Micro Devices, Inc.Method for forming fins in a FinFET device using sacrificial carbon layer
US6645826Mar 7, 2002Nov 11, 2003Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating the same
US6656853Dec 26, 2001Dec 2, 2003Nec Electronics CorporationEnhanced deposition control in fabricating devices in a semiconductor wafer
US6657259Dec 4, 2001Dec 2, 2003International Business Machines CorporationMultiple-plane FinFET CMOS
US6664160Nov 19, 2002Dec 16, 2003Hyundai Electronics Industries Co., Ltd.Gate structure with high K dielectric
US6680240Jun 25, 2002Jan 20, 2004Advanced Micro Devices, Inc.Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US6689650Sep 27, 2001Feb 10, 2004International Business Machines CorporationFin field effect transistor with self-aligned gate
US6693324Sep 6, 1996Feb 17, 2004Mitsubishi Denki Kabushiki KaishaSemiconductor device having a thin film transistor and manufacturing method thereof
US6696366Jun 30, 1999Feb 24, 2004Lam Research CorporationTechnique for etching a low capacitance dielectric layer
US6706571Oct 22, 2002Mar 16, 2004Advanced Micro Devices, Inc.Method for forming multiple structures in a semiconductor device
US6709982Nov 26, 2002Mar 23, 2004Advanced Micro Devices, Inc.Double spacer FinFET formation
US6713396Apr 29, 2002Mar 30, 2004Hewlett-Packard Development Company, L.P.Method of fabricating high density sub-lithographic features on a substrate
US6716684Nov 13, 2000Apr 6, 2004Advanced Micro Devices, Inc.Method of making a self-aligned triple gate silicon-on-insulator device
US6716690Mar 12, 2003Apr 6, 2004Advanced Micro Devices, Inc.Uniformly doped source/drain junction in a double-gate MOSFET
US6730964Oct 1, 2002May 4, 2004Hitachi, Ltd.Semiconductor device and method of producing the same
US6744103Sep 6, 2002Jun 1, 2004Spinnaker Semiconductor, Inc.Short-channel schottky-barrier MOSFET device and manufacturing method
US6756657Jan 28, 1999Jun 29, 2004Semiconductor Energy Laboratory Co., Ltd.Method of preparing a semiconductor having controlled crystal orientation
US6764884Apr 3, 2003Jul 20, 2004Advanced Micro Devices, Inc.Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US6770516Sep 5, 2002Aug 3, 2004Taiwan Semiconductor Manufacturing CompanyMethod of forming an N channel and P channel FINFET device on the same semiconductor substrate
US6774390Feb 21, 2003Aug 10, 2004Kabushiki Kaisha ToshibaSemiconductor device
US6780694Jan 8, 2003Aug 24, 2004International Business Machines CorporationMOS transistor
US6787402Apr 27, 2001Sep 7, 2004Advanced Micro Devices, Inc.Double-gate vertical MOSFET transistor and fabrication method
US6787406Aug 12, 2003Sep 7, 2004Advanced Micro Devices, Inc.Systems and methods for forming dense n-channel and p-channel fins using shadow implanting
US6787439Nov 8, 2002Sep 7, 2004Advanced Micro Devices, Inc.Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6787845Mar 21, 2001Sep 7, 2004Commissariat A L'energie AtomiqueMetal source and drain mos transistor
US6787854Mar 12, 2003Sep 7, 2004Advanced Micro Devices, Inc.Method for forming a fin in a finFET device
US6790733Mar 28, 2003Sep 14, 2004International Business Machines CorporationPreserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
US6794313Sep 20, 2002Sep 21, 2004Taiwan Semiconductor Manufacturing Company, Ltd.Oxidation process to improve polysilicon sidewall roughness
US6794718Dec 19, 2002Sep 21, 2004International Business Machines CorporationHigh mobility crystalline planes in double-gate CMOS technology
US6798000Jul 3, 2001Sep 28, 2004Infineon Technologies AgField effect transistor
US6800885Mar 12, 2003Oct 5, 2004Advance Micro Devices, Inc.Asymmetrical double gate or all-around gate MOSFET devices and methods for making same
US6800910Dec 31, 2002Oct 5, 2004Advanced Micro Devices, Inc.FinFET device incorporating strained silicon in the channel region
US6803631Jan 23, 2003Oct 12, 2004Advanced Micro Devices, Inc.Strained channel finfet
US6812075May 2, 2003Nov 2, 2004International Business Machines CorporationSelf-aligned dog-bone structure for FinFET applications and methods to fabricate the same
US6812111Nov 12, 2002Nov 2, 2004Samsung Electronics Co., Ltd.Methods for fabricating MOS transistors with notched gate electrodes
US6815277Aug 21, 2003Nov 9, 2004International Business Machines CorporationMethod for fabricating multiple-plane FinFET CMOS
US6821834Dec 4, 2002Nov 23, 2004Yoshiyuki AndoIon implantation methods and transistor cell layout for fin type transistors
US6831310Nov 10, 2003Dec 14, 2004Freescale Semiconductor, Inc.Integrated circuit having multiple memory types and method of formation
US6833588Oct 22, 2002Dec 21, 2004Advanced Micro Devices, Inc.Semiconductor device having a U-shaped gate structure
US6835614 *Jun 30, 2003Dec 28, 2004International Business Machines CorporationDamascene double-gate MOSFET with vertical channel regions
US6835618Aug 5, 2003Dec 28, 2004Advanced Micro Devices, Inc.Epitaxially grown fin for FinFET
US6838322May 1, 2003Jan 4, 2005Freescale Semiconductor, Inc.Method for forming a double-gated semiconductor device
US6844238Mar 26, 2003Jan 18, 2005Taiwan Semiconductor Manufacturing Co., LtdMultiple-gate transistors with improved gate control
US6849884May 16, 2003Feb 1, 2005International Business Machines CorporationStrained Fin FETs structure and method
US6852559Jun 30, 2003Feb 8, 2005Hynix Semiconductor Inc.Transistor of semiconductor device, and method for manufacturing the same
US6855606Feb 20, 2003Feb 15, 2005Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor nano-rod devices
US6855990Nov 26, 2002Feb 15, 2005Taiwan Semiconductor Manufacturing Co., LtdStrained-channel multiple-gate transistor
US6858478Feb 14, 2003Feb 22, 2005Intel CorporationTri-gate devices and methods of fabrication
US6867433Apr 30, 2003Mar 15, 2005Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6867460Nov 5, 2003Mar 15, 2005International Business Machines CorporationFinFET SRAM cell with chevron FinFET logic
US6869868Dec 13, 2002Mar 22, 2005Taiwan Semiconductor Manufacturing Company, Ltd.Method of fabricating a MOSFET device with metal containing gate structures
US6884154Feb 21, 2001Apr 26, 2005Shin-Etsu Handotai Co., Ltd.Method for apparatus for polishing outer peripheral chamfered part of wafer
US6885055Feb 4, 2003Apr 26, 2005Lee Jong-HoDouble-gate FinFET device and fabricating method thereof
US6890811Oct 6, 2003May 10, 2005Taiwan Semiconductor Manufacturing Company, Ltd.Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US6897527Apr 28, 2004May 24, 2005Advanced Micro Devices, Inc.Strained channel FinFET
US6902947May 9, 2003Jun 7, 2005Applied Materials, Inc.Integrated method for release and passivation of MEMS structures
US6909147May 5, 2003Jun 21, 2005International Business Machines CorporationMulti-height FinFETS
US6919238Jul 29, 2002Jul 19, 2005Intel CorporationSilicon on insulator (SOI) transistor and methods of fabrication
US6921691Mar 18, 2004Jul 26, 2005Infineon Technologies AgTransistor with dopant-bearing metal in source and drain
US6921702Jul 30, 2002Jul 26, 2005Micron Technology Inc.Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6921963Apr 23, 2004Jul 26, 2005Advanced Micro Devices, IncNarrow fin FinFET
US6921982Jul 21, 2003Jul 26, 2005International Business Machines CorporationFET channel having a strained lattice structure along multiple surfaces
US6924190Oct 24, 2002Aug 2, 2005Micron Technology, Inc.Use of gate electrode workfunction to improve DRAM refresh
US6960517Jun 30, 2003Nov 1, 2005Intel CorporationN-gate transistor
US6967351Dec 4, 2001Nov 22, 2005International Business Machines CorporationFinfet SRAM cell using low mobility plane for cell stability and method for forming
US6969878Apr 8, 2003Nov 29, 2005Stmicroelectronics S.A.Surround-gate semiconductor device encapsulated in an insulating medium
US6970373Oct 2, 2003Nov 29, 2005Intel CorporationMethod and apparatus for improving stability of a 6T CMOS SRAM cell
US6974738Apr 28, 2004Dec 13, 2005Intel CorporationNonplanar device with stress incorporation layer and method of fabrication
US7018551Dec 9, 2003Mar 28, 2006International Business Machines CorporationPull-back method of forming fins in FinFets
US7045401Jun 23, 2003May 16, 2006Sharp Laboratories Of America, Inc.Strained silicon finFET device
US7060539Mar 1, 2004Jun 13, 2006International Business Machines CorporationMethod of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
US7061055Dec 23, 2002Jun 13, 2006National Institute Of Advanced Industrial Science And TechnologyDouble-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US7071064Sep 23, 2004Jul 4, 2006Intel CorporationU-gate transistors and methods of fabrication
US7074623Jun 6, 2003Jul 11, 2006Amberwave Systems CorporationMethods of forming strained-semiconductor-on-insulator finFET device structures
US7074656Apr 29, 2003Jul 11, 2006Taiwan Semiconductor Manufacturing Company, Ltd.Doping of semiconductor fin devices
US7074662Jun 16, 2004Jul 11, 2006Samsung Electronics Co., Ltd.Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
US7105390 *Dec 30, 2003Sep 12, 2006Intel CorporationNonplanar transistors with metal gate electrodes
US7105891Jul 15, 2002Sep 12, 2006Texas Instruments IncorporatedGate structure and method
US7112478Jan 9, 2004Sep 26, 2006Acorn Technologies, Inc.Insulated gate field effect transistor having passivated Schottky barriers to the channel
US7122463Apr 29, 2004Oct 17, 2006Elpida Memory, Inc.Manufacturing method of semiconductor device
US7132360Jun 10, 2004Nov 7, 2006Freescale Semiconductor, Inc.Method for treating a semiconductor surface to form a metal-containing layer
US7138320Oct 27, 2004Nov 21, 2006Advanced Micro Devices, Inc.Advanced technique for forming a transistor having raised drain and source regions
US7141480Mar 26, 2004Nov 28, 2006Texas Instruments IncorporatedTri-gate low power device and method for manufacturing the same
US7141856Feb 17, 2004Nov 28, 2006Samsung Electronics Co., Ltd.Multi-structured Si-fin
US7154118Mar 31, 2004Dec 26, 2006Intel CorporationBulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7163851Aug 26, 2002Jan 16, 2007International Business Machines CorporationConcurrent Fin-FET and thick-body device fabrication
US7172943Sep 24, 2003Feb 6, 2007Taiwan Semiconductor Manufacturing Company, Ltd.Multiple-gate transistors formed on bulk substrates
US7183137Dec 1, 2003Feb 27, 2007Taiwan Semiconductor Manufacturing CompanyMethod for dicing semiconductor wafers
US7187043Mar 11, 2004Mar 6, 2007Sharp Kabushiki KaishaMemory function body, particle forming method therefor and, memory device, semiconductor device, and electronic equipment having the memory function body
US7238564Mar 10, 2005Jul 3, 2007Taiwan Semiconductor Manufacturing CompanyMethod of forming a shallow trench isolation structure
US7241653Jun 30, 2005Jul 10, 2007Intel CorporationNonplanar device with stress incorporation layer and method of fabrication
US7247578Dec 30, 2003Jul 24, 2007Intel CorporationMethod of varying etch selectivities of a film
US7250367Sep 1, 2004Jul 31, 2007Micron Technology, Inc.Deposition methods using heteroleptic precursors
US7250645Jan 22, 2004Jul 31, 2007Advanced Micro Devices, Inc.Reversed T-shaped FinFET
US7268024Nov 29, 2004Sep 11, 2007Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US7291886Jun 21, 2004Nov 6, 2007International Business Machines CorporationHybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
US7297600Dec 23, 2004Nov 20, 2007Samsung Electronics Co., Ltd.Methods of forming fin field effect transistors using oxidation barrier layers
US7304336Feb 13, 2004Dec 4, 2007Massachusetts Institute Of TechnologyFinFET structure and method to make the same
US7323710Jun 17, 2004Jan 29, 2008Samsung Electronics Co., Ltd.Fin field effect transistors having multi-layer fin patterns
US7329913Dec 27, 2004Feb 12, 2008Intel CorporationNonplanar transistors with metal gate electrodes
US20020011612Jul 30, 2001Jan 31, 2002Kabushiki Kaisha ToshibaSemiconductor device and method for manufacturing the same
US20020166838Jul 6, 2001Nov 14, 2002Institute Of MicroelectronicsSloped trench etching process
US20030067017Sep 13, 2002Apr 10, 2003Meikei IeongVariable threshold voltage double gated transistors and method of fabrication
US20030085194Nov 7, 2001May 8, 2003Hopkins Dean A.Method for fabricating close spaced mirror arrays
US20030098488Nov 27, 2001May 29, 2003O'keeffe JamesBand-structure modulation of nano-structures in an electric field
US20030151077Feb 13, 2002Aug 14, 2003Leo MathewMethod of forming a vertical double gate semiconductor device and structure thereof
US20040029345 *Jun 8, 2001Feb 12, 2004Simon DeleonibusDamascene architecture electronics storage and method for making same
US20040036126Aug 23, 2002Feb 26, 2004Chau Robert S.Tri-gate devices and methods of fabrication
US20040063286 *Jul 1, 2003Apr 1, 2004Kim Sung-MinField effect transistors having multiple stacked channels
US20040094807Nov 7, 2003May 20, 2004Chau Robert S.Tri-gate devices and methods of fabrication
US20040121531 *Jul 22, 2003Jun 24, 2004Karsten WieczorekMethod of removing features using an improved removal process in the fabrication of a semiconductor device
US20040126975Jun 24, 2003Jul 1, 2004Ahmed Shibly S.Double gate semiconductor device having separate gates
US20040191980Mar 27, 2003Sep 30, 2004Rafael RiosMulti-corner FET for better immunity from short channel effects
US20040195624Feb 24, 2004Oct 7, 2004National Taiwan UniversityStrained silicon fin field effect transistor
US20040203254Apr 11, 2003Oct 14, 2004Sharp Laboratories Of America, Inc.Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films
US20040238887Jun 25, 2002Dec 2, 2004Fumiyuki NiheyField-effect transistor constituting channel by carbon nano tubes
US20040262683Jun 27, 2003Dec 30, 2004Bohr Mark T.PMOS transistor strain optimization with raised junction regions
US20050093154Jul 26, 2004May 5, 2005Interuniversitair Microelektronica Centrum (Imec Vzw)Multiple gate semiconductor device and method for forming same
US20050104055Dec 22, 2004May 19, 2005Hynix Semiconductor Inc.Transistor of semiconductor device, and method for manufacturing the same
US20050127362Dec 10, 2003Jun 16, 2005Ying ZhangSectional field effect devices and method of fabrication
US20050139860Oct 21, 2004Jun 30, 2005Snyder John P.Dynamic schottky barrier MOSFET device and method of manufacture
US20050145941Jan 7, 2004Jul 7, 2005International Business Machines CorporationHigh performance strained silicon FinFETs device and method for forming same
US20050156202Nov 12, 2004Jul 21, 2005Hwa-Sung RheeAt least penta-sided-channel type of FinFET transistor
US20050156227Mar 15, 2005Jul 21, 2005Applied Intellectual Properties Co., Ltd.Nonvolatile memory with undercut trapping structure
US20050167766Jun 24, 2004Aug 4, 2005Atsushi YagishitaSemiconductor device and manufacturing method thereof
US20050224797Apr 1, 2004Oct 13, 2005Taiwan Semiconductor Manufacturing Company, Ltd.CMOS fabricated on different crystallographic orientation substrates
US20050227498Mar 31, 2004Oct 13, 2005International Business Machines CorporationMethod for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby
US20050230763Apr 15, 2004Oct 20, 2005Taiwan Semiconductor Manufacturing Co., Ltd.Method of manufacturing a microelectronic device with electrode perturbing sill
US20050233156Jun 24, 2005Oct 20, 2005Aviza Technology, Inc.System and method for forming multi-component dielectric films
US20060014338Jun 30, 2004Jan 19, 2006International Business Machines CorporationMethod and structure for strained finfet devices
US20060040054Aug 18, 2004Feb 23, 2006Pearlstein Ronald MPassivating ALD reactor chamber internal surfaces to prevent residue buildup
US20060086977Oct 25, 2004Apr 27, 2006Uday ShahNonplanar device with thinned lower body portion and method of fabrication
US20060154478Jan 12, 2005Jul 13, 2006Taiwan Semiconductor Manufacturing Co., Ltd.Contact hole structures and contact structures and fabrication methods thereof
US20060172479 *Mar 14, 2006Aug 3, 2006International Business Machines CorporationMethod of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions
US20060211184May 18, 2006Sep 21, 2006Boyd Diane CUltra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US20060286755 *Jun 15, 2005Dec 21, 2006Brask Justin KMethod for fabricating transistor with thinned channel
US20070093010Oct 25, 2005Apr 26, 2007Leo MathewMethod of making an inverted-T channel transistor
US20070108514Apr 28, 2004May 17, 2007Akira InoueSemiconductor device and method of fabricating the same
DE102039978A1 Title not available
EP0623963A1May 2, 1994Nov 9, 1994Siemens AktiengesellschaftMOSFET on SOI substrate
EP1202335A2Oct 15, 2001May 2, 2002International Business Machines CorporationMethod of fabricating semiconductor side wall fin
EP1566844A2Feb 18, 2005Aug 24, 2005Samsung Electronics Co., Ltd.Multi-gate transistor and method for manufacturing the same
GB2156149A Title not available
WO2002043151A1Jun 29, 2001May 30, 2002Hitachi, LtdSemiconductor device and method for fabricating the same
WO2004059726A1Dec 20, 2002Jul 15, 2004International Business Machines CorporationIntegrated antifuse structure for finfet and cmos devices
Non-Patent Citations
1Ali Javey et al., "Ballistic Carbon Nanotube Field-Effect Transistors", Nature, vol. 424, Aug. 7, 2003, pp. 654-657.
2Ali Javey et al., "High-K Dielectrics for Advanced Carbon-Nanotube Transistors and Logic Gates", Advance Online Publication, Published online, Nov. 17, 2002, pp. 1-6.
3Auth et al., "Vertical, Fully-Depleted, Surroundings Gate MOSFETS on Sub 0.1um Thick Silicon Pillars", 1996 54th Annual Device Reseach Conference Digest, (1996) pp. 108-109.
4Burenkov et al., "Corner Effect in Double and Triple Gate FinFets", IEEE 2003, pp. 135-138.
5Charles Kuo et al. "A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications, IEEE Transactions on Electron Devices", vol. 50, No. 12, Dec. 2003, pp. 2408-2416.
6Charles Kuo et al., "A Capacitorless Double-Gate DRAM Cell Design for High Density Applications", 2002 IEEE International Electron Devices Meeting Technical Digest, Dec. 2002, pp. 843-846.
7David M. Fried et al., "Improved Independent Gate N-Type FinFET Fabrication and Characterization", IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, pp. 592-594.
8David M. Fried et al., "Improved Independent Gate P-Type Independent-Gate FinFETs", IEEE Electron Device Letters, vol. 25, No. 4, Apr. 2004, pp. 199-201.
9Digh Hisamoto et al., "FinFet-A Self Aligned Double-Gate MOSFET Scalable to 20nm", IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
10E.C. Jones, "Doping Challenges in Exploratory Devices for High Performance Logic", 14th International Conference, Piscataway, NJ, Sep. 22-27, 2002, pp. 1-6.
11E.J. Nowak et al., "A Functional FinFET-DGCMOS SRAM Cell", International Electron Devices Meeting 2002, San Francisco, CA, Dec. 8-11, 2002, pp. 411-414.
12E.J. Nowak et al., "Scaling Beyond the 65nm Node with FinFET-DGCMOS", IEEE 2003, CICC, San Jose, CA, Sep. 21-24, 2033, pp. 339-342.
13Evert Seevinck et al., "Static-Noise Margin Analysis of MOS SRAM Cells" 1987 IEEE, IEEE Journals of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987.
14Fu-Liang Yang, et al., "5nm-Gate Nanowire FinFET" 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004 IEEE, pp. 196-197.
15Hisamoto et al. "A Folded-Channel MOSFET for Deep-sub-tenth Micron Era", 1998 IEEE International Electron Device Meeting Technical Digest, (1998) pp. 1032-1034.
16Hisamoto et al., "A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertical Ultrathin SOI MOSFET", IEEE Electron Device Letters, vol. 11 No. 1, (1990) pp. 36-38.
17Huang et al., "Sub 50nm FinFet: PMOS", 1999 IEEE International Electron Device Meeting Technical Digets, (1999) pp. 67-70.
18Jae-Hyoun Park, "Quantum-wired MOSFET Photodetector Fabricated by Conventional Photolithography on SOI Substrate", Nanotechnology, 2004, 4th IEEE Conference on Munich, Germany, Aug. 16-19, 2004, Piscataway, NJ, pp. 425-427, XP010767302.
19Jin et al., "Mobility Enhancement in Compressively Strained SiGe Surface Channel PMOS Transistors with Hf02/TiN Gate Stack", Proceedings of the First Joint International Symposium, 206th Meeting of Electrochemical Society, Oct. 2004, pp. 111-122.
20Jing Guo et al. "Performance Projections for Ballistic Carbon Nanotube Field-Effect Transistors" Applied Physics Letters, vol. 80, No. 17, Apr. 29, 2002, pp. 3192-2194.
21Jong-Tae Park et al., "Pi-Gate SOI MOSFET" IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001, pp. 405-406.
22L. Chang et al. "CMOS Circuit Performance Enhancement by Surface Orientation Optimization"IEEE Transactions on Electron Devices, IEEE Service Center, Piscataway, NJ vol. 51, No. 10, Oct. 2004, pp. 1621-1627 XP001211140.
23M. Ieong et al. "Three Dimensional CMOS Devices and Integrated Circuits", IEEE 2003, CICC, San Jose, CA, Sep. 21-24, 2003, pp. 207-214.
24M. Stadele et al., "A Comprehensive Study of Corner Effects in Tri-gate Transistors", IEEE 2004, pp. 165-168.
25Peter A. Stolk et al. "Modeling Statistical Dopant Fluctuations in MOS Transistors", 1998 IEEE, IEEE Transactions on Electron Devices, vol. 45, No. 9, Sep. 1998, pp. 1960-1971.
26R. Chau, "Advanced Metal Gate/High-K Dielectric Stacks for High-Performance CMOS Transistors", Proceedings of AVS 5th International Conference of Microelectronics and Interfaces, Mar. 2004, (3 pgs.).
27Richard Martel et al., "Carbon Nanotube Field Effect Transistors for Logic Applications" IBM, T.J. Watson Research Center, 2001 IEEE, IEDM 01, pp. 159-162.
28S.T. Chang et al., "3-D Simulation of Strained Si/SiGe Heterojunction FinFETs", pp. 176-177.
29Sung Min Kim, et al., A Novel Multi-channel Field Effect Transistor (McFET) on Bulk Si for High Performance Sub-80nm Application, IEDM 04-639, 2004 IEEE, pp. 27.4.1-27.4.4.
30T. Ludwig et al., "FinFET Technology for Future Microprocessors" 2003 IEEE, pgs. 33-34.
31T. M. Mayer, et al., "Chemical Vapor Deposition of Fluoroalkylsilane Monolayer Films for Adhesion Control in Microelectromechanical Systems" 2000 American Vacuum Society B 18(5), Sep.-Oct. 2000, pp. 2433-2440.
32T. Park et al. "PMOS Body-Tied FinFET (Omega MOSFET) Characteristics", Device Research Conference, Piscataway, NJ, Jun. 23-25, 2003, IEEE, pp. 33-34.
33T. Park et al., "Fabrication of Body-Tied FinFETs (Omega MOSFETS) Using Bulk Si Wafers", 2003 Symposia on VLSI Technology Digest of Technical Papers, Jun. 2003, pp. 135-136.
34T. Tanaka et al., Scalability Study on a Capacitorless 1T-DRAM: From Single-Gate PD-SOI to Double-Gate FinDram, 2004 IEEE International Electron Devices Meeting Technical Digest, Dec. 2004, (4 pgs.).
35Takashi Ohsawa et al., "Memory Design Using a One-Transistor Gain Cell on SOI", IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522.
36V. Subramanian et al. "A Bulk Si-Compatible Ultrathin-Body SOI Technology for Sub-100nm MOSFETS", Proceedings of the 57th Annual Device Reach Conference, (1999) pp. 28-29.
37W. Xiong, et al., "Corner Effect in Multiple-Gate SOI MOSFETs" 2003 IEEE, pp. 111-113.
38Weize Xiong, et al., "Improvement of FinFET Electrical Characteristics by Hydrogen Annealing" IEEE Electron Device Letters, vol. 25, No. 8, Aug. 2004, XP-001198998, pp. 541-543.
39Yang-Kyu Choi et al. "Sub-20nm CMOS FinFET Technologies", IEEE 2001, IEDM 01-421 to 01-424.
40Yang-Kyu Choi, et al., "A Spacer Patterning Technology for Nanoscale CMOS" IEEE Transactions on Electron Devices, vol. 49, No. 3, Mar. 2002, pp. 436-441.
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US9496338Mar 17, 2015Nov 15, 2016International Business Machines CorporationWire-last gate-all-around nanowire FET
US9502416Jan 8, 2016Nov 22, 2016Samsung Electronics Co., Ltd.Semiconductor device including transistors having different threshold voltages
US9607987Dec 21, 2011Mar 28, 2017Intel CorporationMethods for forming fins for metal oxide semiconductor device structures
US20110201186 *Apr 29, 2011Aug 18, 2011Infineon Technologies AgMethod and apparatus for reducing flicker noise in a semiconductor device
U.S. Classification438/689, 438/719
International ClassificationH01L21/302
Cooperative ClassificationH01L29/42392, H01L21/28194, H01L29/0673, H01L29/78618, H01L29/66742, H01L29/78696, Y10S438/957, Y10S438/926, H01L29/51, H01L29/66636, H01L29/6656, H01L29/7834, H01L29/517, H01L29/518, H01L21/28079, H01L29/66545, H01L29/495, H01L29/41775, H01L29/66606
European ClassificationH01L29/417D12, H01L29/51M, H01L29/78F2, H01L21/28E2C2D, H01L29/49D, H01L21/28E2B5, H01L29/66M6T6F10, H01L29/66M6T6F11E, H01L29/66M6T6F8, H01L29/66M6T6F11C
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