|Publication number||US7932586 B2|
|Application number||US 11/949,800|
|Publication date||Apr 26, 2011|
|Filing date||Dec 4, 2007|
|Priority date||Dec 18, 2006|
|Also published as||CN101207117A, CN101207117B, US20080142937|
|Publication number||11949800, 949800, US 7932586 B2, US 7932586B2, US-B2-7932586, US7932586 B2, US7932586B2|
|Inventors||Nan-Jang Chen, Hong-Chin Lin|
|Original Assignee||Mediatek Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Non-Patent Citations (4), Referenced by (3), Classifications (50), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit of U.S. Provisional Application No. 60/870,445 filed on Dec. 18, 2006, the entirety of which is incorporated herein by reference.
1. Field of the Invention
The invention relates to semiconductor packages, and in particular, to leadframe semiconductor packages mounted on a heat-sink and fabrication thereof.
2. Description of the Related Art
Requirements for faster signal transmissions are being driven by consumer demand for electronic devices with greater bandwidth capacity. Two main semiconductor packaging challenges encountered with high-speed data transmissions are: 1) thermal problems due to greater power consumption requirements; and 2) electrical problems due to higher signal bandwidth. In order to solve signal and power integrity (F3dB=0.35/tr) and heat dissipation (P=CL×f×VDD 2) issues, semiconductor packaging with both lower parasitic effects and lower costs are required for high speed integrated circuit applications.
Conventional semiconductor quad flat packages (QFPs) are used for low cost applications. The low cost applications require improved power dissipation benefit from the use of drop-in heat sink (DHS), die pad heat sink (DPH), exposed drop-in heat sink (EDHS), or exposed pad low profile in QFP (E-PAD LQFP), respectively. However, letting the heat sink act as a ground plane or floating ground plane does not improve the electrical performance effectively.
Alternatively, the semiconductor die 110 can be directly mounted on the heat sink 130 with adhesion 120. The heat sink 130 can also serve as a die pad. Both ends of the heat sink 130 are connected to the lead 150 through the polyimide tape 135, as shown in the die pad heat sink quad flat pack (DPH-QFP) 100 b in
U.S. Pat. Nos. 6,326,678 and 6,552,417, the entirety of which is hereby incorporated by reference, disclose molded plastic packages with heat sinks and enhanced electrical performance.
Taiwan Patent No. 1249829, the entirety of which is hereby incorporated by reference, discloses leadframe based semiconductor packages and fabrication methods thereof. An embedded and/or exposed heat sink is disposed between the chip and the leads to promote electrical and thermal performance.
Thus, a novel semiconductor packing processes is desired, which is capable of fulfilling both high performance and low production costs for applications related to high speed product integration requirements such as using the system in package (SiP) to integrate RF+BB chips or DTV+DDR SDRAMs.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention relates to integration of leadframe on heat sink (LOHS) with multi-chips (system) mounted in a package (SiP). Meanwhile, the heat sink can be pre-divided into several PWR and GND regions to reduce number of leads further shrinking package dimensions
An embodiment of the invention provides a system in package, comprising: a leadframe having extension leads, configured with divisional heat sinks serving as power and ground nets; a set of semiconductor dies attached by adhesive on the central region of the lead frame; a plurality of wire bonds electrically connecting the set of semiconductor dies to the leadframe and to the divisional heat sinks respectively; and an encapsulation layer enclosing the leadframe, but leaves the extension leads and the divisional heat sink uncovered, exposing a heat dissipating surface.
Another embodiment of the invention further provides an electronic system, comprising: a printed circuit board (PCB) with a plurality of different chips with different types of semiconductor packaging and electronic devices mounted thereon; a system in package (SiP) attached on the PCB with solders, wherein the system in package is operatically synergized with the plurality of different chips with different types of semiconductor packaging and electronic devices. The system in package (SiP) comprises a leadframe having extension leads, configured with divisional heat sinks serving as power and ground nets; a set of semiconductor dies attached by adhesive on the central region of the lead frame; a plurality of wire bonds electrically connecting the set of semiconductor dies to the leadframe and to the divisional heat sinks respectively; and an encapsulation layer enclosing the leadframe, but leaving the extension leads and the divisional heat sink uncovered, exposing a heat dissipating surface.
Another embodiment of the invention further provides a fabrication method for a system in package, comprising: assembling a leadframe having extension leads, configured with divisional heat sinks; attaching a set of semiconductor dies by adhesive on the central region of the lead frame; bonding wires connecting the set of semiconductor dies to the leadframe and to the divisional heat sinks respectively; and molding an encapsulation layer enclosing the leadframe, but leaving the extension leads and the divisional heat sink uncovered, exposing a heat dissipating surface.
Note that assembling of the leadframe comprises providing a top metal, a dielectric material and a bottom metal; pressing an assembly of the top metal, a dielectric material and a bottom metal; etching the top metal to create a leadframe with extension leads and an opening at a central region thereof; etching bottom metal to create divisional heat sinks; forming through holes proliferating the assembly; removing the dielectric material within the opening; forming a solder mask at the peripheral region of the leadframe; and electroplating a metal on the wirebonding area.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact or not in direct contact.
The LOHS-SiP 400 further comprises an interconnection section 432 as a bridge electrically connecting the set of semiconductor dies and the divisional heat sinks by wire bonds. A die paddle 436 is optionally disposed on the central region of the lead frame 440 for supporting the set of semiconductor dies 420 and 450. The LOHS-SiP 400 is mounted on a printed circuit board (PCB) 480 with solders 470 and 475.
The leadframe and the heat sink are fabricated by compatible semiconductor processes, and then bonded with the stacked chips. The added heat sink not only improves heat removal, but also creates several power and ground planes. For example, the heat sink can be pre-divided into several PWR/GND regions to reduce number of leads further shrinking package dimensions. Since the number of the leads can be thus reduced, better signal integrity and power integrity with fine lead pitch can also be achieved. Furthermore, the power and ground planes are bonded to the corresponding power and ground pads on the die and then soldered to the power and ground nets on the printed circuit board (PCB). Since power and ground do not need to go through the leads on the COHS-LF package, there is more space available to design the lead geometry for high-speed application, and therefore increased opportunity to reduce the package size.
Since the abovementioned LOHS structures include a solder mask, the contact region with injection mold is flat. As such, the dam bar design is unnecessary, thus subsequent conventional deflash/trim or dejunk/trimming steps are omitted.
The ground divisional heat sinks beneath the leads allow for controlling of impedance.
Heat flows (Th) from the higher temperature chip to the lower temperature ambient outer environment. Therefore, a higher thermal conductivity (κ) between chip and ambient enhances heat removal (e.g., copper κ≈400 W/mK). Thermal and electrical analysis of the package with chip surface attached to the exposed heat sink showed it had even smaller temperature increment, less signal losses and cross-talk than the conventional BGA package and LOC-TSOP packages.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
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|TW249829B||Title not available|
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|3||"Design and Evaluation of Chip on Heat Sink Quad Flat Package (COHS-QFP) for Consumer Electronics" iMAPS—Taiwan 2005 Technical Symposium, pp. 260-264, Jun. 24-25, 2005.|
|4||English abstract of CN1819187.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8963305 *||Sep 21, 2012||Feb 24, 2015||Freescale Semiconductor, Inc.||Method and apparatus for multi-chip structure semiconductor package|
|US9466588||Feb 23, 2015||Oct 11, 2016||Freescale Semiconductor, Inc.||Method and apparatus for multi-chip structure semiconductor package|
|US20140084432 *||Sep 21, 2012||Mar 27, 2014||Freescale Semiconductor, Inc.||Method and apparatus for multi-chip structure semiconductor package|
|U.S. Classification||257/675, 257/666, 257/706, 257/777, 257/686|
|Cooperative Classification||H01L2924/181, H01L2924/00014, H01L2924/351, H01L24/48, H01L2924/01023, H01L2924/14, H01L2924/01046, H01L2224/32245, H01L2224/48247, H01L2924/01006, H01L2924/01082, H01L23/49541, H01L2224/4824, H01L2224/4911, H01L2224/48091, H01L2924/01087, H01L2224/4826, H01L2224/49109, H01L2924/19041, H01L24/49, H01L2924/1433, H01L2924/01074, H01L2924/014, H01L23/3107, H01L2224/73215, H01L23/49575, H01L23/4334, H01L2924/01047, H01L23/49589, H01L2924/01029, H01L2924/3011, H01L2924/30107, H01L2924/01079, H01L2924/01013, H01L2924/3025, H01L2924/01028, H01L2924/01078, H01L2924/01033, H01L2224/73265|
|European Classification||H01L23/495G, H01L23/433E, H01L23/495L, H01L23/495Q, H01L24/49|
|Dec 4, 2007||AS||Assignment|
Owner name: MEDIATEK INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, NAN-JANG;LIN, HONG-CHIN;REEL/FRAME:020190/0580
Effective date: 20071113
|Oct 27, 2014||FPAY||Fee payment|
Year of fee payment: 4