|Publication number||US7936191 B2|
|Application number||US 11/963,857|
|Publication date||May 3, 2011|
|Filing date||Dec 24, 2007|
|Priority date||Dec 25, 2006|
|Also published as||US20080150595|
|Publication number||11963857, 963857, US 7936191 B2, US 7936191B2, US-B2-7936191, US7936191 B2, US7936191B2|
|Original Assignee||Realtek Semiconductor Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Referenced by (5), Classifications (8), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to start-up reset circuits and related methods, and more particularly, to start-up reset circuits and related methods adaptive to low voltage systems.
2. Description of the Prior Art
In current electronic devices, in order to make the circuit therein operate normally, it is typical to send a start-up reset signal (which is typically labeled as “RESET”) to all circuit components that require reset operations to have correct initial values, to ensure correct further operations.
A conventional start-up reset circuit utilizes a comparator to compare a reference voltage with a voltage source Vdd within an integrated circuit (IC), wherein the reference voltage can be generated by a bandgap voltage generator. Architecture and functions of the bandgap voltage generator are well known in the art, and therefore not explained in detail here.
According to the prior art, as the chip area required for the circuit thereof (for example, the comparator or the bandgap voltage generator) is large, the power consumption is correspondingly high. In addition, as semiconductor technologies progress rapidly, the internal circuit scale of ICs becomes smaller and smaller, and internal circuits and circuit configurations of various components are more complicated. Accordingly, semiconductor processes are forced to approach a tiny scale such as the order of nanometers. As a result, the voltage source Vdd required for the internal circuits becomes smaller and smaller accordingly. Regarding this, the start-up reset circuit of the prior art is not able to operate normally under a lower value of the voltage source Vdd.
As mentioned, the start-up reset circuit of the prior art is complicated and the chip area required is large. Furthermore, the power consumption is correspondingly high. Therefore, it is necessary to solve the above problems and other problems that will be faced when semiconductor processes are forced to approach the tiny scale mentioned above.
It is an objective of the claimed invention to provide start-up reset circuits and related methods, so as to correctly send a reset signal to all circuits that require start-up reset before normal operations.
It is another objective of the claimed invention to provide start-up reset circuits and related methods, so that chip areas and power consumption of circuits can be properly controlled under corresponding target values.
It is another objective of the claimed invention to provide start-up reset circuits and related methods, so as to meet requirements for circuits operating with low operation voltages.
According to embodiment(s) of the claimed invention, a start-up reset circuit is disclosed. The start-up reset circuit comprises: a clock signal generator, for generating a first clock signal and a second clock signal, wherein there is a phase difference between the first and the second clock signals, and a frequency of the first clock signal and a frequency of the second clock signal are substantially the same; and a flip-flop, for receiving an operation voltage and having a setup time, comprising an input terminal to receive the first clock signal, a clock input terminal to receive the second clock signal, and an output terminal to output a reset signal, wherein the setup time corresponds to the operation voltage.
According to embodiment(s) of the claimed invention, a start-up reset circuit is disclosed. The start-up reset circuit comprises: an oscillator, for generating a first clock signal and a second clock signal, wherein there is a phase difference between the first and the second clock signals; and a flip-flop, coupled to the oscillator. The flip-flop comprises: a first latch circuit for receiving the first and the second clock signals, wherein the first latch circuit samples the first clock signal by utilizing the second clock signal to output a sample signal; and a second latch circuit for receiving the sample signal and the second clock signal, wherein the second latch circuit samples the sample signal by utilizing the second clock signal to output a reset signal.
According to embodiment(s) of the claimed invention, a generation method for generating a start-up reset signal is disclosed. The generation method comprises: generating a first clock signal and a second clock signal, wherein there is a phase difference between the first and the second clock signals, and a frequency of the first clock signal and a frequency of the second clock signal are substantially the same; utilizing an input terminal of a flip-flop to receive the first clock signal, wherein the flip-flop has a setup time, and the setup time corresponds to an operation voltage received by the flip-flop; utilizing a clock input terminal of the flip-flop to receive the second clock signal; and utilizing an output terminal of the flip-flop to output a reset signal.
According to the above descriptions, no matter what kind of voltage is utilized by a circuit, the start-up reset operation(s) can be properly performed.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Generally speaking, a voltage source of a circuit can be coupled to a large capacitor for reducing the interference of noise. Therefore, during circuit start-up, the voltage of the voltage source gradually increases with a ramp waveform from 0 till the voltage is charged up to Vdd. If the voltage of the voltage source has not reached a threshold voltage Vth, the data output terminal Q is logic 1. If the voltage of the voltage source reaches the threshold voltage Vth, the data output terminal Q will be logic 0.
Here, an equation well known in the art is utilized as a supplementary explanation, so as to demonstrate why different values of the voltage source Vdd that drives the flip-flop 310 cause different values of the setup time, where the setup time corresponds to a charge/discharge time required for a latch within. The equation is listed as follows:
According to the above equation, the setup time is approximately inversely proportional to the voltage source Vdd of the circuit. That is, if the value of the voltage source Vdd is greater, the setup time is smaller.
In an embodiment, the clock enabling input terminal CK is implemented with negative phase driving, so a phase difference between two phases that are respectively coupled to the data input terminal D and the clock enabling input terminal CK is at least 180 degrees.
As shown in
According to the above descriptions, the present invention provides simpler circuits, which means the circuit scale is smaller and the power consumption is correspondingly lower. The present invention methods and circuits can be applied to the start-up reset function of digital circuits or analog circuits. In addition, by the phase difference adjustment of the two clock signals of the clock signal generator 320, the threshold voltage can be changed. Thus, the present invention can be applied to different voltage values of the voltage source Vdd (e.g. 0.9, 1.2, 1.5, 1.8, 2.5, 3.3 and 5.0 volts), so as to generate the reset signal required. In other words, even if a lower voltage value of the voltage source Vdd is given for driving the circuits, the present invention is still applicable. In another embodiment, by properly varying the present invention circuit(s), the clock enabling input terminal CK can be implemented with positive phase driving.
Those skilled in the art may derive some other detailed characteristics of the present invention method(s) according to the above disclosure related to the present invention circuits. Similar descriptions are not repeated in detail here.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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|US9130550 *||Jun 4, 2014||Sep 8, 2015||Samsung Electronics Co., Ltd.||Semiconductor device and method for operating the same|
|US9537470 *||Aug 12, 2015||Jan 3, 2017||Samsung Electronics Co., Ltd.||Semiconductor device and method for operating the same|
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|U.S. Classification||327/143, 327/198, 327/202, 327/218, 327/142|
|Dec 24, 2007||AS||Assignment|
Owner name: REALTEK SEMICONDUCTOR CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HONG, YUN-JAN;REEL/FRAME:020285/0941
Effective date: 20071217
|Sep 1, 2014||FPAY||Fee payment|
Year of fee payment: 4