|Publication number||US7948027 B1|
|Application number||US 12/635,662|
|Publication date||May 24, 2011|
|Priority date||Dec 10, 2009|
|Also published as||CN102097412A, CN102097412B, US20110140196|
|Publication number||12635662, 635662, US 7948027 B1, US 7948027B1, US-B1-7948027, US7948027 B1, US7948027B1|
|Inventors||Shing-Hwa Renn, Cheng-Chih Huang, Yung-Meng Huang|
|Original Assignee||Nanya Technology Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (1), Non-Patent Citations (2), Referenced by (5), Classifications (17), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to an embedded bit line structure, a field effect transistor (FET) structure with the same and a method of fabricating the same.
2. Description of the Prior Art
A vertical Fin-shaped gate field effect transistor (FinFET) with an embedded (or buried) bit line is the mainstream to achieve next generation 4F2 (feature) cell because of simplified middle-of-line (MOL) process. However, front-end-of-line (FEOL) process becomes more complicated accordingly. Especially, shallow trench isolation (STI) with half feature size is required. As a result, an aspect ratio of STI larger than 20 happens for thirties nm generation, and difficulty for gap fill with oxide film could be an obstacle to dynamic random access memory (DRAM) shrinkage.
Vertical surrounding gate transistors (SGT) with embedded bit lines have been proposed with enlarging isolation rule (close to 1F (feature)) to greatly reduce STI manufacturing difficulty. However, Vth (threshold voltage) stability for the memory cell array becomes much worse because of complicated fabricating process, including, for example, tedious embedded bit line formation steps, recess for spin-on-dielectric (SOD) formation steps, metal and n+ type poly defined transistor gate length. Reducing Vth variation with longer channel length is also unfeasible under vertical dimension constraint.
Therefore, there is still a need for a novel FinFET structure and the fabrication process therefore to avoid the aforesaid problems.
An objective of the present invention is to provide an embedded bit line structure, an FET structure with the same and a method of fabricating the same, in which aspect ratio of STI can be relatively reduced and Vth can be stable.
According to one embodiment of the present invention, an embedded bit line structure is provided, which includes a substrate including an active area, a trench surrounding the active area, and a bit line. The substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer. A bit line is disposed within the lower portion of the trench along one side of the active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.
According to another embodiment of the present invention, an FET structure with an embedded bit line, which includes a substrate including an active area, a trench, a bit line, and a word line. The FET structure includes a bit line structure similar to the aforesaid one. Additionally, an FET element is formed with the semiconductor layer of the active area. The bit line is disposed to electrically connect the FET. The word line is disposed within the substrate along another side of the active area, crosses over the bit line, and electrically connecting the FET.
According to further another embodiment of the present invention, a method of fabricating an embedded bit line structure is provided, which includes steps as follows. A substrate including an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer is provided. An active area on the substrate is provided. A trench surrounding the active area and down through the semiconductor layer and into the insulator layer is formed, A first portion of a bit line is formed within the trench at one side of the active area, wherein the first portion of the bit line is below the original top surface of the insulator layer. An insulator liner is formed on a sidewall of the trench opposite the active area above the first portion of the bit line for isolating the bit line from the semiconductor layer of the substrate. A second portion of the bit line is formed on the first portion of the bit line within the trench to electrically connect the bit line to the semiconductor layer of the active area. The trench is filled with insulator material to form an STI.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
An FET structure with an embedded bit line is provided in the present invention. The FET structure includes an embedded bit line structure according to the present invention, and both are described in detail, referring to
A word line 26 is disposed within the substrate 10, along another side of the active area, crossing over the bit line 22, and electrically connecting the gate (not shown) of FET.
As shown in
According to further another embodiment of the present invention, a method of fabricating an embedded bit line structure is provided. One embodiment of the method is illustrated by a flow chart of
Thereafter, in the step 109, an insulator liner 28 is formed on a sidewall of the trench 11 opposite the active area above the first portion 18 of the bit line for isolating the bit line from the semiconductor layer 16 of the substrate. The formation of the insulator liner 28 may be carried out by forming an insulator liner on all of the sidewalls of the trench using for example a deposition process, followed by stripping off the insulator liner on the sidewall of the active area above the first portion 18 of the bit line using for example an etching process in which the desired portion is protected by a mask. In the step 111, a second portion 20 of the bit line is formed on the first portion 18 of the bit line within the trench 11 to electrically connect the bit line 22 to the semiconductor layer 16 of the active area. The second portion 20 may include polysilicon and may be formed by a chemical vapor deposition process. In the step 113, the trench is filled with insulator material, such as oxide material, by for example a chemical vapor deposition or spin-on-dielectric process to form an STI 24.
Also referring to
A conventional fin gate structure can be suitably formed based on the bit line structure of the present invention. The gate structure may comprise a fin gate structure, such as a double gate FinFET structure. Another word line may be further disposed, such that two word lines electrically connect two opposite sides of the fin gate structure respectively. Alternatively, referring to
The thickness of the semiconductor layer, such as silicon film, of the substrate depends on the resulting device desired and decided by vertical transistor geometric sizes including sizes of junction out-diffusion, channel length, STI format capability, and the like. As the semiconductor layer is disposed on the insulator layer, the bit line having a structure according to the present invention can be well insulated within the insulator layer and the STI, the thickness of the semiconductor layer can be significantly reduced as compared with conventional one.
Since the lower portion of the embedded bit line is formed within an insulator layer, parasitic capacitance is reduced. Since the FET is constructed on an insulator layer, the STI can be relatively shallow; and thus the fabrication is relatively easy. With easy STI fill process with embedded bit lines, longer channel is possible even for feature size of 40 nm or less, resulting in a stable array Vth. Furthermore, with embedded metal bit line structure, no metal contamination is risked.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US7518182 *||Jul 20, 2004||Apr 14, 2009||Micron Technology, Inc.||DRAM layout with vertical FETs and method of formation|
|1||Kazumi Inoh, et al., "FBC (Floating Body Cell) for Embedded DRAM on SOI", 2003 Symposium on VLSI Technology Digest of Technical Papers, 2003.|
|2||Tomoaki Shino, et al., "Highly Scalable FBC (Floating Body Cell) with 25nm Box Structure for Embedded DRAM Applications", 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 132-133, IEEE.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8659079 *||May 29, 2012||Feb 25, 2014||Nanya Technology Corporation||Transistor device and method for manufacturing the same|
|US9287271 *||Apr 29, 2015||Mar 15, 2016||Micron Technology, Inc.||Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices|
|US9401363 *||Aug 23, 2011||Jul 26, 2016||Micron Technology, Inc.||Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices|
|US20130049110 *||Aug 23, 2011||Feb 28, 2013||Kuo Chen Wang||Vertical Transistor Devices, Memory Arrays, And Methods Of Forming Vertical Transistor Devices|
|US20150236023 *||Apr 29, 2015||Aug 20, 2015||Micron Technology, Inc.||Vertical Transistor Devices, Memory Arrays, And Methods Of Forming Vertical Transistor Devices|
|U.S. Classification||257/329, 257/E27.112, 438/212, 257/347, 257/349, 257/E29.262|
|Cooperative Classification||H01L27/10885, H01L27/1203, H01L27/10826, H01L27/10879, H01L21/84|
|European Classification||H01L27/12B, H01L21/84, H01L27/108M4D2, H01L27/108F7, H01L27/108M4C4|
|Dec 10, 2009||AS||Assignment|
Owner name: NANYA TECHNOLOGY CORP., TAIWAN
Effective date: 20091209
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RENN, SHING-HWA;HUANG, CHENG-CHIH;HUANG, YUNG-MENG;REEL/FRAME:023637/0640
|Nov 24, 2014||FPAY||Fee payment|
Year of fee payment: 4