|Publication number||US7952376 B1|
|Application number||US 12/231,024|
|Publication date||May 31, 2011|
|Filing date||Aug 28, 2008|
|Priority date||Aug 28, 2008|
|Publication number||12231024, 231024, US 7952376 B1, US 7952376B1, US-B1-7952376, US7952376 B1, US7952376B1|
|Inventors||Zunhang Yu Kasnavi, Chung Fu, Ramraj Gottiparthy|
|Original Assignee||Altera Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Non-Patent Citations (2), Referenced by (4), Classifications (6), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Data transceiver functionality is increasingly incorporated into integrated circuit (IC) designs. To effect better performance, the receiver sections of such transceivers often include equalization circuitry. Such equalization circuitry, however, often employs analog circuit components that pose testing challenges for the manufacturer. Frequently, high cost, sophisticated, precision testers are needed to adequately test on-chip equalizer functionality. Even with high end testers, producing accurate test results takes a substantial amount of test time. Accordingly, manufacturers would welcome faster and lower cost options for testing IC's with on-chip equalization and products that include them.
Novel apparatus and methods are disclosed yielding improved testing and testability of equalization circuitry. In one aspect of the invention a loopback circuit provides a test signal to a receiver having an equalization function. The loopback circuit is equipped with a signal conditioner which can be used during testing to provide a test signal mimicking characteristics of imperfect, real world signals.
In another aspect of the invention a device having a loopback circuit with such a signal conditioner is tested for performance characteristics of its equalizer circuitry. Multiple measurements of a device are made using different selectable modes of signal conditioner operation. The measurements are then comparatively assessed to ascertain the performance of the equalizer.
In yet another aspect of the invention access is made at certain points within portions of the control circuitry of an adaptive equalizer circuit, including to a digital output representing an analog signal comparison. An external analog signal is applied to the control circuitry with the digital output signaling the result for testing analog circuit operation.
These and other aspects of the invention will be appreciated by one of skill in the art by the drawings and detailed description that follows.
Transceiver 100 includes transmitter and receiver sections, and an internal loopback section. The various sections of transceiver 100 are preferably located close together on a single silicon die. In one embodiment the silicon die is that of a programmable logic device (PLD), such as an FPGA, and transceiver 100 can be variously and programmably coupled to routing, logic, I/O, and other functional circuitry of the PLD. One of skill in the art will appreciate that inventive aspects are not limited to a PLD implementation but that many other embodiments are possible including, for example, other integrated circuit types such as ASICs.
The transmitter section 110 of transceiver 100 includes transmit logic circuit 112 which further has a pseudo random binary sequence (PRBS) generator circuit 114. PRBS generator circuit 114 is used in the production of test data during a testing operation.
The receiver section includes receiver input section 170, general receiver circuitry section 130, and equalization (EQ) circuitry (here, adaptive equalization circuitry) having analog section 140, digital section 160, and selective coupling section 150. Receiver input section 170 includes input buffer 172 and adjustable filter 174. Input buffer 172 is adapted to receive a data signal from external sources, for example, through connector pins exposed on the IC package. A buffered data signal from buffer 172 is coupled to the input side of adjustable filter 174. Adjustable filter 174 performs at least an equalization operation on its input signal to produce a data signal at its output. Control input 175 of adjustable filter 174 illustrates that the operation of filter 174 is dynamically adjustable and, in particular, that its equalization function is adjustable. The data signal from adjustable filter 174 of receiver input section 170 is conveyed to general receiver circuitry section 130 and to analog section 140 of the EQ circuitry. Receiver logic 132 of general receiver circuitry section 130 includes PRBS generator 134 which may be used during testing using known methods to generate data for comparison with the received data signal in making a determination of the accuracy of the received data.
In the analog section 140 of the EQ circuitry, the data signal from adjustable filter 174 is coupled to two signal paths, one reference and one ideal. Each of the reference and ideal signal paths includes extraction circuitry to exact information about a data signal. Edge rate and amplitude extraction circuits 144 and 146 in
The output of comparator 148 is coupled to circuitry adapted to convey an output signal to additional circuitry, devices, or equipment to conduct testing operations, in a preferred embodiment. Such a test signal access point is indicated by circuit block 156 including one or more passive or active electronic components or conductors. In one embodiment test signal access circuitry 156 has a highly conductive metal path to a connection pin exposed on an IC package. In another embodiment where analog section 140 is to be incorporated into an FPGA device having programmable digital signal routing resources, test signal access circuitry 156 includes a programmable switch to selectively couple the signal to digital routing resources on the chip.
The digital section 160 of the EQ circuit provides the signal that will drive the control input 175 of adjustable filter 174 to effect the adaptive aspect of adaptive equalization. Digital section 160 includes digital logic circuitry 162 with its output coupled to digital-to-analog converter 164. In one simple and space-efficient embodiment, digital logic circuitry 162 includes a binary up/down counter having a control input for a signal determining the direction of counting in a given cycle. The output of digital-to-analog converter 164 couples to drive the filter adjustment input 175. The output of digital-to- analog converter 164 further couples to test signal access point 167, implemented after the fashion of access point circuitry 145 and 147. The signal available via access point 167 is useful for testing the existence and degree of convergence achieved by the equalization system circuitry and for testing the functionality of digital section 160, itself.
The selective coupling section 150 of the EQ circuit serves to provide a selected input signal to digital section 160 of the EQ circuit. For one embodiment, the selective coupling section 150 provides the up/down direction control signal to a binary counter of digital logic 162. During normal (i.e., non-test) circuit operation, mode selection circuitry 154 signals test mode multiplexer 152 to couple the comparator 148 output of the analog section 140 to the input of digital section 160. Accordingly, in the described embodiment the 1-bit result of the comparison of the reference and ideal information signals by the comparator 148 controls the direction of counting by digital logic 162 and in turn the change to the signal applied at control input 175 of adjustable filter 174. During circuit testing operation, mode selection circuitry 154 signals test mode multiplexer 152 to couple a signal from test input circuitry 155 to the input of digital section 160. Accordingly, in the described embodiment a 1-bit signal from test input circuitry 155 controls the direction of counting by digital logic 162 and in turn the change to the signal applied at control input 175 on adjustable filter 174 to effect adaptation of the equalization function. Test input circuitry 155 may include, for example, a 1-bit memory element. In an alternative embodiment where selective coupling section 150 is to be incorporated into an FPGA device having programmable routing, logic, and I/O circuitry, test input circuitry 155 uses a programmable switch to selectively couple its respective output signal to FPGA digital signal routing resources.
Similar implementation alternatives exist for mode selection circuitry 154 as appreciated by one of ordinary skill in the art. Examples include a 1-bit memory element such as a register, latch, or SRAM cell circuit.
Inclusion in a device of circuitry illustrated within selective coupling section 150 advantageously improves testability (1) by permitting a break in the loop (from the adjustable filter 174 output to its adjustment input 175) that is effective during normal adaptive equalizer, to isolate sections of circuitry for testing, and (2) by permitting the use of comparator 148 in voltage measurement operations.
The transmitter section 110 is coupled to the receiver section by internal loopback circuit 120. During testing, the PRBS generator 114 and transmit logic 112 generates a test data signal that is applied to the input side of internal loopback circuit 120. The two lines shown connecting transmit logic circuitry 112 with internal loopback circuit 120 in
Internal loopback circuit 120 includes slew rate control (SRC) circuit 122. The slew rate control circuit of the preferred embodiment serves as a circuit element to condition, and in particular to distort, a data signal during testing of equalization in a receiver. Slew rate control circuit 122 acts to limit the signal slew rate in the preferred embodiment. Limiting the slew rate achieves the effect of a low pass filter attenuating the amplitude of higher frequency components in the data signal. Such attenuation preferably mimics signal distortion occurring on transmission lines that might normally be expected to carry a data signal to receiver input buffer 172 such as a twisted wire pair. Different and additional signal distortion operations can be included in the internal loopback signal pathway in other embodiments. Signal distortion circuitry can affect signal parameters other than amplitude, and as may be addressed by equalization adaptation functions and, similarly, transmission line distortion characteristics.
Control signal source circuitry 124 couples to an input of slew rate control circuitry 122 to apply a signal that varies slew rate control circuit operation. In one embodiment, slew rate control circuitry 122 accepts a binary control signal that enables or disables slew rate control conditioning on the data signal. In another embodiment, slew rate control circuitry 122 accepts a multi-bit binary control signal that disables or, alternatively, enables a stepped level of slew rate control on the data signal (e.g., low, medium, or high slew rate limiting). It is apparent to one of skill in the art that many alternatives are possible. Alternatives for control signal source circuitry 124 are similarly variable and embodiments may appropriately include physical implementations such as those previously discussed in relation to circuit blocks 156, 154, and 155.
Inclusion of the distortion element, here, the slew rate control circuit, in the internal loopback circuit of an IC transceiver improves the testability of the IC. Advantageously, dependence on a high-function external test data signal source is eliminated along with associated time requirements.
The initial testing phase of
The processing of block 210 also involves test equipment connected to the IC which, in this described preferred embodiment, advantageously includes a low-cost structural tester having, for example, binary data and DC signal capabilities. Prior to inventive aspects disclosed herein, block testing such as this utilized a high-end test device typically having functional generation and observation, DC signal, pin timing, and high signal integrity capabilities, and the associated high cost. In block 210, the IC under test is connected to external test equipment by insertion into an IC socket. The external test equipment is configured to test the reference leg of analog circuit block 140 by coupling a controllable voltage source to the pin associated with access point 147, and by coupling monitor circuitry for the digital signal value exposed via access point 156.
Processing of block 212 of
After the introduction of the conditioned data signal to the receiver circuitry, and after isolation of the EQ analog section from the digital section using the selective coupling circuitry, a sweep voltage supplied by the controllable voltage source is applied at access point 147 and the output signal of comparator 148 is monitored via access point 156. In the preferred embodiment, the controllable voltage source applies a linear sweep signal but other sweep signals that supply a range of voltage levels over time can also be used, including, for example, nonlinear continuous sweep signals and stepped sweep signals. While the sweep signal is applied to the unit under test, a change in the comparator output value signals to the test equipment the intersection of the sweep voltage with the reference voltage. The voltage of the sweep signal at the intersection point is collected as a data sample at block 218. Note that to instead target the ideal leg of analog circuit block 140 with the test procedure, the sweep voltage source coupling is moved from access point 147 to access point 145, and the sweep voltage applied there. The comparator output is identically monitored and the voltage determination made. It can be seen that the analog processing of voltage determination is advantageously performed locally by the comparator rather than by the external circuitry of test equipment. As illustrated and described, one low-speed, noise immune, digital signal is communicated off the chip to signal the voltage measurement which offers many advantages.
The test procedure described above in relation to
The standard production quality unit testing phase of
The initial testing phase of
After isolation of the EQ analog section from the digital section using the selective coupling circuitry and the application of the test signal to the digital logic circuitry, a sweep voltage supplied by the controllable voltage source is applied at access point 147 and the output signal of comparator 148 is monitored via access point 156. In the preferred embodiment, the controllable voltage source applies a linear sweep signal but other sweep signals that supply a range of voltage levels over time can also be used as already discussed. While the sweep signal is applied to the unit under test, a change in the comparator output value signals to the test equipment the intersection of the sweep voltage with the output of digital-to-analog circuit 164. The voltage of the sweep signal at the intersection point is collected as a data sample at block 318. It can be seen that the analog processing of voltage determination is again advantageously performed locally by the comparator rather than by the external circuitry of test equipment.
The test procedure described above in relation to
The standard production quality unit testing phase of
From the above examples, one can appreciate how a comparator circuit with enhanced connectivity can advantageously provide improved device testing capability.
The method depicted in
The method depicted in
The method depicted in
Processing of block 440 compares the third maximum frequency determination with the first. Similarly, processing of block 450 compares the third maximum frequency determination with the second. At block 460 a determination is made whether the adaptive equalization system of the circuit under test passes or fails criteria established for the quality of circuit operation. In one embodiment, greater proximity of the third maximum frequency to the first maximum frequency is a greater indicator of success. In one embodiment, the greater the third maximum frequency exceeds the second maximum frequency, the greater the indicator of success. Embodiments using other measures and/or other comparisons are possible. For example, another embodiment may use both the proximity of the third maximum frequency to the first, and, the significant degree that the second maximum frequency is below the first, to establish success.
In one preferred embodiment, the circuit under test is incorporated into an FPGA IC product and processing for adaptive equalization system testing, as that depicted in
The above description of illustrative embodiments includes many implementation details in order to clearly explain and develop an understanding of the inventive subject matter. The reader will appreciate that use of the inventive subject matter can occur without use of the embodiments and implementation details disclosed above. The above description of illustrative embodiments also includes discussion of many alternative implementation examples. The reader will appreciate that alternative means for using inventive subject matter are not limited to the examples discussed but that many other alternatives can be employed. For example, as an alternative to routing resources or memory elements (such as configuration RAM bits) for implementation of the circuitry in an FPGA as discussed above, JTAG or test I/O resources may be used to implement the circuitry in an ASIC. These and other departures from the specific details shown and described herein will be appreciated by one of ordinary skill in the art.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8531196 *||Feb 3, 2009||Sep 10, 2013||Altera Corporation||Delay test circuitry|
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|U.S. Classification||324/762.01, 324/750.01|
|Cooperative Classification||G01R31/318516, G01R31/31715|
|Nov 5, 2008||AS||Assignment|
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YU KASNAVI, ZUNHANG;FU, CHUNG;GOTTIPARTHY, RAMRAJ;REEL/FRAME:021790/0891
Effective date: 20081031
Owner name: ALTERA CORPORATION, CALIFORNIA
|Oct 28, 2014||FPAY||Fee payment|
Year of fee payment: 4