|Publication number||US7975205 B2|
|Application number||US 11/627,519|
|Publication date||Jul 5, 2011|
|Filing date||Jan 26, 2007|
|Priority date||Jan 26, 2007|
|Also published as||US20080184093|
|Publication number||11627519, 627519, US 7975205 B2, US 7975205B2, US-B2-7975205, US7975205 B2, US7975205B2|
|Inventors||Larry J. Thayer|
|Original Assignee||Hewlett-Packard Development Company, L.P.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Referenced by (7), Classifications (5), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Common to nearly all computing system platforms is the need for substantial amounts of reliable random-access digital memory. Such memory is often employed to contain software, such as operating system and application software, as well as data utilized by these programs. Further, capacity, speed, and reliability requirements for memory for these platforms continue to become more stringent. In addition, a memory controller is often included as part of the memory system to facilitate computer system access to large memory.
In many systems, such as high-performance desktop computing platforms and network servers, memory requirements have been satisfied primarily by one or more dual in-line memory modules (DIMMs), each of which is populated with several dynamic random-access memory (DRAM) devices. Typically, each DIMM provides one or two “ranks,” or portions of the address range of the memory. Each rank includes a number of DRAMs, with each DRAM providing a predetermined number of bits of each addressable word of the rank. Unfortunately, the increase in capacity delivered by DIMMs has been accompanied with a concomitant increase in the occurrence of data errors, necessitating the use of error correction schemes or algorithms to detect and correct the errors. To facilitate these schemes, each DIMM often provides one or more additional DRAMs beyond what the associated computing system requires for its data requirements to allow the attendant memory controller to store error correction data along with the user data in the DIMM.
Current error correction algorithms are often able to correct data associated with one or more entire DRAMs. In this case, for each word in a rank, the error correction scheme would have the capacity to correct at least all bits of a single DRAM for each word of the rank. Such capability is advantageous since “hard,” or permanent, failures often affect a significant portion of a single DRAM. To this end, the memory controller often implements an error correction algorithm that is optimized for the particular DRAM bit-width being employed in the memory system. For example, DIMMs are often designed to use DRAMs providing thousands of memory locations, with each location providing a bit-width of either four or eight. Presuming an error correction algorithm optimized to correct any DRAM of a system employing eight-bit DRAMs, use of the same error correction algorithm in a memory system using four-bit DRAMs likely would not allow replacement of any two of the DRAMs, unlike an error correction algorithm specifically optimized for four-bit DRAMs. Thus, memory systems are typically designed to align the error correction algorithm employed in the memory controller with the particular DRAM devices utilized in the DIMMs to maximize memory system reliability.
However, correlating the error correction algorithm with the type of DRAM employed produces some limitations. For example, a computing system may be designed to accept two or more types of DIMMs differentiated by DRAM bit-widths. Such a system design may be beneficial over the life of the system, as one type of DIMM may be more desirable over another in terms of pricing and availability at various points in time. Thus, as replacements for failed DIMMs in the system are required, the types of DIMMs employed in any one system may change over time. The same holds true during production of a computing product, as the purchase of one DIMM type may be more attractive than another due to prevailing market conditions. In either case, the option of employing one DIMM type over another would not be available if the memory controller is designed and optimized for DIMMs of a specific DRAM bit-width.
Another embodiment, a memory controller 202 employed within a memory system 200, is illustrated in
Another embodiment of the invention—a memory controller 302 within a memory system 300—is depicted in the block diagram of
Each rank 312, in turn, includes either a first number P of four-bit-wide (×4) DRAM memory devices 314 or a second number R of eight-bit-wide (×8) DRAM memory devices 316. In the specific example of
Other organizations of the memory 310 may be employed in other embodiments. For example, all ranks 312 may contain either all ×4 DRAMs, all ×8 DRAMs, or DRAMs of other bit-widths. In another implementation, each rank 312 may span two or more DIMMs coupled in parallel, thus allowing more error correction data to be present in each addressable location of the memory 310, thereby strengthening the capability of the particular error correction algorithm employed for that rank 312. Other memory technologies, such as SRAMs, may be employed in the alternative. Also, single in-line memory modules (SIMMs) may replace the DIMMs of
Each DIMM of
Similar to the memory controller 202 of
The memory controller 302 also includes a table 308 containing multiple entries 309. In one embodiment, each entry 309 is associated with a rank 312 of the memory 310, wherein each entry 309 includes an indication of the bit-width of the DRAMs used in that rank 312. In another implementation, each entry 309 is associated with an address range of the memory 310, and includes an indication of the bit-width of the DRAMs used in that particular range.
The memory controller 302 and the memory 310 of
The control logic 304 then processes the information regarding the organization of the memory 313 to construct the entries 309 of the table 308 (operation 404). In the embodiment of
After the control logic 304 constructs the table 308, the memory controller 302, by way of the error correction logic 306, employs the memory interface 320 to perform read and write operations on the memory 310. Ordinarily, the memory controller 302 performs these operations in response to a request for access received from a processor (not shown in
In response to an internal request (i.e., a request originating from inside the memory controller 302) or an external request (i.e., a request originating from outside the memory controller 302) to access the memory 313 (operation 406), the error correction logic 306 consults the table entry 309 associated with the rank 312 being accessed to determine the bit-width of the DRAMs 314 of that rank 312 (operation 408). The error correction logic then selects the particular error correction algorithm associated with that bit-width (operation 410). In one embodiment, the each of the error correction algorithms may be a Reed-Solomon error correction algorithm. In other implementations, each of the error correction algorithms may be an algorithm other than a Reed-Solomon error correction algorithm. Also, a mixture of Reed-Solomon algorithms and others may be employed within the error correction logic 306.
Thereafter, in the case of a write operation (operation 412), the error correction logic 306 uses the selected error correction algorithm to generate the appropriate error correction data for the user data to be written to the accessed rank 312 (operation 414). The user data and the error correction data are then both written to the accessed rank 312 by way of the memory interface 320 (operation 416). For example, if the accessed rank 312 contains eighteen ×4 DRAMs 314, the memory controller 302, in conjunction with the error correction logic 306, may write the user data for each accessed data word to sixteen of the ×4 DRAMs 314, and write the associated error correction data to the remaining two ×4 DRAMs 314. If, instead, the accessed rank 312 utilizes nine ×8 DRAMs 316, the memory controller 302 writes the user data for each accessed data word to eight of the ×8 DRAMs 316, and writes the corresponding error correction data to the remaining ×8 DRAM 316.
If the requested access to the memory 310 is a read operation (operation 412), the memory controller 302 retrieves one or more data words from the accessed rank 312 by way of the memory interface 320 (operation 418). In one embodiment, each of the data words contains user data and error correction data. The error correction logic 306 then detects and corrects errors in the data words by processing the user data and the error correction data with the selected error correction algorithm associated with the accessed rank 312, as discussed above (operation 420).
After each read or write operation, the memory controller 302 is configured to respond to each subsequent memory access as before, wherein the control logic 304 utilizes the entry 309 of the table 308 corresponding to the rank 312 being accessed to determine which error correction algorithm to employ for that particular memory access.
In one embodiment, the memory controller 302 may adapt to changes in the organization of the memory 310 while the memory system 300 remains in an operational state. For example, the memory system 300 may be configured as a “hotplug” system, in which a defective DIMM may be removed from, or replaced in, the memory 310, or a new DIMM may be added to the memory 310, while the memory system 300 continues to operate. In such an embodiment, the memory controller 302 is configured to detect if one of the DIMMs of the memory 310 has been removed, replaced or added (operation 422). If so, the control logic 304 once again reads the configuration information from each of the DIMMs regarding the organization of the memory 310 associated with each of the ranks 312 by way of the configuration interface 330 (operation 402), and processes the information to construct the entries 309 of the table 308 (operation 404).
In another embodiment, the organization of the memory 310 may not be detected electronically, such as by way of the configuration interface 330 and the SPD standard discussed above, so that the entries 309 of the table 308 are written appropriately. In that case, a computer operator may be cognizant of the organization of the memory 310, including the types of DRAMs 314, 316 employed. As a result, the operator may directly or indirectly enter the necessary information into the entries 309 of the table 308 describing the organization of the memory 310, such as by way of keyboard entry through an operator panel or other means. Such an alternative may eliminate the need for the configuration interface 330 and associated logic, thus simplifying the design of the memory system 300.
As described above, various embodiments of the present invention allow a single memory controller to provide any of a number of possible error correction algorithms, and to select the most appropriate of those algorithms for the particular memory organization involved. Therefore, the same memory controller may be employed in a number of different computing systems, each of which incorporates a different type of DIMM or other memory configuration, thus maintaining a high level of memory reliability while providing flexibility in the types of DIMMs employed. In some implementations, the memory controller may select the correct error correction algorithm on a per-rank basis for memory systems that employ diverse types of DIMM organizations simultaneously. In addition, some embodiments are capable of adjusting the type of algorithm involved long after initial power-up to benefit systems in which one or more DIMMs may be removed, replaced, or added while the host computing system continues to operate.
While several embodiments of the invention have been discussed herein, other embodiments encompassed by the scope of the invention are possible. For example, while some embodiments of the invention are described above in specific reference to memory systems employing DIMMs carrying ×4 and ×8 DRAMs, memory systems employing other memory device types and configurations may benefit from other embodiments of the invention. Further, while only a single memory level is discussed with particularity in the foregoing embodiments, other embodiments may be devised which facilitate multiple memory levels, such as those incorporating one or more levels of memory cache. Also, aspects of one embodiment may be combined with those of alternative embodiments to create further implementations of the present invention. Thus, while the present invention has been described in the context of specific embodiments, such descriptions are provided for illustration and not limitation. Accordingly, the proper scope of the present invention is delimited only by the following claims.
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|Cooperative Classification||G06F11/1044, G11C2029/0411|
|Jan 30, 2007||AS||Assignment|
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:THAYER, LARRY J.;REEL/FRAME:018834/0175
Effective date: 20070123
|Dec 24, 2014||FPAY||Fee payment|
Year of fee payment: 4
|Nov 9, 2015||AS||Assignment|
Owner name: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;REEL/FRAME:037079/0001
Effective date: 20151027