Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS7977705 B2
Publication typeGrant
Application numberUS 12/470,152
Publication dateJul 12, 2011
Filing dateMay 21, 2009
Priority dateJun 30, 2008
Also published asCN102017075A, CN102017075B, DE112009001477B4, DE112009001477T5, US20090321873, WO2010002515A2, WO2010002515A3
Publication number12470152, 470152, US 7977705 B2, US 7977705B2, US-B2-7977705, US7977705 B2, US7977705B2
InventorsBich-Yen Nguyen, Carlos Mazure
Original AssigneeS.O.I.Tec Silicon On Insulator Technologies
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Low-cost substrates having high-resistivity properties and methods for their manufacture
US 7977705 B2
Abstract
In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.
Images(6)
Previous page
Next page
Claims(20)
1. A method of manufacturing a substrate having high-resistivity (HR) properties for devices fabricated therein, the method comprising:
providing a support having a first resistivity of standard resistivity;
providing an HR semiconductor layer on the support, the HR layer having a thickness between 20 nm and 5000 nm and a resistivity that is greater than the first resistivity of the support;
providing an insulating layer having a thickness between 10 nm and 200 nm on the HR semiconductor layer or at the surface of a donor substrate;
assembling the support with the donor substrate; and
reducing the thickness of the donor substrate portion.
2. The method of claim 1 wherein the first resistivity is between 8 Ohm-cm and 30 Ohm-cm , and wherein the resistivity of the HR semiconductor layer is greater than 103 to 104 Ohm-cm.
3. The method of claim 1 wherein providing the HR semiconductor layer further comprises depositing an undoped silicon layer.
4. The method of claim 1 further comprising implanting nitrogen ions into the HR semiconductor layer.
5. The method of claim 1 wherein providing the insulating layer further comprises one or more of depositing the insulating layer and oxidizing the HR semiconductor layer or the surface of the donor substrate.
6. The method of claim 1 wherein the insulating layer is provided at the surface of the donor substrate; and wherein the step of assembly further comprises bringing into contact the support with the insulating layer at the surface of the donor substrate.
7. The method of claim 1 further comprising providing a diffusion barrier layer having a thickness greater than 20 nm on the support before the step of providing the HR semiconductor layer.
8. The method of claim 1 further comprising fabricating one or more electronic devices in the top semiconductor layer, the fabricated devices having HR properties comprising one or more of reduced signal loss and improved signal to noise ratio when operated at frequencies greater than 0.1 GHz.
9. A substrate having high-resistivity (HR) properties for devices fabricated therein, the substrate comprising:
a support having a first resistivity of standard resistivity;
a HR semiconductor layer arranged on the support, the layer having a resistivity that is greater than the first resistivity of the support;
an insulating layer arranged on the HR semiconductor layer; and
a top semiconductor layer arranged on the insulating layer and suitable for device fabrication.
10. The substrate of claim 9 wherein the first resistivity is between 8 Ohm-cm and 30 Ohm-cm, and wherein the resistivity of the HR semiconductor layer is greater than 103 to 104 Ohm-cm.
11. The substrate of claim 9 wherein the support comprises one or more of quartz, mono-crystalline silicon, poly-crystalline silicon, poly-crystalline silicon carbide, or poly-crystalline aluminium nitride.
12. The substrate of claim 9 wherein the HR semiconductor layer comprises one or more of undoped amorphous silicon or undoped poly-crystalline silicon.
13. The substrate of claim 9 wherein the HR semiconductor layer further comprises nitrogen species at a concentration of between 1013 and 1015/cm3.
14. The substrate of claim 9 wherein the thickness of the HR semiconductor layer is between 20 nm and 5000 nm.
15. The substrate of claim 9 further comprising a diffusion barrier layer having a thickness greater than 20 nm arranged between the support and the HR semiconductor layer.
16. The substrate of claim 9 wherein the insulating layer has a thickness between 10 nm and 200 nm and comprises one or more of silicon dioxide, silicon nitride, a high k dielectric material, a low k dielectric material, or silicon oxide.
17. The substrate of claim 9 wherein the top layer comprises mono-crystalline silicon.
18. The substrate of claim 9 further comprising one or more electronic devices fabricated in the top semiconductor layer.
19. The substrate of claim 9 wherein the HR properties comprises one or more of reduced signal loss and improved signal to noise ratio when devices fabricated therein operate at frequencies greater than 0.1 GHz.
20. A substrate having high-resistivity (HR) properties for devices fabricated therein, the substrate comprising:
a support having a first resistivity of standard resistivity;
a HR semiconductor layer arranged on the support, the layer having a resistivity that is greater than the first resistivity of the support;
a diffusion barrier layer comprising one or more layers comprising silicon dioxide, nitride rich silicon nitride, and silicon nitride arranged between the support and the HR semiconductor layer;
an insulating layer arranged on the HR semiconductor layer; and
a top semiconductor layer arranged on the insulating layer and suitable for device fabrication.
Description

This application claims the benefit of application No. 61/093,887 filed Sep. 3, 2008, the entire content of which is expressly incorporated herein by reference thereto.

BACKGROUND OF THE INVENTION

The present invention relates to substrates structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate, and to methods of manufacturing such substrates.

BACKGROUND OF THE INVENTION

Examples of known substrates with high electrical resistivity “HR” substrates are disclosed in documents US 2006/0166451 and US 2007/0032040. Such known substrates generally comprise a top layer in which or on which high frequency devices will be formed, an insulating layer below the top layer and a high-resistivity support. In some instances, additional layers could be inserted between the insulating layer and the support to further improve the high electrical resistivity properties of the substrate.

Although known HR substrates are suitable for devices with improved performance because they provide reduced signal loss in the support or improved signal to noise ratio due to reduced crosstalk, they suffer from a major drawback: their cost can be high. This is partly due to the fact that known HR substrates incorporate high-resistivity supports that are priced at an elevated cost compared to traditional, non HR, supports. High cost is a particular concern when substrates will be used for fabrication of devices to be integrated into price sensitive products, such as consumer products telecom markets

The higher cost of HR supports often arises because their manufacture requires additional steps. In case of mono-crystalline silicon, such additional steps often involve multi-step and lengthy annealing to precipitate residual oxygen present in the support. Such additional steps can also include, e.g., forming an additional layer in-between the insulating layer and the support, or removing a surface layer of the support to further increase or preserve the high-resistivity of the substrate, or so forth.

SUMMARY OF THE INVENTION

The present invention provides high-resistivity “HR” substrates—that is substrates structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate—that are simpler to manufacture and of lower cost than known HR substrates. HR substrates of this invention have applications in microelectronics, optoelectronics, photovoltaics, micro-electro mechanical devices, and particularly in devices that operate at high frequency typically over 100 Mhz, such as radio frequency devices that can be found in telecommunication or radio detection applications.

In general, the invention replaces known, higher-cost HR substrates with lower-cost, HR substrates comprising a top layer and a support. Instead of relying on high-resistivity of the support to provide high-resistivity of the final substrate, the invention provides high-resistivity of the final substrate by means of a support with a surface layer of a lower-cost, high-resistivity semiconductor material. Accordingly, the support can have standard resistivity, and optionally lower quality, and thus can be of lower cost. The invention also provides low-cost methods for manufacturing HR substrates.

In more detail, the invention provides substrates having high-resistivity properties that include a support having a standard resistivity, a high-resistivity semiconductor layer on the support substrate, an insulating layer on the high-resistivity layer, and a top layer on the insulating layer. The high-resistivity semiconductor layer can have a resistivity greater than 1000 Ohm/cm. Optionally, the provided substrates further include a diffusion barrier layer arranged between the support and the semiconductor layer.

The invention also provides methods for manufacturing a substrate having high-resistivity properties. The methods include providing a support presenting a standard resistivity, forming a high-resistivity semiconductor layer on the support substrate to form a first intermediate structure, providing an insulating layer on the first intermediate structure, assembling the intermediate structure with a donor substrate to form a second intermediate structure, and finally reducing the thickness of the donor substrate of the second intermediate structure to form the substrate. Optionally, methods of the invention further include providing a diffusion barrier layer on the support before the step of forming the high-resistivity semiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the invention will become apparent from the following descriptions that refer to the appended drawings, which illustrate exemplary but non-limiting embodiments of the invention, and in which:

FIG. 1 illustrates an embodiment of the substrates of the invention;

FIG. 2 illustrates another embodiment of the substrates of the invention;

FIGS. 3 a to 3 e illustrates an embodiment of methods for manufacturing substrates; and

FIG. 4 a to 4 f illustrates another embodiment of methods for manufacturing substrates.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The preferred embodiments and particular examples described herein should be seen as examples of the scope of the invention, but not as limiting the present invention. The scope of the present invention should be determined with reference to the claims.

FIG. 1 illustrates embodiments according to the invention of substrates 1 structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. These substrates of the invention are also more simply referred to herein as “HR substrates”. The substrate 1 can have a diameter depending on its final application of, e.g., 300 mm, 200 mm, or other diameters.

Substrate 1 comprises top layer 5, in which or on which devices are ultimately formed. In some cases, devices, e.g., known CMOS devices, can be formed according to known techniques directly on and in top layer 5. In other cases, e.g., gallium nitride HEMT devices, further layers (not illustrated in FIG. 1) are provided on top layer 5. The top layer can comprise various materials chosen according to device application, e.g., mono-crystalline silicon, silicon carbide, gallium nitride, and the like. The thickness of the top layer 5 can also be chosen according to device application, need, and manufacturing capability, but typically varies between about 10 nm and about 1 micron. It is noted that the thickness of top layer 5 does not affect the HR properties of substrate 1.

HR substrate 1 also comprises insulating layer 4 on which top layer 5 is arranged. Insulating layer 4 commonly comprises silicon dioxide, since this material can be easily formed either by deposition or by oxidation of a silicon substrate. The insulating layer can also comprise silicon nitride, high k dielectric materials, low k dielectric materials, or a combination of layers such materials. The thickness of the insulating layer can be from a few nm, to 10 nm, to 100 nm, up to 200 nm, or other thicknesses.

HR substrate 1 also comprises support 2 which, in contrast to what is known in the prior art, has a standard resistivity. A standard resistivity support is one that has not been designed to provide HR properties and therefore has a resistivity that is standard or normal for that particular type of support and doping level. For example, standard or normal resistivity can be between about 8 Ohm-cm and about 30 Ohm-cm. Such standard-resistivity supports cost less than HR supports, and further, can be selected to have economical crystalline properties or other features. For example, supports can comprise quartz, poly-crystalline silicon, poly-crystalline silicon carbide, poly-crystalline aluminium nitride, and the like. It can also be a reclaimed silicon wafer that has been used in preceding manufacturing steps.

HR substrate 1 also comprises high-resistivity semiconductor layer 3 arranged on top of the support substrate but below insulating layer 4. As the high-resistivity of substrate 1 arises primarily from the high-resistivity of semiconductor layer 3, it is preferred that the HR semiconductor layer has sufficient resistivity and sufficient thickness so that the resistivity of substrate 1 is suitable to its intended application. In preferred embodiments, HR semiconductor layer 3 has a resistivity greater than about 103 Ohms-cm, or more preferably greater than about 104 Ohm-cm, and a thickness between about 20 nm and 5000 nm.

HR semiconductor layer 3 preferably comprises amorphous silicon having high-resistivity by virtue of a lack of doping (or lack of intentional doping), e.g., having concentrations of either p-type or n-type dopants that are preferably less than about 5×1012/cm3. Optionally, the resistivity of this layer can be enhanced by doping with nitrogen species at a density of, e.g., between 1013/cm3 to 1015/cm3. Amorphous silicon layers are preferred since they can be provided at low-cost and on many types of supports. HR semiconductor layer 3 can also comprise poly-crystalline silicon, or less preferably, mono-crystalline silicon.

FIG. 2 illustrates another embodiment of HR substrate 11 of the invention which comprises several elements that are similar to corresponding elements of the prior embodiments. Similar elements include: support 2 having a standard or normal resistivity, high-resistivity semiconductor layer 3 arranged on the support substrate and having a resistivity preferably greater than 103 Ohms-cm, insulating layer 4 arranged on high-resistivity layer 2, and top layer 5 arranged on the insulating layer. Prior descriptions of these elements are not repeated here.

In contrast to the prior embodiments, HR substrate 11 also comprises diffusion barrier layer 6 on top of support 2 but below high-resistivity semiconductor layer 3.

The diffusion barrier avoids or limits the diffusion of contaminants or dopants from the support into the HR semiconductor layer that would be likely to reduce its high-resistivity. Such a contaminants. Diffusion barrier layer 6 can comprise single or multiple layers of silicon dioxide, silicon nitride, combinations of these materials, or other materials, and can have a thickness of at least 20 nm. In preferred embodiments, diffusion barrier layer 6 comprises nitride rich silicon nitride, e.g., SiXNY that incorporates more nitrogen atoms than stochiometric, e.g., Si3N4, silicon nitride. Nitride rich silicon nitride, for instance formed by chemical vapour deposition that can be plasma assisted, is known to be both a diffusion barrier and a high-resistivity dielectric.

It should be understood that diffusion of dopants and contaminants from the top layer 5 into the high-resistivity semiconductor layer 3 is similarly limited or prevented by insulating layer 4, and can be even further reduced by selecting appropriate materials for this layer. For instance, insulating layer 4 can comprise a nitride-rich silicon nitride layer that can act as an efficient diffusion barrier layer.

Diffusion barrier layer 6 of this preferred embodiment has advantages beyond simply acting to effectively prevent diffusion of dopants or contaminants into high-resistivity semiconductor layer 3. This diffusion barrier layer is also a high-resistivity dielectric that can contribute to the high-resistivity of the substrate, and can form a source of N species that can migrate into the high-resistivity semiconductor layer 3 and further increase its resistivity.

FIGS. 3 a to 3 e illustrate embodiments of methods for manufacturing substrates 1 of the invention.

FIG. 3 a illustrates initial support 2 having standard resistivity, which can comprise, e.g., a mono-crystalline silicon wafer having a resistivity between about 8 Ohms-cm and about 30 Ohms-cm.

FIG. 3 b illustrates a next step which forms first intermediate structure 7 by placing and/or forming high-resistivity semiconductor layer 3 on support 2. HR semiconductor layer 3 can be formed by, e.g., depositing an undoped amorphous or poly-crystalline silicon layer on the support 2 by means of chemical vapour deposition or physical vapour deposition.

FIGS. 3 c and 3 d illustrate alternatives for the next step which forms and/or places insulating layer 4 on first intermediate structure 7. The alternative illustrated in FIG. 3 c includes forming insulating layer 4 by depositing insulation material on HR semiconductor layer 3 of the first intermediate structure, or by oxidizing undoped silicon HR semiconductor layer 3 should this layer comprises silicon.

The alternative illustrated in FIG. 3 d first forms insulating layer 4 primarily on or in donor substrate 8, and second, places insulating layer 4 on first intermediate structure 7 during assembly of first intermediate structure 7 with donor substrate 8 to form second intermediate structure 9 FIG. 3 e. Optionally, donor substrate 8 can initially comprise a surface insulating layer.

FIG. 3 e illustrates a further step which bonds first intermediate structure 7 and donor substrate 8 to form second intermediate structure 9. In the alternative of FIG. 3 c, first intermediate structure 7 already has surface insulating layer 4; while in the alternative of FIG. 3 d, the donor substrate 8 has surface insulating layer 4. Bonding of donor substrate 8 to first intermediate structure 7 can optionally be facilitated by, before the step of assembling, a further step of polishing the exposed surface of intermediate structure 7 and/or of the substrate 8 and/or of insulating layer 4.

In a final step not illustrated, the thickness of donor substrate 8 of second intermediate structure 9 is reduced to form final substrate 1 by known thickness reducing techniques, e.g., grind and etch back techniques, Smart Cut® techniques (that perform ion implantation and fracture), or other techniques.

During the steps of assembling and/or reducing the thickness, it can be advantageous to apply thermal treatments. Although such treatments can transform the nature of high-resistivity semiconductor layer 3, e.g., from an amorphous layer as initially deposited into a poly-crystalline layer 3 after thermal treatment, the high-resistivity is this layer is not expected to be substantially changed.

FIGS. 4 a to 4 f illustrate embodiments of methods for manufacturing HR substrate 11, which as described, comprises diffusion barrier layer 6 on top of support 2 but under HR semiconductor layer 3. The present embodiment has similarities to the prior embodiment, e.g., the nature of the materials, the resistivity level of the materials, and an optional step polishing before assembly. Prior descriptions of these steps are not repeated here.

FIG. 4 a illustrates initial support 2 having standard resistivity.

FIG. 4 b illustrates a next step in which diffusion barrier layer 6 is formed and/or placed on support 2, preferably by chemical vapour deposition (optionally plasma enhanced) of a nitride rich silicon nitride material. Diffusion barrier layer 6 allows more flexibility in the manufacturing process.

FIG. 4 c illustrates a further step of forming and/or placing HR semiconductor layer 3 on diffusion barrier layer 6.

FIGS. 4 d and 4 e illustrate alternative steps for forming and/or placing insulating layer 4 on HR semiconductor layer 3. These steps are similar to the steps illustrated in FIGS. 3 c and 3 d and the corresponding prior descriptions are not repeated here.

FIG. 4 f illustrates a further step in which the intermediate structure is assembled with donor substrate 8 to form a second intermediate structure 9.

In a final step (not illustrated), the thickness of donor substrate 8 of second intermediate structure 9 is reduced to form final substrate 11 by known thickness reducing techniques.

Optionally, the resistivity of HR semiconductor layer 3 can be further increased by introducing nitrogen species into that layer by, e.g., forming diffusion barrier layer 6 that is nitrogen rich so nitrogen species can migrate into high-resistivity layer 3 during processing, or by implanting nitrogen species, e.g., nitrogen ions, through top layer 5 and insulating layer 4. A preferred concentration of nitrogen species is between 1013/cm3 to 1015/cm3.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4300150Jun 16, 1980Nov 10, 1981North American Philips CorporationLateral double-diffused MOS transistor device
US4771016Apr 24, 1987Sep 13, 1988Harris CorporationUsing a rapid thermal process for manufacturing a wafer bonded soi semiconductor
US5399507Jun 27, 1994Mar 21, 1995Motorola, Inc.Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications
US5750000Nov 25, 1996May 12, 1998Canon Kabushiki KaishaSemiconductor member, and process for preparing same and semiconductor device formed by use of same
US5773151Jun 30, 1995Jun 30, 1998Harris CorporationIntergrated circuits that operate at microwave frequencies
US6063713Nov 10, 1997May 16, 2000Micron Technology, Inc.Methods for forming silicon nitride layers on silicon-comprising substrates
US6140163Jul 11, 1997Oct 31, 2000Advanced Micro Devices, Inc.Method and apparatus for upper level substrate isolation integrated with bulk silicon
US6166411Oct 25, 1999Dec 26, 2000Advanced Micro Devices, Inc.Heat removal from SOI devices by using metal substrates
US6221732Apr 11, 2000Apr 24, 2001Sharp Kabushiki KaishaMethod of producing semiconductor device
US6391744Mar 19, 1997May 21, 2002The United States Of America As Represented By The National Security AgencyMethod of fabricating a non-SOI device on an SOI starting wafer and thinning the same
US6538916Sep 27, 2001Mar 25, 2003Kabushiki Kaisha ToshibaSemiconductor memory device
US6645795May 3, 2001Nov 11, 2003International Business Machines CorporationPolysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator
US6646307Feb 21, 2002Nov 11, 2003Advanced Micro Devices, Inc.MOSFET having a double gate
US6664598Sep 5, 2002Dec 16, 2003International Business Machines CorporationPolysilicon back-gated SOI MOSFET for dynamic threshold voltage control
US6812527Sep 5, 2002Nov 2, 2004International Business Machines CorporationMethod to control device threshold of SOI MOSFET's
US6815296Sep 11, 2003Nov 9, 2004International Business Machines CorporationPolysilicon back-gated SOI MOSFET for dynamic threshold voltage control
US6826320Feb 19, 2002Nov 30, 2004Sioptical, Inc.Focusing mirror and lens
US6946373Nov 20, 2002Sep 20, 2005International Business Machines CorporationRelaxed, low-defect SGOI for strained Si CMOS applications
US6955971Nov 12, 2003Oct 18, 2005S.O.I.Tec Silicon On Insulator Technologies S.A.Semiconductor structure and methods for fabricating same
US7018873Aug 13, 2003Mar 28, 2006International Business Machines CorporationMethod of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate
US7089515Mar 9, 2004Aug 8, 2006International Business Machines CorporationThreshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power
US7102206Jan 12, 2004Sep 5, 2006Matsushita Electric Industrial Co., Ltd.Semiconductor substrate, method for fabricating the same, and method for fabricating semiconductor device
US7221038Feb 15, 2005May 22, 2007S.O.I.Tec Silicon On Insulator Technologies S.A.Method of fabricating substrates and substrates obtained by this method
US7273785Oct 15, 2004Sep 25, 2007International Business Machines CorporationMethod to control device threshold of SOI MOSFET's
US7358166Aug 19, 2005Apr 15, 2008International Business Machines CorporationRelaxed, low-defect SGOI for strained Si CMOS applications
US7387946Jun 7, 2005Jun 17, 2008Freescale Semiconductor, Inc.Method of fabricating a substrate for a planar, double-gated, transistor process
US7417288Dec 19, 2005Aug 26, 2008International Business Machines CorporationSubstrate solution for back gate controlled SRAM with coexisting logic devices
US7422958Jun 21, 2007Sep 9, 2008S.O.I.Tec Silicon On Insulator TechnologiesMethod of fabricating a mixed substrate
US7883990Oct 31, 2007Feb 8, 2011International Business Machines CorporationHigh resistivity SOI base wafer using thermally annealed substrate
US20020170487Sep 26, 2001Nov 21, 2002Raanan ZehaviPre-coated silicon fixtures used in a high temperature process
US20030039439Feb 12, 2002Feb 27, 2003Optronx, Inc.Optical coupler having evanescent coupling region
US20030057487Nov 29, 2001Mar 27, 2003Kabushiki Kaisha ToshibaSemiconductor chip having a functional block positioned in silicon-on-insulator region and another functional block positioned in bulk region in a single chip
US20040079993Oct 25, 2002Apr 29, 2004International Business Machines CorporationSilicon-on-insulator (SOI) integrated circuit (IC) chip with the silicon layers consisting of regions of different thickness
US20040150067Nov 12, 2003Aug 5, 2004Bruno GhyselenForming dilectric over substrate; controlling thickness; bonding
US20040171232Nov 6, 2003Sep 2, 2004CeaMethod of detaching a thin film at moderate temperature after co-implantation
US20040256700Jun 17, 2003Dec 23, 2004International Business Machines CorporationHigh-performance CMOS devices on hybrid crystal oriented substrates
US20050112845Oct 18, 2004May 26, 2005Bruno GhyselenMethod for fabricating a substrate with useful layer on high resistivity support
US20050205930Jun 25, 2004Sep 22, 2005Voxtel, Inc.Silicon-on-insulator active pixel sensors
US20060016387Nov 14, 2003Jan 26, 2006Takashi YokoyamaSilicon wafer, its manufacturing method, and its manufacturing apparatus
US20060125013Feb 9, 2006Jun 15, 2006International Business Machines CorporationDouble silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
US20060154442Jan 7, 2005Jul 13, 2006International Business Machines CorporationQuasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
US20060166451Mar 24, 2006Jul 27, 2006Jean-Pierre RaskinProcess for manufacturing a multilayer structure made from semiconducting materials
US20060264004May 23, 2005Nov 23, 2006Ziptronix, Inc.Method of detachable direct bonding at low temperatures
US20060276004Jun 7, 2005Dec 7, 2006Freescale Semiconductor, Inc.Method of fabricating a substrate for a planar, double-gated, transistor process
US20070032040 *Sep 27, 2004Feb 8, 2007Dimitri LedererMethod of manufacturing a multilayer semiconductor structure with reduced ohmic losses
US20070138558Dec 12, 2006Jun 21, 2007Naoto SaitohSemiconductor integrated circuit device
US20070190681Feb 13, 2006Aug 16, 2007Sharp Laboratories Of America, Inc.Silicon-on-insulator near infrared active pixel sensor array
US20080029815Aug 2, 2006Feb 7, 2008Hao-Yu ChenSemiconductor-on-insulator (SOI) strained active area transistor
US20080054352Aug 29, 2007Mar 6, 2008Sony CorporationSemiconductor device and method of manufacturing semiconductor device
US20080079123Sep 18, 2007Apr 3, 2008Marek KostrzewaMethod of fabricating a mixed microtechnology structue and a structure obtained thereby
US20080105925Nov 3, 2006May 8, 2008Sangwoo PaeProcess charging and electrostatic damage protection in silicon-on-insulator technology
US20080124847Aug 4, 2006May 29, 2008Toshiba America Electronic Components, Inc.Reducing Crystal Defects from Hybrid Orientation Technology During Semiconductor Manufacture
US20080153313Feb 21, 2007Jun 26, 2008Oleg KononchukMethod for producing a semiconductor-on-insulator structure
US20100127345 *Nov 25, 2008May 27, 2010Freescale Semiconductor, Inc.3-d circuits with integrated passive devices
DE4232844A1Sep 30, 1992Mar 31, 1994Siemens AgExposure method for optical projection lithography used in integrated circuit mfr. - applying imaged structure to non-planar surface of exposure mask to increase image sharpness
FR2906078A1 Title not available
FR2910702A1 Title not available
JPH08124827A Title not available
WO2004100268A1Apr 28, 2004Nov 18, 2004Canon KkSubstrate, manufacturing method therefor, and semiconductor device
WO2005031842A1 Title not available
Non-Patent Citations
Reference
1"Controlled, Varying Depth Etching for VIA Holes and for Variable Conductor Thickness," IBM Technical Disclosure Bulletin, 31(7): 81-82 (Dec. 1988).
2Disney, "SOI Smart IGBT with Low Cost and High Performance," IEEE International Symposium on Power Semiconductor Devices and IC's, May 1997, pp. 289-292.
3French Preliminary Search Report, FA 709128, FR 0803676 dated Feb. 2, 2009.
4French Preliminary Search Report, FA 709339, FR 0803700, dated May 11, 2009.
5H. Nagano et al., XP009097417, "SOI/Bulk Hybrid Wafer Fabrication Process Using Selective Epitaxial Growth (SEG) Technique for High-End SoC Applications", Japanese Journal of Applied Physics, vol. 42, No. 4B, pp. 1882-1886 (2003).
6International Search Report and Written Opinion of the International Searching Authority, application No. PCT/US2009/044810, Jan. 13, 2010.
7International Search Report, and Written Opinion of the International Searching Authority, application No. PCT/US2009/044825, Jan. 13, 2010.
8International Search Report, application No. PCT/US2009/044365, Jul. 16, 2009.
9International Search Report, application No. PCT/US2009/044372, Jul. 10, 2009.
10Maleville et al., "Multiple SOI layers by multiple Smart Cut® transfers," IEEE International SOI Conference, Oct. 2000, pp. 134-135.
11Non-Final Office Action, U.S. Appl. No. 12/469,436, dated Jan. 25, 2011.
12Non-Final Office Action, U.S. Appl. No. 12/470,253, dated Aug. 3, 2010.
13Non-Final Office Action, U.S. Appl. No. 12/470,253, dated Dec. 9, 2010.
14Rajkumar et al., "Effects of Nitrogen Plasma Immersion Ion Implantation in Silicon," Engineering Thin Films With Ion Beams, Nanoscale Diagnostics, and Molecular Manufacturing, Proceedings of the SPIE, vol. 4468, pp. 131-139 (2001).
15Restriction Requirement, U.S. Appl. No. 12/470,253, dated Jul. 12, 2010.
16Search Report of French Patent Application No. 0803696.
17Search Report of French Patent Application No. 0803697 dated Feb. 17, 2009.
18Search Report of French Patent Application No. 0803701 dated Feb. 18, 2009.
19Yang et al., "High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations," International Electron Devices Meeting, Dec. 2003, pp. 18.7.1-18.7.3.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8536035Feb 1, 2012Sep 17, 2013International Business Machines CorporationSilicon-on-insulator substrate and method of forming
US8741739Jan 3, 2012Jun 3, 2014International Business Machines CorporationHigh resistivity silicon-on-insulator substrate and method of forming
US20120235283 *Mar 13, 2012Sep 20, 2012Memc Electronic Materials, Inc.Silicon on insulator structures having high resistivity regions in the handle wafer
Classifications
U.S. Classification257/169, 257/523, 257/364, 438/478, 438/354, 257/E29.152, 257/218, 438/141
International ClassificationH01L29/02
Cooperative ClassificationH01L21/76251
European ClassificationH01L21/762D8
Legal Events
DateCodeEventDescription
Jun 11, 2009ASAssignment
Owner name: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, FRANC
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NGUYEN, BICH-YEN;MAZURE, CARLOS;REEL/FRAME:022815/0261;SIGNING DATES FROM 20090505 TO 20090519
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NGUYEN, BICH-YEN;MAZURE, CARLOS;SIGNING DATES FROM 20090505 TO 20090519;REEL/FRAME:022815/0261