Publication number | US8005135 B1 |

Publication type | Grant |

Application number | US 12/643,965 |

Publication date | Aug 23, 2011 |

Filing date | Dec 21, 2009 |

Priority date | Apr 28, 2000 |

Fee status | Paid |

Also published as | US7254198, US7646807, US7664172, US7756228, US8447000, US20120183025 |

Publication number | 12643965, 643965, US 8005135 B1, US 8005135B1, US-B1-8005135, US8005135 B1, US8005135B1 |

Inventors | Tulsi Manickam, Peter J. Sallaway, Sreen A. Raghavan, Abhijit M. Phanse, James B. Wieser |

Original Assignee | National Semiconductor Corporation |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (37), Non-Patent Citations (7), Referenced by (4), Classifications (9), Legal Events (1) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 8005135 B1

Abstract

An analog equalizer (**613** and **614**) adaptively equalizes an input analog signal affected with intersymbol interference (“ISI”), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter (**210**) converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer (**212**) adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder (**605**) decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols. Equalization control circuitry (**213, 214,** and **217**) adjusts equalization filter characteristics of the equalizers such that adjustments of the filter characteristics of one of the equalizers depend adaptively on adaptive adjustments of the filter characteristics of the other equalizer.

Claims(20)

1. A receiver system comprising:

a pre-filtering analog equalizer for adaptively performing analog equalization on a symbol-information-carrying input analog signal affected with intersymbol interference, or on a first intermediate analog signal generated from the input analog signal, to produce a filtered partially equalized analog signal with reduced intersymbol interference;

an analog-to-digital converter for converting the filtered analog signal, or a second intermediate analog signal generated from the filtered analog signal, into an initial digital signal;

a digital equalizer for adaptively performing digital equalization on the initial digital signal, or on an intermediate digital signal generated from the initial digital signal, to produce an equalized digital signal as a stream of equalized digital values with further reduced intersymbol interference;

an output decoder for decoding the equalized digital values, or intermediate digital values generated from the equalized digital values, into a stream of symbols; and

equalization control circuitry for adjusting equalization filter characteristics of the analog and digital equalizers such that adjustments of the filter characteristics of a specified one of the equalizers depend adaptively on adaptive adjustments of the filter characteristics of the other of the equalizers.

2. A receiver system as in claim 1 wherein the control circuitry adaptively adjusts the filter characteristics of the specified equalizer in response to information provided by operating on the equalized digital values or on further digital values generated from the equalized digital values.

3. A receiver system as in claim 1 wherein the control circuitry adaptively adjusts (a) a specified parameter of the filter characteristics of the specified equalizer in response to an error signal generated by decoding the equalized digital values or further digital values generated from the equalized digital values and (b) a specified parameter of the other of the equalizers in response to the adaptively adjusted parameter of the filter characteristics of the specified equalizer.

4. A receiver system as in claim 3 wherein the error signal at any time during operation of the receiver system varies according to the difference between (i) the equalized digital value at that time or a further digital value generated from that equalized digital value and (ii) the value of a corresponding one of an alphabet of predefined symbols from which the stream of symbols is substantially formed, the corresponding predefined symbol being produced by decoding that equalized digital value or that further digital value.

5. A receiver system as in claim 4 wherein the predefined symbols used in generating the error signal are generated along a different signal processing path than the stream of symbols.

6. A receiver system as in claim 3 further including an additional decoder for generating the error signal.

7. A receiver system as in claim 6 wherein the additional decoder comprises a slicer.

8. A receiver system as in claim 1 further including an echo canceller for causing the equalized digital values or the intermediate digital values generated from the equalized digital values to be produced with reduced effects of echo in the analog input signal.

9. A receiver system as in claim 8 wherein the echo canceller performs echo reduction on at least one of (a1) the input analog signal, (a2) a third intermediate analog signal generated from the input analog signal, (a3) the filtered analog signal, and (a4) a fourth intermediate analog signal generated from the filtered analog signal or/and on at least one of (b1) the initial digital signal, (b2) a further intermediate digital signal generated from the initial digital signal, (b3) the equalized digital values, and (b4) further digital values generated from the equalized digital values.

10. A receiver system as in claim 8 wherein the echo canceller performs echo reduction on at least one of (a1) the input analog signal, (a2) a third intermediate analog signal generated from the input analog signal, (a3) the filtered analog signal, and (a4) a fourth intermediate analog signal generated from the filtered analog signal and on at least one of (b1) the initial digital signal, (b2) a further intermediate digital signal generated from the initial digital signal, (b3) the equalized digital values, and (b4) further digital values generated from the equalized digital values.

11. A receiver system as in claim 10 wherein the echo canceller adaptively performs echo reduction.

12. A receiver system as in claim 8 wherein the echo canceller operates in response to error information indicative of how much the equalized digital values or further digital values generated from the equalized digital values differ from decoded information generated by decoding the equalized or further digital values.

13. A receiver system as in claim 12 wherein the decoded information utilized in generating the error information is generated along a different signal processing path than the stream of symbols.

14. A receiver system as in claim 1 further including a crosstalk canceller for causing the equalized or/and intermediate digital values to be produced with reduced effects of crosstalk in the input analog signal.

15. A receiver system as in claim 14 wherein the crosstalk canceller performs the crosstalk reduction at least partially adaptively.

16. A method comprising:

adaptively performing analog equalization on a symbol-information-carrying input analog signal affected with intersymbol interference, or on a first intermediate analog signal generated from the input analog signal, to produce a filtered partially equalized analog signal with reduced intersymbol interference;

converting the filtered analog signal, or a second intermediate analog signal generated from the filtered analog signal, into an initial digital signal;

adaptively performing digital equalization on the initial digital signal, or on an intermediate signal generated from the initial digital signal, to produce an equalized digital signal as a stream of equalized digital values with further reduced intersymbol interference;

decoding the equalized digital values, or intermediate digital values generated from the equalized digital values, into a stream of symbols; and

adjusting equalization filter characteristics during the equalization-performing acts such that adjustments of the filter characteristics during a specified one of the equalization-performing acts depend adaptively on adaptive adjustments of the filter characteristics during the other of the equalization-performing acts.

17. A method as in claim 16 wherein the characteristics-adjusting act comprises adaptively adjusting the filter characteristics during the specified equalization-performing act in response to information provided by operating on the equalized digital values or on further digital values generated from the equalized digital values.

18. A method as in claim 16 wherein the characteristics-adjusting act comprises adaptively adjusting (a) a specified parameter of the filter characteristics during the specified equalization-performing act in response to an error signal and (b) a specified parameter of the filter characteristics during the other of the equalization-performing acts in response to the adaptively adjusted parameter of the filter characteristics during the specified equalization-performing act.

19. A method as in claim 18 wherein the adaptively adjusting act includes:

decoding one of the equalized digital values, or a further digital value generated from that digital value, to produce a corresponding one of an alphabet of predefined symbols from which the stream of symbols is substantially formed; and

generating the error signal to vary according to the difference between (i) that equalized digital value or that further digital value and (ii) the value of the corresponding predefined symbol.

20. A method as in claim 19 wherein the predefined symbols used in generating the error signal are generated along a different signal processing path than the stream of symbols.

Description

This is a continuation of U.S. patent application Ser. No. 11/490,437, filed 19 Jul. 2006, now U.S. Pat. No. 7,646,807 B1, which is a division of U.S. patent application Ser. No. 09/561,086, filed Apr. 28, 2000, now U.S. Pat. No. 7,254,198 B1.

This invention relates to digital communication systems and, more particularly, to an optimal architecture for receiver processing.

The dramatic increase in desktop computing power driven by intranet-based operations and the increased demand for time-sensitive delivery between users has spurred development of high speed Ethernet local area networks (LANs). 100BASE-TX Ethernet (see IEEE Std. 802.3u-1995 *CSMA/CD Access Method, Type *100 *Base*-*T*) using existing category 5 (CAT-5) copper wire, and the newly developing 1000BASE-T Ethernet (see IEEE Draft P802.3ab/D4.0 *Physical Layer Specification for *1000 *Mb/s Operation on Four Pairs of Category *5 *or Better Twisted Pair Cable *(1000 *Base*-T)) for gigabit-per-second transfer of data over category 5 data grade copper wiring, require new techniques in high speed symbol processing. On category 5 cabling, gigabit-per-second transfer can be accomplished utilizing four twisted pairs and a 125 megasymbol-per-second transfer rate on each pair where each symbol represents two bits.

Physically, data is transferred using a set of voltage pulses where each voltage represents one or more bits of data. Each voltage in the set is referred to as a symbol and the whole set of voltages is referred to as a symbol alphabet.

One system of transferring data at high rates is Non-Return-to-Zero (NRZ) signaling. In NRZ, the symbol alphabet {A} is {−1, +1}. A logical “1” is transmitted as a positive voltage while a logical “0” is transmitted as a negative voltage. At 125 megasymbols per second, the pulse width of each symbol (the positive or negative voltage) is 8 ns.

An alternative modulation method for high speed symbol transfer is Multilevel Threshold-3 (MLT3) and involves a three-level system. (See American National Standard Information System, *Fibre Distributed Data Interface *(*FDDI*)-*Part: Token Ring Twisted Pair Physical Layer Medium Dependent *(*TP*-*PMD*), ANSI X3.263:199X.) The symbol alphabet {A} for MLT3 is {−1, 0, +1}. In MLT3 transmission, a logical “1” is transmitted by either a −1 or a +1 while a logical “0” is transmitted as a 0. A transmission of two consecutive logical “1”s does not require the system to pass through zero in the transition. A transmission of the logical sequence (“1”, “0”, “1”) results in transmission of the symbols (+1, 0, −1) or (−1, 0, +1), depending on the symbols transmitted prior to this sequence. If the symbol transmitted immediately prior to the sequence was a +1, the symbols (+1, 0, −1) are transmitted. If the symbol transmitted before this sequence was a −1, the symbols (−1, 0, +1) are transmitted. If the symbol transmitted immediately before this sequence was a 0, the first symbol of the sequence transmitted will be a +1 if the previous logical “1” was transmitted as a −1 and will be a −1 if the previous logical “1” was transmitted as a +1.

The detection system in the MLT3 standard, however, needs to distinguish between three levels, instead of two levels as in a more typical two-level system. The signal-to-noise ratio required to achieve a particular bit error rate is higher for MLT3 signaling than for two-level systems. The advantage of the MLT3 system, however, is that the energy spectrum of the emitted radiation from the MLT3 system is concentrated at lower frequencies and therefore more easily meets FCC radiation emission standards for transmission over twisted pair cables. Other communication systems may use a symbol alphabet having more than two voltage levels in the physical layer in order to transmit multiple bits of data using each individual symbol. In Gigabit Ethernet over twisted pair CAT-5 cabling, for example, five-level Pulse-Amplitude Modulation (PAM-5) data can be transmitted at a baud rate of 125 megabaud. (See IEEE Draft P802.3ab/D4.0 *Physical Layer Specification for *1000 *Mb/s Operation on Four Pairs of Category *5 *or Better Twisted Pair Cable *(1000 *Base*-*T*).)

Therefore, there is a necessity for a receiver capable of receiving signals having large intersymbol interference from long transmission cables. There is also a necessity for reducing the difficulties associated with digital equalization of signals with large intersymbol interference without losing the equalization versatility required to optimize the receiver.

In accordance with the invention, a receiver system for providing signal equalization is partitioned into an analog pre-filter and a digital receiver. At least some of the intersymbol interference is removed from the signal by the analog pre-filter before the signal is processed through a digital equalizer in the digital receiver. Signals having a large amount of intersymbol interference, such as those transmitted through long cables, are preprocessed through the pre-filter, thereby reducing the difficulties of digital equalization without losing the versatility of the digital equalizer.

Embodiments of the invention can include any equalization scheme, including linear equalization, decision feedback equalization, trellis decoding and sequence decoding, separately or in combination. Embodiments of the invention may also include cable quality and cable length indication and baseline wander correction. Further, embodiments of receivers according to the present invention can also include echo cancellation and near end crosstalk (NEXT) cancellation.

These and other embodiments of the invention are further explained below along with the following figures.

**3**B and **3**C on an input signal.

**6**B, **6**C, **6**D and **6**E show embodiments of a multi-wire receiver system according to the present invention.

In the figures, elements having similar or identical functions may have identical identifiers.

**100** for a single-wire transmission channel. Transmission system **100** includes transmitter **107**, transmission channel **102** and receiver **103**. Transmitter **107** transmits a symbol stream {a_{k}} and can perform some signal shaping on the waveform formed by symbol stream {a_{k}}. Notationally, a particular symbol in clock cycle k is denoted without brackets as a_{k }whereas the symbol sequence or stream is denoted with curly brackets as {a_{k}}.

Transmission channel **102** which can be any transmission medium distorts the transmitted waveform, creates intersymbol interference, and adds noise to the transmitted signal. Receiver **103** receives the transmitted signals from transmission channel **102**. Receiver **103** includes an analog-to-digital converter (ADC) **104** and an equalizer **106** connected in series. In receiver **103** of **103** is accomplished digitally. Digital equalization becomes problematic as the cable length increases due to the large intersymbol interference associated with longer cables.

In general, a signal received by receiver **103** includes contributions from several transmitted symbols as well as noise and channel distortions. Each transmitted symbol is diffused in the transmission process so that it is commingled with symbols being transmitted at later transmission times. This effect is known as “intersymbol interference” (ISI). (See E. A. LEE AND D. G. MESSERCHMITT, DIGITAL COMMUNICATIONS (1988).)

Intersymbol interference is a result of the dispersive nature of the communication channel. The IEEE LAN standards require that LAN communication systems be capable of transmitting and receiving data through at least a 100 meter cable. In a 100 meter cable, the signal strength at the Nyquist frequency of 62.5 Mhz is reduced nearly 20 db at the receiving end of the cable. Given this dispersion, a single symbol may affect symbols throughout the transmission cable of transmission channel **102**.

An input signal x_{k }to receiver **103** at sample time k, neglecting channel distortion and noise, can be digitally represented as

*x* _{k} *=C* _{0} *a* _{k} *+C* _{1} *a* _{k−1} *+ . . . +C* _{j} *a* _{k−j }. . . , (1)

where a_{k−j }represents the (k−j)th symbol in the symbol sequence and coefficient C_{j }represents the contribution of the (k−j)th symbol to signal x_{k}. Equalizer **106** receives digitized sample x_{k }and deduces currently received symbol â_{k }by removing, usually adaptively, the contribution of previous symbols a_{k−j }from detected sample x_{k }(i.e., by removing the intersymbol interference). The deduced symbol â_{k }represents the best estimation by receiver **103** as to what the transmitted symbol a_{k }was.

However, with long cable lengths, the contribution of earlier received symbols becomes significant. For example, with cable lengths above about 100 meters, coefficient C_{1 }for immediately previous symbol a_{k−1 }can be as high as 0.95 (i.e., 95% of symbol a_{k−1 }may be represented in the input signal). Contributions from other previous symbols can also be high. Given that equalizer **106** cannot adjust for the contribution of symbols not yet received (e.g., the kth detected sample cannot include contributions from the (k+1)th transmitted symbol), equalizer **106** has a difficult time distinguishing the kth and the (k−1)th symbol under these circumstances. An adaptive receiver can have particular difficulty upon startup in distinguishing the contribution of the kth symbol from the contribution of the (k−1)th symbol and in determining the equalizer parameters corresponding to the mixing parameters {C_{j}}.

Therefore, for large cable lengths a digital equalizer is faced with deducing the current symbol from a sample containing significant contributions from numerous previously received symbols. The difficulty is not only deducing the symbols but in adaptively choosing the operating parameters of the equalizer in order to optimize the performance of receiver **103**.

An alternative approach to digital equalization is analog equalization. **110** having an analog receiver **111** coupled to transmission channel **102**. Receiver **111** includes an analog equalizer **112** having an analog filter tailored to remove intersymbol interference from the received signal. Although having the advantage of processing loop speed, equalizer **112** cannot be adaptively optimized for the performance of receiver **111**.

**200** according to the present invention. Transmission system **200** includes a transmitter **221**, a transmission channel **201** and a receiver system **206**. Transmitter **221** outputs a symbol stream {a_{k}} to transmission channel **201**. Transmitter **221** can output symbol stream {a_{k}} directly or, in some embodiments of the invention, perform some pre-processing of the waveform formed by the sequential transmission of the symbol stream {a_{k}}.

Transmission channel **201** represents the transmission of a signal between transmitter **221** and receiver **206** and can include any transmission medium, including twisted copper, coaxial cable or optical fiber. The symbol stream {a_{k}} can be composed of any symbol alphabet, including NRZ, MLT3, PAM-5 (where the symbol alphabet is given by {−2, −1, 0, 1, 2}) or any other symbol alphabet and modulation that are used in transceivers such as transmission system **200**.

Transmission system **200** may be a portion of a larger transceiver system. In general, transceivers of this type may have any number of transmission channels similar to transmission channel **201**. For example, gigabit-per-second transfer of data can be accomplished using four transmission channels, each with one twisted pair cable. Further, transmission channels such as transmission channel **201** can be bi-directional, i.e., transmit data in both directions. For example, receiver **206** may be associated with a transmitter that transmits symbol streams to other receivers coupled to the same cable as is included in transmission channel **201**. Any number of transmitters and receivers may be coupled to the cable associated with transmission channel **201**. Each coupling may affect the response of transmission channel **201**.

The transmitted symbols in the sequence {a_{k}} are members of the symbol alphabet {A}. In the exemplary case of PAM-5 signaling, the symbol alphabet {A} is given by {−2, −1, 0, +1, +2}. The index k again represents the time index for each transmitted symbol, i.e., at sample time k, the symbol being transmitted to transmission channel **201** is given by a_{k}.

The real-time output of transmitter **221** can be represented as A_{s}(ω), where A_{s}(ω) is the Fourier transform of the analog signal a_{s}(t) that represents the symbol stream {a_{k}}. Therefore,

Signal a_{s}(t) also represents the effects of any pre-shaping that may be performed by transmitter **221**.

The output signal y_{k }or Y_{s}(ω) from transmission channel **201**, now treated as an analog signal, suffers from channel distortion, the addition of random noise, and a flat signal loss. Referring to _{s}(ω) is the Fourier transform of the analog signal that represents the output signal stream {Y_{k}} from transmission channel **201**. Channel output signal y_{k }or Y_{s}(ω) is input to receiver **206**.

As shown in **201** can be modeled as having a linear, time invariant portion **202** with transfer function H_{s}(ω) and a noise portion represented as noise adder **203**. The transfer function H_{s}(ω) includes the effects of transmit and receive transformers and the transmission medium (e.g., cable) on the transmitted signal. The input signal A_{s}(ω) to transmission channel **201** and thus to portion **202** is related to the output signal X_{s}(ω) of portion **202** by the relationship

*X* _{s}(ω)=*H* _{s}(ω)*A* _{s}(ω). (3)

The total output signal Y_{s}(ω) from transmission channel **201** then is,

*Y* _{s}(ω)=*H* _{s}(ω)*A* _{s}(ω)+*n* _{s}(ω), (4)

where n_{s}(ω) is a random noise component. Equations 3 and 4 assume a linear, time invariant transmission system.

For long cable lengths, the intersymbol interference contained in signal Y_{s}(ω) can be severe, including significant portions of previously transmitted symbols in Y_{s}(ω). For example, at a cable length of above about 100 meters, the contribution of the last sent symbol to the currently received signal may be as high as 95%.

Receiver system **206** contains an analog amplifier **222**, a pre-filter **207**, and a receiver **208** constituted as a digital filter. Amplifier **222** amplifies signal y_{k }or Y_{s}(ω) from transmission channel **201**. Pre-filter **207** is described in the immediately following paragraphs. Digital filter **208** contains an anti-aliasing filter **209**, an analog-to-digital converter **210**, a digital amplifier **211**, a digital equalizer **212**, a slicer **213**, a coefficient update **214**, a digital automatic gain control **215**, a clock recovery **216**, a phase detector **217**, and an analog automatic gain control **220**. Similar to how components **217** and **220** are depicted in **217** and **220** could be described as outside digital filter **208** since their output signals go to components that precede digital filter **208**.

Pre-filter **207** receives the amplified signal from amplifier **222** and pre-shapes that signal for input to digital filter (receiver) **208**. The pre-shaping performed by pre-filter **207** can include partial removal of intersymbol interference so that less intersymbol **20** interference remains to be removed by digital equalizer **212**.

Pre-filter **207** can be designed based on frequency-sampling methods in which a desired frequency response is uniformly sampled and filter coefficients are then determined from these samples using an inverse discrete Fourier transform. For example, one embodiment of pre-filter **207** includes a one-zero two-pole filter having a frequency response of approximately the inverse of, for example, the transfer function H_{s}(ω) associated with a 50 meter cable (CAT-5) in combination with any pre-shaping that may have been performed by transmitter **221**. Pre-filter **207**, therefore, can be fixed to remove the influence of intersymbol interference from a given cable configuration, e.g., a twisted-copper pair having a particular length. Variations in the intersymbol interference inherent in variations of the cable or its length from that expected can be accommodated by adaptive functions in digital equalizer **212**.

Although pre-filter **207** can be any number of filters coupled in series, pre-filter **207** can be represented with a transfer function H_{PF}(ω) that represents the effects on an input signal of all of the filters in pre-filter **207**. Therefore, assuming that pre-filter **207** is linear and time-invariant, the Fourier transform output signal Z_{s}(ω) from pre-filter **207** is given by

*Z* _{s}(ω)=*GH* _{PF}(ω)*Y* _{s}(ω), (5)

where G is the analog gain of analog amplifier **222**. The transfer function H_{T}(ω) that represents the combination of transmission channel **201**, amplifier **222**, and pre-filter **207** is given by

*H* _{T}(ω)=*GH* _{s}(ω)*H* _{PF}(ω). (6)

Ideally, if pre-filter **207** completely compensates for transmission channel **201**, the total transfer function H_{T}(ω) is unity. In a practical transmission system, the transfer function H_{PF}(ω) of pre-filter **207** is determined by inverting the predicted or measured transfer function H_{s}(ω) of transmission channel **201**.

The frequency response H_{c}(f, 1) of the complete channel, i.e., transmission system **200** including transmission channel **201** and digital filter **208**, neglecting random noise n_{s}(ω) and not including the frequency response of pre-filter **207**, can be modeled as

*H* _{c}(*f,*1)=*H* _{PR}(*z*)*H* _{s}(*f,*1)*H* _{EQ}(*z*)*gG H* _{co}(*f*) (7)

where H_{PR }(z) is the partial response shaping accomplished by transmitter **221** before transmission, z equals e^{jωT}, ω equals 2πf, f is the frequency, and T is the symbol (and sampling) interval. H_{s}(f,1) is the frequency response of transmission channel **201**, e.g., of the CAT-5 cable, of length l and the transmit and receive transformers. In one embodiment, the partial response shaping H_{PR }(z) equals 0.75+0.25z^{−1 }where z^{−1 }represents a one-symbol period delay. H_{EQ}(z) is the transfer function of digital equalizer **212** and is generally given by

where N and M are positive integers. Inasmuch as z^{−1 }represents a one-symbol period delay, z represents a one-symbol period advance. In one embodiment, equalizer transfer function H_{EQ }(z) is chosen to be c_{−1}z+c_{0}+c_{1}z^{−1}. The parameter g is the output gain of automatic gain control (AGC) **215** in digital filter **208**. H_{co}(f) represents the frequency response of the remaining elements of the complete channel, e.g., analog-to-digital converter **210** (whose pulse can be a rectangular pulse of length T or a trapezoidal pulse with rising and falling edges of length T/2 and flat portion of length T/2) and other elements of transmission channel **201**.

The frequency response H_{s }(f,1) of transmission channel **201** is a function of cable length l. Both gain g and digital equalizer transfer function H_{EQ }(z) will depend on cable length l. The gain g is increased for increased cable length l due to increased signal loss. The coefficient parameters c_{−1}, c_{0}, and c_{1 }of equalizer transfer function H_{EQ }(z) also depend on cable length l. Channel-remainder frequency response H_{co}(f) is not a function of cable length l.

Examples of the frequency response for transmission system **200** are shown in _{s }(ω) of transmission channel **201**. As shown in _{s }(ω) approaches zero asymptotically. ^{−sτ} where s equal jω, and τ is the timing phase difference discussed below. _{PF}(s) of pre-filter **207**. **3**B and **3**C.

The frequency response H_{c}(f,1) of the complete channel does not include the effects of pre-filter **207**. The transfer function H_{PF }(s) of analog pre-filter **207** can be represented by (b_{1}s+l)/(a_{2}s^{2}+a_{1}s+1), where s again equals jω. Pre-filter transfer function H_{PF }(s), therefore, is characterized by the filter parameters b_{1}, a_{1}, and a_{2}. Transfer function H_{PF}(s) can be determined by minimizing a cost function that is related to the total intersymbol interference found in transmission system **200**.

A measure E(1) of the intersymbol interference due to the comparison of the folded spectrum with a flat spectrum can be expressed as

*E*(*l*)=∫_{−1/2T} ^{1/2T} *|[H* _{c}(*f,l*)*H* _{PF}(*s*)*e* ^{jωτ}]_{fold}−**1**|^{2} *df* (8)

The parameter τ is the timing phase difference between the transmitter digital-to-analog converter (not shown) and the receiver analog-to-digital converter (ADC **210**), as calculated by clock recovery **216**. The integral in Equation (8) represents the inverse discrete Fourier transform of all signals received in one period, e.g., −0.5/T to 0.5/T. The folded spectrum in the integral can be described by spectrum folding, which can be defined as

where X(f) is any general function of frequency.

In one embodiment, the transfer function H_{PF}(s) of analog pre-filter **207** is obtained by minimizing the cost function C given as

with respect to the filter parameters b_{1}, a_{1}, and a_{2}where w_{i }is a weight factor, l_{i }is the ith cable length, K is the number of cable lengths, and P is a high frequency penalty. The first K terms are a measure of intersymbol interference at cable lengths l_{1}, l_{2}, . . . l_{K}. In one embodiment, K equals 3. Although any number K of cable lengths can generally be used, minimizing cost function C for K equal to 1 results in an implementation of pre-filter **207** optimized for only one cable length. Alternatively, using too many cable lengths complicates the optimization. The last term P in Equation (10),

*P=∫* _{1/2T} ^{∞} *|H* _{PF}(*s*)|^{2} *df* (11)

imposes an additional penalty on the high frequency components of pre-filter transfer function H_{PF}(s). The high frequency penalty P operates to attenuate high frequency echoes. Other factors can be included in a cost function. For example, a term to reduce quantization noise can be added. This quantization term would be proportional to g√c_{1} ^{2}+c_{2} ^{2}+ . . . +c_{K} ^{2}.

Each term in the cost shown in Equation (10) is weighted by a weight factor w_{i}. These weights specify the importance of each term. The weights are chosen such that the peak magnitude of pre-filter transfer function H_{PF}(s) is not too large and so that transfer function H_{PF}(s) is small at high frequencies. The analog pre-filter **207** determined by transfer function H_{PF}(s) found by optimizing cost function C of Equation 10 minimizes the intersymbol interference for cable lengths l_{1 }through l_{K }and attenuates high frequency echo signals.

As previously described, transmission-channel transfer function H_{s}(ω,l), gain g, and equalizer transfer function H_{EQ}(z) all depend on cable length l. Timing phase difference τ from clock recovery **216** also depends on cable length l. Therefore, intersymbol interference measures E(l_{1}) through E(l_{K}) are all different. The parameters G, g, τ, the equalizer parameters in equalizer transfer function H_{EQ}(z) (e.g., c_{−1}, c_{0}, and c_{1}), and the measurement parameters in intersymbol interference measures E(l_{1}) through E(l_{K}) are those parameters that the adaptive loops in analog gain control **220**, gain control **215**, clock recovery **216**, and coefficient update **214** converge for cable lengths through l_{K}, respectively.

Minimizing intersymbol interference measure E(l) with respect to parameters b_{1}, a_{1}, and a_{2 }should enable transfer function H_{PF}(s) for pre-filter **207** to produce a flat folded spectrum if the cable length is 1. However, this is based on the assumption that the actual equalizer parameters for equalizer transfer function H_{EQ}(z), analog gain G, digital gain g, and timing phase τ are the same as those used in Equation 8 for measure E(**l**). If they are different, the results are less useful.

The better determination of equalizer parameters for equalizer transfer function H_{EQ}(z), gain g, and timing phase τ is found by an iterative procedure as described below, resulting in determination of pre-filter transfer function H_{PF}(s). With an initial choice of equalizer parameters for equalizer transfer function H_{EQ}(z), gain g, and timing phase τ, the cost function C is minimized to determine an initial version of pre-filter transfer function H_{PF}(s). Using this H_{PF}(s) version, the equalizer parameters for equalizer transfer function H_{EQ}(z), gain g, and timing phase τ are determined for each cable length l_{1 }through l_{K}. Using these new sets of equalizer parameters for transfer function H_{EQ}(z), gain g, and timing phase τ (one set of parameters for each cable length l_{1 }through l_{K}) in the cost function C, pre-filter transfer function H_{PF}(s) is recomputed. This process is repeated until there are no significant changes between successive iterations. In other words, the above procedure converges to a particular set of filter parameters for transfer function H_{PF}(s) that determines pre-filter **207**.

In one case, transmission-channel transfer function H_{s}(ω) includes the frequency response of the transmit and receive transformers, each of which is modeled as a first order transfer function with −3 dB cutoff at 100 MHz. Additionally, transmission channel **201** is a category-5 twisted copper pair cable, equalizer transfer function H_{EQ}(z) equals c_{−1}z+c_{0}+c_{1}z^{−1}, partial response shaping H_{EQ}(z) equals 0.75+0.25z^{−1}, and pulse length T equals 8 ns. The optimization of the cost function C in Equation 10 with K equals to 3 and cable lengths l_{1 }equals to 0 m, l_{2}equal to 50 m, l_{3 }equal to 120 m leads to filter transfer function H_{PF}(s) for pre-filter **207** described by

where ŝequals sT.

Alternatively, pre-filter **207** can be an adaptive analog filter. Transfer function H_{PF}(s) for an adaptive analog version of pre-filter **207** can be of the form

*H* _{PF}(*s*)=(1*−V* _{c})+*V* _{c}PF(*s*) (13)

and is controlled by the single parameter V_{c}where PF(s) is an analog filter function. The parameter V_{c }is varied in the range 0<V_{c}<1 to achieve partial equalization for various cable lengths. If V_{c }equals 0, pre-filter transfer function H_{PF}(s) is 1 (unity), i.e., no equalization is performed by pre-filter **207**. If V_{c }equals 1, transfer function H_{PF}(s) is analog filter function PF(s), i.e., maximum attainable equalization is achieved attainable by the filter structure defined by analog function PF(s) for pre-filter **207**. As V_{c }is varied linearly from 0 to 1, pre-filter transfer function H_{PF}(s) varies from unity to analog function PF(s).

Analog filter function PF(s) can represent a band-pass or high-pass filter. Therefore, the peak magnitude of the frequency response of pre-filter transfer function H_{PF}(s) increases with increasing V_{c}. If analog function PF(s) performs suitable equalization for a particular cable length l_{o}, pre-filter **207** with V_{c}<1 performs suitably for cable length l<l_{o}. Hence V_{c }is monotonic with cable length l.

For example, analog filter function PF(s) can have one zero and two poles (complex-conjugate pair) in the form

where ω_{z }is the zero frequency, ω_{n }is the pole frequency, and δ is a damping factor.

At low frequency, the filter described by Equation 14 starts from unity and rolls off as 1/s at high frequencies. Hence the filter passes less noise and high frequency echo. Moreover, a small order PF(s) requires fewer resistors, capacitors, and operational amplifiers to realize the circuit, which implies less sources of circuit noise and also easier and cheaper implementation for pre-filter **207**. In another embodiment, analog filter function PF(s) is the optimized analog filter function that optimizes the cost C described in Equation 10 for one cable length where that length is the maximum targeted cable length. Parameter V_{c }can be adapted, then, to shorter cable lengths.

To minimize the peak magnitude of the filter structure H_{PF}(s), two stages of filter structures, namely pre-filter transfer function H_{PF}(s) equals H_{PF}(s)=H_{1}(s)H_{2}(s) where H_{1}(s) and H_{2}(s) are the respective transfer functions for a pair of cascaded analog filters, can be utilized. In this case,

*H* _{1}(*s*)=(1*−V* _{c1})+*V* _{c1}PF(*s*), (15)

and

*H* _{2}(*s*)=(1*−V* _{c2})+*V* _{c2}PF(*s*). (16)

For example, analog filter function PF(s) could be a one-zero two-poles filter with the zero at 30 MHz and complex-conjugate pair poles at 70 MHz with a damping factor of 0.4. That is, zero frquency ω_{z }equals 60π×10^{6 }radians/sec., pole frequency ω_{n }equals 140π×10^{6 }radians/sec., and damping factor δ equals 0.4 in Equation 14 above. A cascade of filter transfer functions H_{1}(s) and H_{2}(s) each with the above PF(s) analog function can provide good partial equalization for a wide range of cable lengths.

In one embodiment, the digital equalizer transfer function H_{EQ}(z) executed by equalizer **212** can be expressed in the form

*H* _{EQ}(*z*)=*c* _{−1} *z+c* _{0} *+c* _{1} *z* ^{−1} *+c* _{2} *z* ^{−2} *+ . . . +c* _{K} *z* ^{−K} (17)

The first two coefficients c_{−1 }and c_{0 }can be fixed (i.e., coefficient update **214** does not alter coefficient c_{−1 }or c_{0}). For example, the first two equalizer coefficients can be set at c_{−1 }equal to −1/8 and c_{0 }equal to 1. The remaining equalizer coefficients c_{1 }through c_{K }are adaptively chosen by coefficient update **214**. The parameter K can be any positive integer. For a fixed (non-adaptive) analog filter, equalizer coefficient c_{1 }decreases monotonically with cable length. Therefore, equalizer coefficient c_{1 }is a good indicator of cable length. Additionally, AGC gain g is also a good indicator of cable length. Equalizer coefficient c_{1 }or gain g can be compared to a threshold Th_{AEQ }and the result of that comparison used to adapt analog pre-filter **207**.

In **217** executes an updating algorithm with equalizer coefficient c_{1 }in order to choose adaptive parameters for analog pre-filter **207**. In phase detector **217**, a phase detection parameter PD_{AEQ }can be calculated by

PD_{AEQ}=−(*c* _{1 −Th} _{AEQ}).

The amount of threshold TH_{AEQ }determines how much equalization is performed in analog pre-filter **207** and how much is performed in digital equalizer **212**. In one example, coefficient c_{1 }varies between about −0.35 to about −1.0 and threshold TH_{AEQ }is chosen to be about −0.4.

Phase detector **217** operates to control pre-filter parameter V_{c}. In a cascading prefilter, phase detector **217** controls any number of adaptive analog filter parameters V_{c1 }through V_{cN }where N is the total number of cascaded analog prefilters included in analog pre-filter **207**. One method of adaptively choosing a value for parameter V_{c }(or each of parameters V_{c1 }through V_{cN}) is to increment or decrement the value of V_{c }based on whether the calculated phase detection parameter PD_{AEQ }is positive or negative. Alternatively, phase detector **217** may include an accumulator that inputs the calculated parameter PD_{AEQ }and outputs a signal that controls parameter V_{c}.

Additionally, in receiver (digital filter) **208** of **220** and analog amplifier **222** scale the input signal to analog pre-filter **207**, and thus input signal Z_{s}(ω) to digital filter **208**, so that the entire dynamic range of ADC **210** is utilized while keeping the probability of saturation very low. Analog AGC **220** inputs the signal output of ADC **210**.

Analog AGC **220** outputs a signal to amplifier **222** which adjusts the output level of pre-filter **207** to optimize the functionality of ADC **210**. In one embodiment, AGC **220** calculates a phase detector parameter PD_{AGC }for the loop, accumulates the results of the phase detect parameter calculation, and converts the accumulated phase detector parameter to an analog signal which is input by pre-filter **207**. Phase detector parameter PD_{AGC }for this loop can be defined as

PD_{AGC} *[k]=α* _{k,1}+α_{k,2}, (19)

where

Variable α_{k }is the output signal from ADC **210** during time period k, i.e., at time instant t equal to kT, and modulus number N is chosen to make use of the range of ADC **210**.

At the convergence of the phase loop in AGC **220**, i.e., the steady-state condition, the expected value of PD_{AGC }is 0. This ensures that the probability of |α_{k}| being greater than Th_{AGC }is 1/N for any time period k. The threshold value Th_{AGC }and modulus number N are suitably chosen to make good use of the A/D range. For the application of Gigabit Ethernet, Th_{AGC }and N are chosen such that the probability of saturation of ADC **210** is less than about 10^{−6}. In one example, Th_{AGC }is about 0.8 of the range of ADC **210**, for example, 50 in a 7 bit ADC, and N is about 1024.

In general, pre-filter **207** can be arranged to reduce or eliminate the intersymbol interference inherent in any length cable. Once a transfer function, such as that given in Equation 12 or 14, is determined for a particular configuration of transmission channel **201**, one skilled in the art of filter design can construct the appropriate filter. Therefore, a transfer function such as that shown in Equation 12 or 14 completely describes an analog filter which can be utilized for equalization in pre-filter **207**.

As shown in _{s}(ω) , which is the input symbol sequence {a_{k}} distorted by the transmission channel and filtered by pre-filter **207** in the above described fashion, is input to digital receiver **208**. Anti-aliasing filter **209** receives analog signal Z_{s}(ω) from analog pre-filter **207**. In most embodiments, anti-aliasing filter **209** is an analog low pass filter.

Analog-to-digital converter **210** is coupled to receive an output signal from anti-aliasing filter **209**. ADC **210** can have any accuracy, but in most embodiments a six to eight bit converter is utilized. Due to pre-filter **207**, the linearity, i.e., number of bits, requirement of ADC **210** is reduced. For example, by using a 50-meter cable (CAT-5) plus transmit shaping, as described above, the ADC requirements can be significantly reduced if receiver **206** includes a pre-filter implementing the transfer function described by Equation 8. The requirements of ADC **210** may be reduced from an 8-bit ADC to a 6-bit ADC at 125 megasamples per second, for example.

By reducing the linearity of the ADC requirements, a linear equalizer is used in one embodiment rather than a decision feedback equalizer or a more complicated trellis decoder. In addition, by using pre-filter **207**, critical timing loops normally associated with Gigabit receiver designs are eliminated. Experiment has shown that the time complexity of the critical path required to implement a 4D, 8-state trellis decoder in a Gigabit receiver is reduced. The reduction in complexity inherent in reducing the distortion in the signal input to digital receiver **208** can result in receivers having fewer components and simpler implementations.

A discrete-time model of the response of transmission channel **201** in combination with pre-filter **207** is shown in **204**, represented by the channel function f(z), and a noise adder **205**. Noise adder **205** represents addition of a random noise factor n_{k }to the transmitted signal. The discrete-time model is particularly applicable for digital receiver **208**. In that case, transfer function f(z) is a folded spectrum of the combined frequency response H_{PR}(z)H_{s}(ω)H_{PF}(ω)H_{co}(ω).

It is assumed that the channel model includes the effect of transmit and receive filtering. In addition, the transmission channel **201** is assumed to be linear in that two overlapping signals simply add as a linear superposition. Therefore, the channel function polynomial f(z) of channel response **204** can be defined as

*f*(*z*)=*f* _{0} *+f* _{1} *z* ^{−1} *+f* _{2} *z* ^{−2} *+ . . . +f* _{N} *z* ^{−N}, (22)

where f_{0}, . . . , f_{j}, . . . , and f_{N }are the polynomial coefficients representing the dispersed component of the (k−j)th symbol present in the a_{k}th symbol a_{k}, z^{−1 }represents a one-symbol period delay, and N is a cut-off integer such that f_{j }for j>N is negligible. The polynomial f(z) represents the frequency response of transmission channel **201** in combination with pre-filter **207**. See A. V. OPPENHEIM & R. W. SCHAFER, DISCRETE-TIME SIGNAL PROCESSING 1989.

The noiseless output signal x_{x }of transmission channel **201** at sample time k, i.e., the output signal from channel response **204**, is then given by

*x* _{k} *=f* _{0} **a* _{k} *+f* _{1} **a* _{k−1} *+ . . . f* _{N} **a* _{k−N} (23)

Thus, the channel output signal at time k depends, not only on transmitted data at time k, but also on past values of the transmitted data, i.e., there remains some intersymbol interference.

The noise element of the input signal, represented by noise adder **205**, is represented by the sequence {n_{k}}. Therefore, the noisy output of the channel, i.e., the output signal from ADC **210**, is given by

α_{k} *=x* _{k} *+n* _{k}, (24)

where the noise samples (n_{k}) are assumed to be independent and identically distributed Gaussian random variables (See E. A. LEE AND D. G. MESSERCHMITT, DIGITAL COMMUNICATIONS (1988)) with variance equal to σ^{2}.

Digital amplifier **211** amplifies the output signal a_{k }from analog-to-digital converter **210** to adjust for the loss of signal resulting from the transmission through transmission channel **201** and pre-filter **207**. Equalizer **212** equalizes the amplified version of signal α_{k }to produce equalized signal a_{k}′ as indicated in

Equalizer **212** can be any type of equalizer including a linear equalizer, a decision feedback equalizer, or a sequence detector, alone or in combination. Examples of equalizers applicable to 100 or 1000 BASE-T Ethernet over category-5 wiring, 24 gauge twisted copper pair, are discussed in U.S. patent application Ser. No. 08/974,450, filed Nov. 20, 1997, Raghavan, assigned to the same assignee as the present application, now U.S. Pat. No. 6,083,269, herein incorporated by reference in its entirety; and U.S. patent application Ser. No. 09/020,628, filed Feb. 9, 1998, Raghavan, assigned to the same assignee as the present application, now U.S. Pat. No. 6,115,418, herein incorporated by reference in its entirety.

Further examples of equalization systems are described in U.S. patent application Ser. No. 09/296,086, filed Apr. 21, 1999, Raghavan et al., assigned to the same assignee as the present application, now U.S. Pat. No. 6,418,172 B1, herein incorporated by reference in its entirety; U.S. patent application Ser. No. 09/151,525, filed Sep. 11, 1998, Raghavan, assigned to the same assignee as the present application, now U.S. Pat. No. 6,415,003 B1, herein incorporated by reference in its entirety; U.S. patent application Ser. No. 09/161,346, filed Sep. 25, 1998, Raghavan et al., assigned to the same assignee as the present application, now U.S. Pat. No. 6,438,163 B1, herein incorporated by reference in its entirety; and U.S. patent application Ser. No. 09/560,109, filed Apr. 28, 2000, Sallaway et al., assigned to the same assignee as the present application, now U.S. Pat. No. 7,050,517 B1, herein incorporated by reference in its entirety.

Slicer **213** receives signal stream {a_{k}′} from equalizer **212** and, based on that stream {a_{k}′}, decides on an output symbol stream {â_{k}}. The output symbol stream {â_{k}} represents the best estimate of receiver **208** of the symbol stream {a_{k}} that was originally transmitted by transmitter **221**.

Receiver **208** may be an adaptive receiver, further including coefficient update **214** that adjusts the coefficient parameters of equalizer **212** in order to optimize the performance of receiver **208**. Receiver **208** may also include automatic gain control (AGC) **215** that dynamically adjusts the gain of amplifier **211** in order to maximize the efficiency of receiver **208**. Furthermore, clock recovery **216** can provide timing and framing for analog-to-digital converter **210**, representing an element of a phase-locked loop.

**506** according to the present invention. Receiver **506** includes pre-filter **207**, anti-aliasing filter **209**, analog-to-digital converter **210**, amplifier **211**, and digital equalizer **212**. Although digital equalizer **212** can be any equalizer system, as has been previously described, digital equalizer **212** in **511** coupled in series with a trellis decoder **512**. Equalizer systems are described in U.S. patent application Ser. Nos. 08/974,450, 09/020,628, 09/161,346, 09/296,086, 09/151,525, and 09/560,109, all cited above, will not be further discussed here.

Receiver **506** also includes adaptive coefficient update **214** which adaptively chooses the operating parameters of equalizer **511**, gain control **215** which adaptively chooses the gain setting of amplifier **211**, and clock recovery **216** which forms the phase-locked-loop required to frame the data acquisition by analog-to-digital converter **210**.

Receiver **506** can further include a baseline wander correction circuit **510** that, when combined with adder **515**, corrects the output signal α_{k }of analog-to-digital converter **210** for signal wander. Baseline wander correction is further described in U.S. patent application Ser. No. 09/151,525, cited above. Receiver **506** can also include an A/D reference adjuster **517**, which adjusts the reference voltage of analog-to-digital converter **210** according to the measured apparent length of the cable associated with transmission channel **201**.

Receiver **506** can include a cable quality and length calculator **518**. As described in U.S. patent application Ser. No. 09/161,346, cited above, cable quality and length calculator **518** calculates the length of cable in transmission channel **201** and the quality of transmission channel **201** based on the gain calculation of gain control **215** or the equalizer coefficients of equalizer **511**. Both A/D reference adjuster **517** and cable quality and length calculator **518** are affected by pre-filter **207**, which has the effect of simultaneously making transmission channel **201** appear to be of very high quality and to make the cable length of transmission channel **201** appear longer. The apparent quality increases because pre-filter **207** removes some of the interference caused by transmission channel **201**. The cable appears longer if there is any loss of signal strength in pre-filter **207**. Cable quality and length calculator **518** can, however, adjust for the presence of pre-filter **207** in order to have accurate calculations of cable length and quality.

Receiver **506** can also include an echo canceller **513** and a NEXT canceller **514**. NEXT canceller **514** cancels interference on one transmission line based on the transmission of symbols over neighboring lines. Echo canceller **513** cancels interference from symbols transmitted by a transmitter (not shown) associated with receiver **506**.

In some transmission systems, signals are transmitted over a cable having multiple wires. Transmission channel **201** and receiver **506** represent detection of the transmitted signal over one of the multiple wires. In that case, signals on neighboring wires affect the transmitted signal on transmission channel **201**. NEXT canceller **514** computes the influence of transmitted signal from other pairs of wires at the input of adder **519**. The projected influence from symbols transmitted on neighboring lines is subtracted from the digitized symbol by adder **519**.

Echo canceller **513** subtracts the influence of symbols that are reflected back into receiver **506** by transmission along a cable associated with transmission channel **201**. In most transceiver systems, receiver **506** and a transmitter (not shown) are coupled to a common host. The transmitter transmits signals through transmission channel **201** to a receiver counterpart (not shown) of transmitter **221**. Some of that transmitted signal may be reflected back into receiver **506**. Echo canceller **513** projects the reflected signal based on the transmitted signals and subtracts the influence of that signal at adder **516** and adder **519**.

**207** that is sensitive to the cable length of transmission channel **201**. Pre-filter **207** as shown in **520**-**1** through **520**-N. Pre-filters **520**-**1** through **520**-N execute transfer functions H_{PF} ^{1}(ω) through H_{PF} ^{N}(ω), respectively. Each of pre-filters **520**-**1** through **520**-N is optimized to counter the interference from a transmission channel having a particular cable length. Each pre-filter **520**-*i *can be designed by minimizing a cost function such as that shown in Equation 10. A selector **521**, in response to the cable length L calculated by cable quality and length calculator **518** (**520**-**1** through **520**-N. Selector **521** controls a switch **522** which supplies input signal Y_{s}(ω) to the selected one of pre-filters **520**-**1** through **520**-N. Therefore, pre-filter **207** can be selected in order to optimize the performance of receiver **506**.

**207** according to the present invention. Pre-filter **207** of _{s}(ω) is input to block **525**, which executes the transfer function PF(s). Transfer function PF(s) can, for example, be the transfer function of Equation 14. The input signal Y_{s}(ω) is also input to block **526** which executes the transfer function one. The output signal from block **525** is multiplied by the adaptively chosen parameter V_{c }in multiplier **527** and input to adder **529**. The output signal from block **526** is multiplied by 1−V_{c }in multiplier **218** and added to the output signal from multiplier **527** by adder **529**. The output signal from adder **529** is the output signal Z_{s}(ω) from pre-filter **207**.

**600** according to the present invention. Transmission receiver **600** receives input analog signal streams {y_{k} ^{(1)}} through {y_{k} ^{(M)}} from M wires **603**-**1** through **603**-M, respectively. Signal streams {Y_{k} ^{(1)}} through {Y_{k} ^{(M)}} are also indicated as input signals Y_{s} ^{(1)}(ω) through Y_{s} ^{(M)}(ω), respectively, in _{s} ^{(i)}(ω) is the Fourier transform of receiver input analog signal y_{k} ^{(i) }for integer i running from 1 to M. Each of input signals Y_{s} ^{(1)}(ω) through Y_{s} ^{(M)}(ω) includes the effects of a transmission channel **601**, as described above for transmission channel **201**. Additionally, each of signals Y_{s} ^{(1)}(ω) through Y_{s} ^{(M)}(ω) includes effects of cross talk between wires so that, for example, signal Y_{s} ^{(i)}(ω), where the ith wire **603**-i is an arbitrary one of wires **603**-**1** through **603**-M, includes a contribution from signals on all of the other wires, i.e., wires **603**-**1** through **603**-(*i−*1) and wires **603**-(*i+*1) through **603**-M.

Individual receivers **602**-**1** through **602**-M receive input signals Y_{s} ^{(1)}(ω) through Y_{s} ^{(M)}(ω), respectively, i.e., input analog signal streams {y_{k} ^{(1)}} through {y_{k} ^{(M)}}, respectively, and generate output signal streams {a'_{k} ^{(1)}} through {a'_{k} ^{(M)}}, respectively. In some embodiments, signal streams {a′_{k} ^{(1)}} through {a′_{k} ^{(M)}}are input to slicers (not shown in **602**-**1** through **602**-M, respectively. The slicers in receivers **602**-**1** through **602**-M, determine symbol streams {â′_{k} ^{(1)}} through {â′_{k} ^{(M)}}(also not shown in **602**-**1** through **602**-M. Symbol streams {á_{k} ^{(1)}} through {á_{k} ^{(M)}} here are temporary decisions made in order to control the adaptation of parameters within receivers **602**-**1** through **602**-M, respectively.

An arbitrary receiver **602**-*i*, which is one of receivers **602**-**1** through **602**-M, also inputs the output symbol streams, {Tx_{k} ^{(1)}} through {Tx_{k} ^{(M)}}, from a transmitter **606** associated with receiver **600**. Each of receivers **602**-**1** through **602**-M can then include echo cancellation and near end crosstalk (NEXT) cancellation due to the transmitted symbols of transmitter **606**. As indicated in _{k} ^{(i)}} is also supplied on corresponding wire **603**-*i *to transmission channel 601.

In some embodiments, receiver output signal streams {a′_{k} ^{(1)}} through {a′_{k} ^{(M)}} are input to a delay skew compensator **604**. **604** provides output signal streams, also denoted as {a′_{k} ^{(1)}} through {a′_{k} ^{(M)}} here, that are input to a multi-dimensional (M-D) decoder **605** for final decision on the received symbols.

Delay skew compensator **604** aligns the M signal streams {a′_{k} ^{(1)}} through {a′_{k} ^{(M)}} , i.e., compensator **604** aligns signals a′_{k} ^{(1) }through a′_{k} ^{(M) }at each time period (or clock cycle) k, so that any delays between signal streams {a′_{k} ^{(1)}} through {a′_{k} ^{(M)}} received from receivers **602**-**1** through **602**-M, respectively, are removed. Relative delays between signal streams {a′_{k} ^{(1)}} through {a′_{k} ^{(M)}} may be introduced in transmission channel 601 or by receivers **602**-**1** through **602**-M. The aligned signals a′_{k} ^{(1) }through a′_{k} ^{(M) }from delay skew compensator **604** for particular clock cycle k arrive at M-D decoder **605** simultaneously.

Decoder **605**, which may be a Viterbi decoder, uses aligned signal streams a′_{k} ^{(1) }through a′_{k} ^{(M) }to make a final decision on the incoming data. The final decision of decoder **605** is indicated in _{k} ^{(1) }through â′_{k} ^{(M) }.

Additionally, decoder **605** may utilize an error detecting code such as that defined in the IEEE standard for Gigabit Ethernet. See, e.g., IEEE 802.3ab, “Gigabit Long Haul Copper Physical Layer Standards Committee”, 1997 Standard. In one embodiment, M-D decoder **605** is a Viterbi decoder which makes a final decision on data which has been encoded by an 8-state Ungerboeck code, as described in the IEEE Gigabit Spec. The Viterbi decoder in this embodiment is a maximum likelihood sequence estimator, as described in Viterbi, A.J., “Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,” IEEE Trans. Inf Theory, IT-13, pages 260-269, April 1967, herein incorporated by reference in its entirety. M-D decoder **605**, therefore, maximizes the probability of correctly estimating the entire sequence of symbols.

**602**-*i *that includes an analog prefilter **619** and a digital filter **620**. Analog prefilter **619** includes a DC offset adder **610** coupled to a DC offset correction circuit **628**, an echo canceller adder **611** coupled to an analog echo canceller circuit **627**, an analog multiplier **612** coupled to analog automatic gain control circuit **220**, and analog equalizers **613** and **614** coupled to analog equalizer adaptor circuit (phase detector) **217**. Digital filter **620** includes digital equalizer **212**, a digital echo/NEXT canceller adder **615** coupled to a digital echo canceller **621** and to NEXT cancellers **618**-**1** through **618**-M without a canceller **618**-*i*, AGC booster (digital amplifier) **211** coupled to digital automatic gain control circuit **215**, a baseline wander substracter (or adder) **616** coupled to a baseline wander correction circuit **617**, and slicer **213**. Analog portion **619** is coupled to digital portion **620** through analog-to-digital converter **210**. For exemplary purposes, slicer **213** is shown as a PAM-5 decoder. Timing recovery loop (clock recovery) **216** controls a clock used in both the analog and digital portions of receiver **602**-*i *and calculates the timing phase parameter τ_{k} ^{(i)}.

Slicer **213** provides a temporary decision â_{k} ^{(i) }on the kth symbol a_{k} ^{(i) }intended to be transmitted in signal stream {y_{k} ^{(i)}} on wire **603**-*i *and (b) an error e_{k} ^{(i) }based on input signal a'_{k} ^{(i)}, where error e_{k} ^{(i) }is defined as

*e* _{k} ^{(i)} *=a'* _{k} ^{(i)} *−â* _{k} ^{(i)}. (25)

The temporary decision â_{k} ^{(i) }and error e_{k} ^{(i) }are utilized in various circuit loops in receiver **602**-*i *in order to adapt parameters in receiver **602**-*i*. As discussed below and indicated in _{k} ^{(i) }and error e_{k} ^{(i) }are also utilized to adapt parameters in analog prefilter **619**.

DC offset correction circuit **628** includes an ADCO control **633** coupled to a digital-to-analog converter (DAC) **634**. DAC **634** provides a signal which is negatively added to the received signal Y_{s} ^{(i)}(ω), in DC offset adder **610**. ADCO control **633** inputs the output signal α_{k} ^{(i) }from ADC **210** and estimates the DC offset that occurs in analog prefilter **619**. This calculated DC offset, upon being converted from digital to analog from by DAC **634**, is then subtracted from the input signal Y_{s} ^{(i)}(ω) in adder **610**.

Analog echo canceller circuit **627** includes an AEC control **629**, DACs **630** and **631**, and an RC circuit **632**. AEC control **629** inputs the error signal e_{k} ^{(i) }as well as the transmitted symbol stream {Tx_{k} ^{(i)}} on wire **603**-*i *(_{k} ^{(i) }and capacitance C_{k} ^{(i) }in RC circuit **632**. Transmit signal Tx_{k} ^{(i) }is filtered in RC circuit **632**. Echo adder **611** substracts the resultant filtered signal from input signal Y_{s} ^{(i)}(ω) minus the DC offset determined by DC offset correction circuit **628**. The parameters R_{k} ^{(i) }and C_{k} ^{(i) }are adapted to approximately duplicate the effects of the transmit signal Tx_{k} ^{(i) }on the signal input to adder **611**. Appropriate values for R_{k} ^{(i) }and C_{k} ^{(i) }minimize the residual echo from the transmit signal Tx_{k} ^{(i)}, which results in minimizing the requirements of digital echo canceller circuit **621**. Furthermore, by minimizing the residual echo, analog AGC **220** can provide for maximum boost to input signal Y_{s} ^{(i)}(ω)through multiplier **612** without overloading ADC **210**, which results in clipping. The additional boost at multiplier **612** results in a lessened need for amplification at digital AGC booster **211**, thereby minimizing quantization noise.

Analogous to what occurs in receiver **206** of **220** outputs a gain signal to multiplier **612** that adjusts the output levels of prefilter **619** to optimize the functionality of ADC **210**. Analog gain control circuit **220** contains AGC control circuit **625** and DAC **626**. **220**, specifically embodiments of AGC control circuit **625**.

One embodiment of an AGC control circuit **625** is shown in **630** compares signal α_{k} ^{(i) }with threshold TH_{AGC }and calculates, for each receiver **602**-*i*, value α_{k,1 }according to Equation 20. The value α_{k,2 }is calculated according to Equation 21. The value of PD_{AGC }is calculated according to Equation 19 in adder **631**. The value of PD_{AGC }is input to an adder **632**. The output signal of adder **632** goes to saturation block **633**. Saturation block **633** saturates at, for example, 13 bits. The output from saturation block **633** is delayed one clock cycle and added to PD_{AGC }at adder **632**. The combination of adder **632**, saturation block **633**, and delay **635** forms an accumulator.

The output signal of saturation block **633** is right shifted by a particular number of bits, for example 7 bits, in shifter **634** to give an output signal of a particular number of bits, for example, 6 bits. The output signal from shifter **634** provides an input signal to DAC **626**. Multiplier **612** multiplies the analog output signal from DAC **626**, which is the output signal from analog AGC control circuit **220** (_{s} ^{(i)}(ω) as modified by the subtractions at adders **610** and **611**.

Because of the low frequency nature, the input signal to DAC **626** of AGC **220** has very small variations from sample to sample. In most cases, the variation is at most one count. **220** (AGC control **625** and DAC **626**) that takes advantage of this feature. Instead of a “general purpose” 6 bit D/A, a less expensive Sigma-Delta D/A is used for DAC **626** in the embodiment of **633** is replaced with a smaller block **636** of size, for example, 7 bits. The accumulated value, i.e., the output signal from the accumulator formed by adder **632**, block **636** and delay **635**, is wrapped around (modulo) to a particular number of bits, for example 7 bits.

The output of block **636** is a three-level signal representing overflow, no change, or underflow of the accumulation value. The three-level signal is the output signal received by DAC **626** implemented as a Sigma-Delta DAC. DAC **626** then outputs an analog value which multiplier **612** multiples by the input signal Y_{s} ^{(i)}(ω) again as modified by the subtractions at adders **610** and **611**.

In the embodiment shown in **613** cascaded with analog equalizer **614**. Each of analog equalizer **613** and analog equalizer **614** is controlled by analog equalizer control circuit (phase detector) **217**. Analog equalizer control circuit **217** includes AEQ control **622** coupled to DAC **623**, which is coupled to control analog equalizer **613**, and coupled to DAC **624**, which is coupled to control analog equalizer **614**. Analog equalizers **613** and **614** accomplish partial equalization of the input signal Y_{s} ^{(i)}(ω), resulting in a lessened requirement for digital equalization. Analog equalizers **613** and **614** and analog equalization control circuit **217** operate as is described above in connection with Equations 14 through 18.

Analog-to-digital converter **210** receives the output signal Z_{s} ^{(i)}(ω) from analog prefilter **619** and digitizes the signal. The output from ADC **210** is signal α_{k} ^{(i)}.

ADC **210** samples input signal Z_{s} ^{(i)}(ω) based upon the clock output from timing recovery loop (clock recovery) **216** and phase τ_{k} ^{(i)}. Clock recovery **216** recovers the frequency of the received signal (i.e., the frequency of transmitter **221** (_{k} ^{(i) }of the incoming signal. For a constant clock frequency offset between the remote transmitter's digital-to-analog converter and ADC **210**, the optimal timing phase τ varies linearly with time. The rate of change of phase τ_{k} ^{(i) }is proportional to the clock frequency offset.

Clock recovery **216** can be a second order loop. One embodiment of clock recovery **216** is shown in **650** estimates the difference between the optimal phase τand the current value of τ_{k} ^{(i) }based on the output symbol â_{k} ^{(i) }and the error calculation e_{k} ^{(i)}. The output signal PD_{CR }from phase detector **650** for receiver **602**-*i *can be determined in several manners, including a slope method and a Mueller & Muller (M&M) method. In the M&M method, the output signal PD_{CR }from phase detector **650** is

PD_{CR} *=e* _{k−1} ^{(i)} *â* _{k} ^{(i)} *−e* _{k} ^{(i)} *â* _{k−1} ^{(i)}. (26)

In the slope method,

PD_{CR} *=e* _{k} ^{(i)}slope(*k*), (27)

where

The output signal PD_{CR }from the phase detector **650** is input to a loop filter **651** that has a proportional part and an integral part. The output signal from loop filter **651**, indicating the correction on the clock frequency, is input to a frequency controlled oscillator **652** which causes ADC **210** to sample at an optimal phase by controlling the sampling frequency of ADC **210**. Frequency controlled oscillator **652**, in other words, outputs a clock signal whose zero-crossings are given by NT+τ_{k} ^{(i)}.

If the coefficient c_{−1 }of digital equalizer **212** is adapted, the adaptation algorithms between coefficient update **214** and clock recovery **216** will interact adversely, often causing failure of receiver **600**. To prevent this interaction, coefficient c_{−1 }is fixed, for example, at −⅛, in order that the timing loop can converge to an optimum phase.

Since part of the equalization is accomplished in analog equalizers **613** and **614**, digital equalizer **212** can be simplified. For example, digital equalizer **212** can be a linear equalizer without causing large amounts of noise enhancement. Of course, as has been previously discussed, other embodiments of digital equalizer **212** can use any equalization scheme.

High frequency signals are attenuated more by transmission channel **601** than are low frequency signals. The equalization, between analog equalizers **613** and **614** and digital equalizer **212**, then should equalize the attenuation difference across the frequency band.

In one embodiment, digital equalizer **212** in each receiver **602**-*i * **212** is a linear equalizer executing the transfer function H^{(i)} _{EQ}(z) given as

The parameter K can be any positive integer, for example, in some embodiments. The coefficient c^{(i)} _{k, −1 }can be fixed, for example, at −⅛, to avoid interaction with the adaptation performed by timing recovery loop **216**. Further, the coefficient c^{(i)} _{k,0 }can be fixed, for example, at 1, to avoid interaction with digital AGC **215**. The remaining equalizer coefficient c^{(i)} _{k,1 }through c^{(i)} _{k,K }are adaptively chosen by coefficient update **214**. Equalizer transfer function H^{(i)} _{EQ}(z) of Equation 29 corresponds to equalizer transfer function H_{EQ}(z) of Equation 17 with each coefficient c^{(i)} _{k,j }of Equation 29 replacing corresponding coefficient c_{j }of Equation 17.

Coefficient update **214** can use a least mean squares (LMS) technique to continuously adjust the equalizer coefficients c^{(i)} _{k,j }such that

*C* ^{(i)} _{k+1,j=c} ^{(i)} _{k,j}−μ^{(i)} _{EQ, j}sign(α^{(i)} _{k−j)e} ^{(i)} _{k}. (30)

The LMS technique minimizes the mean squared error, which is a function of intersymbol interference and random noise, of the input signal at slicer **213**. The parameter μ_{EQ,j} ^{(i) }controls the rate at which the coefficient c_{k,j} ^{(i) }changes. In some embodiments, the parameter μ_{EQ,j} ^{(i) }is set to about 10^{−3 }on chip powerup and reduced to about 10^{−5 }for continuous operation.

After equalization with digital equalizer **212**, digital echo canceller **621** removes the residual echo due to transmitter **606** transmitting on wire **603**-*i *which is left by analog echo canceller circuit **627**. The M-**1** NEXT cancellers **618**-**1** through **618**-M remove the near end crosstalk (NEXT) from transmitter **606** on wires **603**-**1** through **603**-M, respectively, other than wire **603**-*i*. In a four-wire system (M=4), there are three NEXT cancellers **618**-**1** through **618**-M except for **618**-*i *and one echo canceller **621** for signals transmitted on wire **603**-*i. *

Digital echo canceller **621** cancels the residual echo not cancelled by analog echo canceller circuit **627**. The bulk of the echo cancellation is accomplished by analog echo canceller circuit **627**. Removing the residual echo by digital echo canceller **621** is necessary to achieve the bit-error rate (BER) performance of receiver **602**-*i. *

In one embodiment, echo canceller **621** uses a finite-impulse response (FIR) filter to estimate the residual echo on the channel. FIR echo canceller **621** executes a transfer function EC^{(i)} _{k }given by

where L is an integer, for example, 64 and 56. Echo canceller **621** inputs the transmitted symbol stream {Tx_{k} ^{(i)}} and estimates the residual echo at that point in the data path, including the impulse response of the residual echo channel after analog echo canceller **627**, analog AGC **625**, analog equalizers **613** and **614**, and digital equalizer **212**.

Each of the coefficients ζ^{(i)} _{k,j }in Equation 31 is chosen by an adaptation loop using a least mean squares technique such that

ζ^{(i)} _{k+1,j=ζ} ^{(i)} _{k,j−μ} ^{(i)} _{EC,jsign(} *Tx* ^{(i)} _{k−j)e} ^{(i)} _{k}. (32)

The coefficients ζ_{k+1,j} ^{(i) }are continuously adjusted to maintain the minimum mean squared error at slicer **213**. The parameter μ_{EC,j} ^{(i) }may initially be set high (e.g., 10^{−3}) and then lowered (e.g., 10^{−5}) for continuous operation.

As mentioned above, the M-1 NEXT cancellers **618**-**1** through **618**-M in receiver **602**-*i *cancel the near end crosstalk which is a result of transmitter **606** transmitting on wires **603**-**1** through **603**-M other than wire **603**-1. Note that there is no NEXT canceller (**618**-*i *) for receiver **602**-*i *because the effects of transmitting symbols on wire **603**-*i *are cancelled by analog echo canceller **627** and digital echo canceller **621**. Each of the M-1 NEXT cancellers **618**-**1** through **618**-M estimates the impulse response from the NEXT in an FIR block. The impulse response that is used to estimate the NEXT at this point in the data path is the impulse response of the NEXT contribution in transmission channel **601** that has been added to the receive signal filtered by analog prefilter **619** and digital equalizer **212**. Each of the M-1 NEXT cancellers **618**-**1** through **618**-M executes a transfer function NE^{(i)} _{p,k }given by

where p denotes a channel that is not channel i and L can be any positive integer, for example, 44 or 16.

Each of the coefficients ξ^{(i)} _{p,k,l }is adaptively chosen according to a least mean squares technique such that

ξ^{(i)} _{p,k+1,j=ξ} ^{(i)} _{p,k,j+μ} ^{(i)} _{NE,p,j}sign(*Tx* ^{(p)} _{k−j})*e* ^{(i)} _{k}. (34).

The coefficients ξ^{(i)} _{p,k,j }are continuously updated to maintain the minimum mean squared error at slicer **213**. The parameter μ^{(i)} _{NE,p,j}may initially be set high (e.g., ˜10^{−3}) and then lowered (e.g., ˜10^{−5}) for steady state operation.

The echo and NEXT estimations performed by echo canceller **621** and the M-1 NEXT cancellers **618**-**1** through **618**-M are subtracted from the output signal of equalizer **212** by adder **615**.

Digital AGC **215** inputs a gain signal g_{k} ^{(i) }to AGC booster **211** which digitally amplifies the output signal from adder **615**. The signal is boosted by AGC booster **211** to levels determined by slicer **213**. The gain g_{k} ^{(i) }is set to counter the losses resulting from transmission channel **601** and not recovered in analog prefilter **619**. During acquisition, the gain g_{k} ^{(i) }can be updated by the equation

*g* ^{(i)} _{k+1=g} ^{(i)} _{k−μ} ^{(i)} _{AGC}(*e* ^{(i)} _{non,k}). (35)

with error e^{(i)} _{non,k }determined from

*e* ^{(i)} _{non,k=|a'} ^{(i)} _{k}(i)|−TH^{(i)} _{AGC}. (36)

where TH^{(i)} _{AGC }is the average absolute value of a'^{(i)} _{k}. The parameter μ^{(i)} _{AGC }can initially be set high and then lowered during steady state operation. During steady state operation, a least mean squares approach can be taken, in which case

*g* ^{(i)} _{k+1=g} ^{(i)} _{k−μ} ^{(i)} _{AGC}sign(*â* ^{(i)} _{k})*e* ^{(i)} _{k}. (37)

Finally, baseline wander correction circuit **617**, in combination with baseline wander subtracter **616**, corrects for baseline wander. A discussion of baseline wander can be found in U.S. patent application Ser. No. 09/151,525, cited above.

One skilled in the art will recognize that the components of receiver **506** may be arranged differently. For example, in **211** follows equalizer **212** while in **212** follows amplifier **211**. One skilled in the art will also recognize that receivers according to the present invention may not have some of the features shown in **5**A, and **6**B or, alternatively, may have other features not shown in **5**A, and **6**B. **5**A, and **6**B, therefore, are not exhaustive of all configurations of receivers that are nonetheless within the scope of this disclosure.

The above examples, therefore, are demonstrative only. One skilled in the art can recognize variations which fall within the scope of this invention. As such, the invention is limited only by the following claims.

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US8837066 | Apr 17, 2014 | Sep 16, 2014 | Lsi Corporation | Adaptive baseline correction involving estimation of filter parameter using a least mean squares algorithm |

US20100309970 * | May 25, 2010 | Dec 9, 2010 | Stmircoelectronics (Grenoble 2) Sas | Dvb-s2 demodulator |

US20140211839 * | Mar 28, 2014 | Jul 31, 2014 | Lsi Corporation | Receiver Having Limiter-Enhanced Data Eye Openings |

Classifications

U.S. Classification | 375/232, 375/348, 375/350 |

International Classification | H04L1/00, H04B1/10 |

Cooperative Classification | H04L25/03254, H04L25/03057 |

European Classification | H04L25/03B7E1, H04L25/03B1A7 |

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