|Publication number||US8005884 B2|
|Application number||US 11/869,426|
|Publication date||Aug 23, 2011|
|Priority date||Oct 9, 2007|
|Also published as||US20090094308|
|Publication number||11869426, 869426, US 8005884 B2, US 8005884B2, US-B2-8005884, US8005884 B2, US8005884B2|
|Inventors||Alexandru Fit-Florea, Debjit Das-Sarma|
|Original Assignee||Advanced Micro Devices, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Non-Patent Citations (2), Referenced by (3), Classifications (5), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates to computer systems, and more particularly, to finding an efficient method to achieve correct rounding for computer arithmetic.
2. Description of the Relevant Art
A computer system may comprise multiple processor cores wherein each core may have a floating-point unit to perform these arithmetic operations. The arithmetic operations may include addition, subtraction, multiplication, division and square root. The rounded result is represented by the computer system with a maximum limit of significance. Each processor core uses a finite number of bits to represent a floating-point numeric value. The finite number of bits used by a processor core is referred to as the processor core's precision. In addition, the accuracy of a floating-point value is referred to how close the processor core's representation of a numeric value is to an infinitely precise representation. It is desired to have the processor representation of the rounded result be as accurate as possible. Furthermore, a processor core may be configured to perform the floating-point arithmetic operations in more than one precision (e.g. single-precision, double-precision, or extended-precision).
A floating-point number is represented in a base number system that defines the radix of the system. For example, the decimal system with base 10 is a common base system. Modern computers use a binary system with base 2. Each base number system has a maximum number of digits that may be used to represent a number. For example, the decimal system uses ten digits, 0-9, and the hexadecimal system uses sixteen digits, 0-9 and a-f. As used herein, for simplicity sake, digits may refer to the digits of any base number system, although digits for a binary system are referred to as bits and digits for a hexadecimal system are referred to as hexadecimal digits, and so forth. Besides the base, three other entities are used to represent a floating-point number. First, the sign is a string used to represent the plus or minus sign. Second, a mantissa is a string of digits used to represent the number. The mantissa is a signed entity meaning it represents a positive or a negative number. Third, an exponent is used to record the position of the most significant digits, or the first non-zero digits, of the mantissa. The value of the floating-point number is found by multiplying the sign and mantissa by the base raised to a power set by the exponent. The floating-point number is referred to as normalized if its mantissa is zero for zero values, or, for non-zero values, its mantissa has a non-zero value in the left-most significant digit of the mantissa. For non-zero values, a non-normalized floating-point number may be normalized by, first, shifting the floating point until the left-most significant digit of the mantissa is non-zero, and, second, adjusting the exponent in order that the floating-point number represented by the above combination of mantissa, base and exponent, remains constant.
A floating-point number represented in a processor does not have an infinite number of digits in the mantissa. A register may hold the value of the normalized mantissa and it is limited to a certain number of memory storage locations, or bits. The number of bits, p, explicitly or implicitly used by a processor to represent the mantissa is referred to as the precision. The result of an arithmetic operation may require more than p bits for the representation of their respective mantissas. Therefore, it is required to find an accurate representation of such mantissas with only p bits.
Older processors truncated the extra bits beyond the most significant p bits. Modern processors perform rounding to obtain a more precise representation. For example, when rounding to the nearest machine representable number is desired, a value of one may be added to the least significant digit of the p digits of a mantissa if the digits following the p most significant digits contain a value more than one-half of the least significant digit of the p digits. When the value is less than one-half, the digits following the p most significant digits are simply truncated. When the value is equal to one-half, the action taken depends on the rounding technique being used. A common standard used for both floating-point number representation and rounding is the IEEE Standard 754 for Binary Floating-Point Arithmetic. Also, a computing system has a limit to the smallest increment or decrement of a floating-point number representation which is referred to as the unit in the last place (ulp).
Rounding methods, which may include one of a variety of algorithms, are used after the arithmetic operation is completed. Table-lookup(s) may be used to aid or complete the operation. One variable for an algorithm used in a rounding method may be the size of a table-lookup. As the size of a table-lookup increases, the accuracy of the result computed at intermediate steps increases, the number of subsequent computations decreases, but also, the die-area requirement for the table-lookup increases. An uncompressed table-lookup with a precision of 13 bits may require only half the area of a 14 bit table. However, more subsequent computations may be required due to the less accuracy of the 13-bit table-lookup. The rounding method may have conditions for the previous operations to complete prior to the use of the rounding method. For example, for division of two operands a and b, prior conditions may include the number of quotients to find (e.g., 1/b, a/b, or both) and the precision or accuracy of the quotients. Afterwards, a number of steps need to be taken to round the result of the calculation, and the number of steps may differ depending on the rounding method chosen.
Two examples of current rounding methods include the FMAC-based method, see P. Markstein, IA-64 and Elementary Functions: Speed and Precision, Hewlett-Packard®/Prentice-Hall, 2000, and the rounding used in floating-point units of AMD's K-8 microprocessors, see S. Oberman, Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor, Proceedings of the 14th IEEE Symposium on Computer Arithmetic, April 1999, pp. 106-115. The method described by Markstein requires the calculation of two quotients in parallel followed by a floating-point multiply accumulate unit (FMAC) operation for the remainder. Although this method's hardware requirements are a FMAC unit and a state machine, it requires two FMAC latencies to determine the rounded result. The K-8 method uses extra precision bits for internal calculations that are unseen to the user. The extra precision bits allows the internal calculations to have smaller bounded errors and only one remainder calculation needs to be performed. However, much extra hardware may be required for the extra precision bits such as a larger table-lookup or more die area for the multiplier circuitry.
In view of the above, an efficient method for floating-point rounding is desired.
Systems and methods for efficient floating-point rounding in computer systems are disclosed.
In one embodiment, a computer system includes one or more microprocessors with a floating-point unit (FPU). For a floating-point calculation, such as division, due to the representation of the operands and the result by registers with a finite number of bits, the real numbers may need to be rounded to the nearest accurate representation possible for the processor. In order to achieve an accurate representation in an efficient manner, the constraints for the remainder may be relaxed in order to reduce the area for look-up tables. An extra internal precision bit may be deemed unnecessary, so hardware resource growth is further reduced. Only one quotient may be calculated, rather than two, again, reducing design complexity, computation time, and die area required to perform the is rounding. Comparison logic may be required that may add a couple of cycles to the rounding computation beyond the calculation of the remainder. However, the extra latency may be much smaller than a second FMAC latency. Also, there may be hardware savings with this approach.
In one embodiment, a processor includes a floating-point unit configured to perform a calculation using operands and a lower accuracy. The unit further receives a calculated first result with the lower accuracy, wherein the first result is an approximation of an actual result. The floating point unit determines a sign and a magnitude of an error between the first result and the actual result and determines a second result to be selected from a selection of three choices including (i) the first result, (ii) the first result less one ulp and (iii) the first result added to one ulp. Finally, the second result is determined to correspond to one of the three choices, wherein the second result is a floating-point rounded quotient of a floating-point division calculation.
These and other embodiments will become apparent upon reference to the following description and figures.
While the invention is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
In the next clock cycle, memory access instructions index the d-TLB and d-cache block 130. Like the i-TLB and i-cache, there may be one or more levels of TLB and caches before access to main memory is necessary. The retirement queue 132, possibly a FIFO queue, stores the results of the instructions as they complete. Results of the instructions may be data-forwarded to other instructions prior to being written in the retirement queue. The retirement queue ensures in-order retirement by writing results of the instructions into the architectural registers 134 in their original program order.
Next, in block 406, a remainder, r, is calculated where r is represented by r=a−(b×qi). Ideally, the value should be zero, but due to the finite precision of a processor, the remainder value may be non-zero. The quotient, qi, is a floating-point number represented by the finite precision of the processor. The value of the actual quotient, qactual, represented by infinite precision lies in a range of floating-point numbers between the calculated quotient, qi, minus 1 ulp and qi plus 1 ulp. Therefore, the rounded result, which will be a floating-point number with finite precision may be one of three values: (qi−1 ulp), qi, or (qi+1 ulp). If qactual lies within +/−½ ulp of qi, then the rounded result will be qi. If qactual has a value lower than (qi−½ ulp), then the rounded result is (qi−1 ulp). Otherwise, if qactual has a value higher than (qi+½ ulp), then the rounded result is (qi+1 ulp). A brief look at block 504 of
Since the smallest increment or decrement of the processor is set by the least significant bit of the finite representation of the processor, the term, ½ ulp, relates to the number of bits, p, the processor uses in its mantissa. The comparison becomes a parallel subtraction of exponents and mantissas of r and b. The value r will not equal the value of b×(½ ulp), since the processor represents a floating-point number with precision of 1 ulp—the processor can represent, for example, the values (qi−1 ulp), qi, or (qi+1 ulp), but not values in between, such as a granularity of ½ ulp. If the remainder is positive (decision block 408) and the above condition is true (decision block 410), then qactual lies within ½ ulp to the right of qi. Thus, the rounded result should be qi as in block 412. If the condition of decision block 410 is not satisfied, then r>b×(½) ulp, which signifies (qactual−qi)>½ ulp. This derivation is similar to the derivation above. In this case, qactual lies more than ½ ulp to the right of qi. The rounded result should be (qi+1 ulp) as in block 414. Similar reasoning may be applied to decision block 416 and blocks 418 and 420 for the cases when qactual lies within ½ ulp to the left of qi and when qactual lies more than ½ ulp to the left of qi.
Block 504 provides an illustration of the rounding problem. It is known that qactual is between (f−1 ulp) and (f+1 ulp). The processor must choose which one of three rounded values, such as (f−1 ulp), f, and (f+1 ulp), it can use to represent the infinite precision result of the division calculation, qactual. Correct rounding may be performed if it is determined to which of the four ½ ulp intervals (e.g., 1, 2, 3, or 4) that qactual belongs. This is the equivalent of determining:
1. Which side of qactual is qi?
2. Is qi further than ½ ulp from qactual?
Computing the sign of the remainder, ri=a−(b×qi), only determines the correct side of q (taking care of no 1 above). This eliminates two of the four ½ ulp intervals where qactual can lay.
For condition no 2 (all values are absolute values):
if (qactual−qi<½ ulp) then:
if (qactual−q; >½ ulp) then:
mantissas of ri and b;
(exponent of r,) and (exponent of b−(p));
And the problem reduces to determining the corresponding signs:
sign of ((mantissa of ri)−(mantissa of b));
sign of ((exponent of ri)−((exponent of b)−(p)));
Block 508 of
ri>b×(½ ulp) if:
((exponent of ri)−((exponent of b)−(p)))>0,
((exponent of ri)−((exponent of b)−(p)))=0 and (mantissa of ri−mantissa of b)>0.
Otherwise, ri<b×(½ ulp).
Finally, the interval where qactual may reside:
If ri>0, and (mantissa of ri)>(mantissa of b), then qactual resides in interval 4, and rounded qi=f+1 ulp.
If ri>=0, and (mantissa of ri)<(mantissa of b), then qactual resides in interval 3, and rounded qi=f.
If ri<0, and (mantissa of ri)>(mantissa of b), then qactual resides in interval 1, and rounded qi=f−1 ulp.
If ri<0, and (mantissa of ri)<(mantissa of b), then qactual resides in interval 2, and rounded qi=f.
Block 606 illustrates the derivations similar to those discussed above in order to determine the correct rounded value to represent the actual quotient of infinite precision. Here, the number of intervals has increased and an extra comparison is needed between the remainder and the denominator. However, this extra comparison involves a subtraction with the value (p−1) and circuit and/or software techniques may be used rather than perform a separate, parallel subtraction with the value p that is already needed. Also, rather than perform all comparisons listed in block 606, in one embodiment, only the first and third comparisons may be performed in parallel. If the conditions of these comparisons are not satisfied, then it is known the second comparison is true. The final decision making that uses the results of the sign of the remainder and the comparisons between the remainder and the denominator is shown in block 608.
It is noted that the above-described embodiments may comprise software. In such an embodiment, the program instructions that implement the methods and/or mechanisms may be conveyed or stored on a computer readable medium. Numerous types of media which are configured to store program instructions are available and include hard disks, floppy disks, CD-ROM, DVD, flash memory, Programmable ROMs (PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage.
Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5568412||Nov 29, 1994||Oct 22, 1996||Goldstar Company, Limited||Rounding-off method and apparatus of floating point arithmetic apparatus for addition/subtraction|
|US5737255 *||Jun 5, 1995||Apr 7, 1998||International Business Machines Corporation||Method and system of rounding for quadratically converging division or square root|
|US5764555||Mar 13, 1996||Jun 9, 1998||International Business Machines Corporation||Method and system of rounding for division or square root: eliminating remainder calculation|
|US6205461||Sep 18, 1998||Mar 20, 2001||Ati International Srl||Floating point arithmetic logic unit leading zero count using fast approximate rounding|
|US20070162535 *||Jan 12, 2006||Jul 12, 2007||International Business Machines Corporation||Rounding floating point division results|
|1||"A Comparison of Three Rounding Algorithms for IEEE Floating-Pointmultiplication"; Even, et al.; This paper appears in Computer Arithmetic, 1999. Proceedings, 14th IEEE Symposium, pp. 225-232.|
|2||"Accelerating Correctly Rounded Floating-Point Division when the Divisor is Known in Advance"; Brisebarre, et al., IEEE Transactions on Computers, vol. 53, No. 8, Aug. 2004; pp. 1069-1072.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8775494 *||Mar 1, 2011||Jul 8, 2014||Nvidia Corporation||System and method for testing whether a result is correctly rounded|
|US20120059866 *||Sep 3, 2010||Mar 8, 2012||Advanced Micro Devices, Inc.||Method and apparatus for performing floating-point division|
|US20120226730 *||Sep 6, 2012||Alexandru Fit-Florea||System and Method for Testing Whether a Result is Correctly Rounded|
|U.S. Classification||708/497, 708/551|
|Oct 18, 2007||AS||Assignment|
Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FIT-FLOREA, ALEXANDRU;DAS-SARMA, DEBJIT;REEL/FRAME:019996/0843
Effective date: 20071004
|Feb 11, 2015||FPAY||Fee payment|
Year of fee payment: 4