|Publication number||US8017982 B2|
|Application number||US 11/761,904|
|Publication date||Sep 13, 2011|
|Filing date||Jun 12, 2007|
|Priority date||Jun 12, 2007|
|Also published as||DE112008001588T5, US8679933, US9484378, US20080308893, US20110287572, US20140191303, US20170040375, WO2008157152A1|
|Publication number||11761904, 761904, US 8017982 B2, US 8017982B2, US-B2-8017982, US8017982 B2, US8017982B2|
|Inventors||Kyle K. Kirby, Steve Oliver|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Non-Patent Citations (1), Referenced by (2), Classifications (17), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention, in various embodiments, relates generally to methods for fabricating photoimagers, such as complementary metal-oxide-semiconductor (CMOS) imagers, which are also referred to herein more simply as “imagers.” More specific embodiments of the present invention include imager fabrication methods in which transistors are fabricated on an active surface of a substrate, then contact openings, contact plugs, metallization, and contact pads are formed on and from a back side of the substrate. In addition, embodiments of the present invention comprise imagers with integrated circuitry on the back sides thereof.
Conventionally, imagers have been fabricated with image sensing regions, integrated circuitry, and contacts on the active surface of a silicon wafer. State-of-the-art semiconductor devices, including imagers, typically have dimensions that are as small as possible. Nonetheless, a significant portion of the area, or real estate, on the active surface of an imager is typically occupied by image sensing elements. Accordingly, various other elements, including conductive lines, or traces, must be densely packed into the remaining, typically peripheral, areas of the semiconductor device. When conductive lines, or traces, are densely arranged, cross-talk, capacitance, and other undesirable electrical issues must be resolved. The difficulty in resolving these issues increases the more densely the conductive lines are arranged.
Another factor that sometimes undesirably adds to the area consumed by an imager is the so-called “snowplow” effect that occurs when color filter array (CFA) materials are applied (e.g., by spin coating) over imagers in which the dielectric material (e.g., glass) that overlies the image sensing elements has been thinned relative to the surrounding areas of the imager. Specifically, a peripheral “dead” zone is provided around an array of image sensing elements to accommodate thicker regions of color filter array material so as to avoid the presence of these thicker, or snowplowed, regions over the image sensing elements. The requirement of additional area prevents further decreases in the total area consumed by the imager, or introduces the additional complexities involved in increasing the density of the peripherally confined elements of the imager.
Furthermore, the presence of bond pads on the active surfaces of imagers necessitates that bond wires or other laterally extending intermediate conductive elements be used to electrically connect such imagers to carriers (e.g., circuit boards) and to other electronic components. As bond wires and other laterally extending intermediate conductive elements extend beyond the periphery of an imager to contacts (e.g., terminals) located outside of the periphery of the imager, they and the contacts occupy even more of the real estate upon the carrier, the value of which increases with decreases in acceptable electronic device dimensions.
Several approaches have been taken to address this undesirable occupation of real estate upon carriers for imagers. One approach has been to form through wafer interconnects (TWIs), or conductive vias, through the substrate of an imager. This approach requires that holes be formed through areas of the imager substrate that are not occupied by image sensing elements or integrated circuitry. The requirement of such “dead” area on a substrate, however, contradicts the trend toward maximized density and, thus, prevents optimal minimization of the dimensions of an imager. The other approach has been to form conductive elements that extend around the outer periphery of the imager substrate, which enables optimal circuit density, but effectively adds to the outer dimensions of the finished semiconductor device. Further, any redistribution layers (RDLs), or redistribution circuitry, required by both of these approaches undesirably adds to the overall thickness and cost of the imager.
Accordingly, there are needs for processes in which undesirable electrical effects of imagers may be reduced and contacts may be fabricated on the back sides of imagers while facilitating minimization of the peripheral dimensions of the imagers.
In the drawings, in which various features of embodiments of the present invention are depicted:
The present invention includes various embodiments of methods for fabricating imagers. Such methods include the fabrication of image sensing elements and transistors on the active surface of a substrate and the fabrication of contact openings, contact plugs, conductive lines, and contacts on and from the back side of the substrate.
With reference to
In addition, imager 10 includes a variety of elements that have been fabricated by known processes. In the illustrated embodiment, in which features corresponding to only one pixel of imager 10 are shown, imager 10 includes at least one image sensing element 20 in active surface 14 of substrate, as well as a photocell capacitor 25 and its underlying shallow trench isolation (STI) structure 27, and a transfer gate 30, a reset gate 35, a source follower gate 40, a row select gate 45, and appropriate source and drain regions (not shown) that correspond to sensing element 20. Transfer gate 30, reset gate 35, source follower gate 40, row select gate 45, and their respective source and drain regions are collectively referred to hereinafter as “imager transistors 30-45.” Like image sensing element 20, photocell capacitor 25, STI structure 27, and imager transistors 30-45 may also be located at active surface 14.
Optionally, as shown in
Imager 10 also includes a dielectric film 50 (e.g., doped silicon dioxide, such as borophosphosilicate glass (BPSG), phosphosilicate glass (BSG), phosphosilicate glass (PSG) or the like, etc., see
In some embodiments, as illustrated in
After the foregoing features have been fabricated (e.g., by employing known techniques or processes described herein) substrate 12 may, in some embodiments of the present invention, be thinned. Known processes (e.g., grinding, wet etching, etc.) may be used to remove material from back side 16 of substrate and, thus, to thin substrate 12. Substrate 12 may be thinned to any acceptable thickness (e.g., as thin as 100 μm in some embodiments, as tin as 50 μm in other embodiments, and even thinner substrates are contemplated as encompassed by the invention). In embodiments where imager 10 already includes contact plugs 64′, the contact plugs 64′ may be exposed as substrate 12 is thinned, potentially eliminating the need for the additional processing described in reference to
Once substrate 12 has a desired thickness, features may be fabricated on back side 16. An embodiment of such a back side fabrication process is depicted in
As illustrated in
As contact holes 60 extend directly to very small features 65 (e.g., features that, in some embodiments, correspond to conductive line widths of about 100 nm or less) (e.g., source/drain regions, etc.) at active surface 14, contact holes 60 may have correspondingly small dimensions. As noted above, in some embodiments contact holes 60 may be about 200 nm or less across, or in diameter. In other embodiments, contact holes may be about 100 nm or less across, or in diameter.
As shown in
In embodiments where the dielectric film 61 covers features 65 to which electrical contacts are to be made, dielectric film 61 is removed from features 65 to re-expose the same to contact holes 60, as depicted in
In some embodiments, such re-exposure may be effected by way of a so-called “spacer etch,” which is a dry etch in which portions of an etched film that are oriented in substantially the same direction as (i.e., substantially parallel to) that in which the etch is to be effected (e.g., portions of dielectric film 61 (
Alternatively, in other embodiments, a mask (e.g., a photomask, a hard mask, a transparent carbon mask, any combination of the foregoing, etc.) (not shown) of a type known in the art may be formed over dielectric film 61 (
Conductive features, including contact plugs 64, may then be formed in contact holes 60, as shown in
Some embodiments of contact plugs 64 may be formed by filling or substantially filling contact holes 60 with conductive material (e.g., by known deposition processes). Other embodiments of contact plugs 64 may be fabricated by forming (e.g., by deposition processes) one or more films, or coatings, of conductive material (e.g., polysilicon, etc.) on a surface of each contact hole 60 (i.e., on dielectric liner 62, a diffusion barrier, an interconnect, etc.), then filling (e.g., by deposition processes, plating processes, etc.) any void remaining within the contact hole 60 with a conductive material (e.g., polysilicon, tungsten, etc.) or a dielectric material.
In embodiments where the material layer or layers from which contact plugs 64 are formed are electrically isolated from back side 16 of substrate 12 by back side dielectric film 66 (see, e.g.,
In other embodiments, where back side 16 of substrate 12 was not covered by a back side dielectric layer 66 prior to the fabrication of contact plugs 64 (see, e.g.,
In such embodiments, as well as in imager 10 embodiments in which contact plugs 64′ are formed through active surface 14 of substrate 12 rather than through back side 16 thereof, such as the embodiment shown in
Next, as shown in
Further processing may continue, as known in the art, to form additional interlayer dielectric films 70, 74, laterally extending conductive lines 72, 76, interlayer contacts or interconnects 71, 73, and any other desired semiconductor device features, as well as a protective layer 78 and external contacts 79 (e.g., bond pads), to fabricate a completed imager 10 with back side integrated circuitry 80, as shown in
Referring now to
As at least some conductive lines 68, 72, 76 and external contacts 79 are carried by back side 16 of substrate 12, they may extend across locations that are opposite from image sensing element 20 and, thus are not confined to the periphery of imager 10. Consequently, electrical and other design constraints may be eased with back side integrated circuitry 80, while the overall size of the chip may be reduced relative to state-of-the-art imagers. Further, back side integrated circuitry 80 eliminates the additional processes and costs associated with fabricating conductive features, such as edge-bound conductive traces or TWIs or conductive vias, to reroute circuitry from above the active surface of an imager substrate to its back side.
Additionally, by placing such metallization on back side 16, in some embodiments, the features that are fabricated on active surface 14 of substrate 12 of imager 10 protrude only a small distance from active surface 14 (e.g., about one-half micron or less in embodiments where no conductive lines extend over photocell capacitor 25 or imager transistors 30-45) and, thus, above image sensing element 20. When compared with the typical seven to ten microns that features of state-of-the-art imagers protrude from the active surfaces of the substrates of such imagers, the distance, or focal length F, between image sensing element 20 and any optical elements (e.g., CFA 85, microlens 90, glass, lenses, filters, etc) to be positioned thereover is significantly reduced. In some embodiments, the reduction in focal length F may be sufficient to eliminate the use of a microlens array over image sensing element 20. Accordingly, some embodiments of imagers 10 of the present invention neither include nor require microlenses.
While the foregoing description is limited to embodiments of photoimagers with contact openings that extend exclusively through the substrate, embodiments of photoimagers that additionally include contact openings that extend through features fabricated over the active surfaces thereof are also within the scope of the present invention.
With reference to
Although the foregoing description includes many specifics, these should not be construed as limiting the scope of the present invention but, merely, as providing illustrations of some of the presently preferred embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention Features from different embodiments may be employed in combination. The scope of the invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions and modifications to the invention as disclosed herein which fall within the meaning and scope of the claims are to be embraced thereby.
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|U.S. Classification||257/291, 257/E27.133, 257/293, 257/432, 257/292, 257/435, 257/294, 257/431|
|Cooperative Classification||H01L27/14612, H01L27/14643, H01L27/14632, H01L27/14625, H01L27/14636|
|European Classification||H01L27/146A18, H01L27/146A10, H01L27/146A14|
|Jun 12, 2007||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIRBY, KYLE K.;OLIVER, STEVE;REEL/FRAME:019416/0903;SIGNING DATES FROM 20070529 TO 20070607
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIRBY, KYLE K.;OLIVER, STEVE;SIGNING DATES FROM 20070529TO 20070607;REEL/FRAME:019416/0903
|Nov 22, 2011||CC||Certificate of correction|
|Feb 25, 2015||FPAY||Fee payment|
Year of fee payment: 4
|May 12, 2016||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001
Effective date: 20160426
|Jun 2, 2016||AS||Assignment|
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426