|Publication number||US8039877 B2|
|Application number||US 12/207,417|
|Publication date||Oct 18, 2011|
|Filing date||Sep 9, 2008|
|Priority date||Sep 9, 2008|
|Also published as||CN101673766A, US20100059797|
|Publication number||12207417, 207417, US 8039877 B2, US 8039877B2, US-B2-8039877, US8039877 B2, US8039877B2|
|Inventors||Tat Ngai, Qi Wang|
|Original Assignee||Fairchild Semiconductor Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (45), Non-Patent Citations (17), Referenced by (6), Classifications (26), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is related to U.S. patent application Ser. No. 12/174,030 filed Jul. 16, 2008, which is commonly assigned and incorporated herein by reference in its entirety for all purposes. This application is also related to U.S. patent application Ser. No. 11/189,163 filed Jul. 25, 2005, which is commonly assigned and incorporated herein by reference in its entirety for all purposes.
The present invention relates in general to semiconductor devices, and more particularly to a method and structure for making trench FETs in (110)-oriented silicon on metal (SOM) substrates and having high dielectric constant (high k) gate dielectrics.
Conventional semiconductor manufacturing utilizes a number of processes to form semiconductor structures on substrates. In certain devices, the substrate is used as part of the current conduction path. For example, the substrate plays an important role with the solid state switch which is a key semiconductor structure used for discrete device applications and integrated circuits. Solid state switches include, for example, the power metal-oxide-semiconductor field effect transistor (power MOSFET), the insulated-gate bipolar transistor (IGBT), and various types of thyristors. Some of the defining performance characteristics for the power switch are its on-resistance (i.e., drain-to-source on-resistance, RDSon), breakdown voltage, and switching speed.
Generally, the switching speed, on-resistance, breakdown voltage, and power dissipation of a typical MOSFET device may be influenced by the layout, dimensions, and materials. Industry design practice has sought to keep the on-resistance of the MOSFET as low as possible to lower conducting power loss and increase current densities. For example, in vertical power MOSFET devices, the on-resistance is composed of several resistances such as channel resistance, drift region (epitaxial layer) resistance, and substrate resistance. The on-resistance of such a vertical power MOSFET device (as well as other MOSFET devices) is directly influenced by the type and dimensions of materials used in the drain to source conduction path. Therefore, for a vertical power devices, such as a power MOSFET, the substrate is a critical performance element.
Additionally, the substrate can impact the property and quality of the gate dielectric in the MOSFET. Therefore, the method of forming the gate dielectric plays an important role in determining the performance and reliability of an MOSFET.
Even though conventional techniques have been used for making vertical power devices utilizing various substrate materials, there are limitations associated with these conventional techniques. Some of these limitations are discussed in detail below.
Thus, there is a need for improved techniques for making vertical devices having desirable substrate and dielectric properties while maintaining a simple manufacturing process.
In accordance with embodiments of the invention, various techniques are described for forming vertical devices using p-type (110) oriented silicon material that provides increased hole mobility in current conduction on a (110) plane and in the <110> direction and heavily doped p-type regions for both reducing substrate resistance and forming a good ohmic contact. Additionally, a method for forming gate dielectric having high dielectric constant is also provided to obtain better quality on a (110) silicon surface compared to conventional thermal oxides. In one embodiment, a layer of heavily doped (110) silicon material is formed and then transferred to a support substrate. Following vertical device fabrication, the support substrate is replaced with a metal contact and support layer to the heavily doped (110) silicon material. In one variation of the invention, a layer of heavily doped (110) silicon material is formed on a lightly doped (110) silicon substrate. After device fabrication, the substrate is removed using a selective etching process after initial mechanical-grinding. Accordingly, embodiments of the invention combine higher hole mobility in the (110) p-type material, improved high k gate dielectric on the (110) surface, and low resistivity of heavily doped (110) p-type material to improve device properties of p-type vertical semiconductor devices.
According to an embodiment of the invention, a method is provided for forming a semiconductor device on a heavily doped p-type (110) semiconductor layer. The method starts with providing a heavily doped p-type (110) silicon layer, and forming a lightly doped p-type (110) silicon layer on the P heavily doped-type (110) silicon layer. The method also includes forming a p-channel MOSFET which has a channel region along a (110) crystalline plane in the lightly doped p-type (110) silicon layer to allow a current conduction in a <110> direction. The p-channel MOSFET also includes a gate dielectric layer having a high dielectric constant material lining the (110) crystalline plane. The method further includes forming a top conductor layer overlying the lightly doped p-type (110) silicon layer and a bottom conductor layer underlying the heavily doped p-type (110) silicon layer. Depending on the embodiment, the p-channel MOSFET can be a trench gate MOSFET, a shielded gate MOSFET, or a lateral MOSFET, etc. In each of these devices, a current conduction from the top conductor layer to the bottom conductor layer is characterized by a hole mobility along a <110> crystalline orientation and on a (110) crystalline plane. Methods for forming these devices are described in more details below.
In an embodiment, the heavily doped p-type (110) silicon layer overlying a first support substrate. After the top conductor is formed, the method includes bonding a second support substrate to the top conductor layer. Then the first support substrate is removed to expose a back surface of the heavily doped p-type (110) silicon layer, and the bottom conductor layer is formed in contact with the exposed back surface of the heavily doped p-type (110) silicon layer. Subsequently, the second support substrate is removed.
In one embodiment, the first support substrate includes an oxide layer overlying a silicon substrate, which is characterized by (100) crystalline orientation, p-type conductivity, and light doping. In a specific embodiment, the p-type heavily doped (110) silicon layer is formed as follows. A p-type heavily doped (110) silicon layer is formed overlying a first silicon substrate which is a lightly doped p-type (110) substrate. A first oxide layer is formed overlying the p-type heavily doped (110) silicon layer. Hydrogen ions are implanted into the heavily doped (110) silicon layer to form a region therein sufficiently weakened by the hydrogen to allow cleaving the heavily doped (110) silicon layer along the region to form an upper (110) layer and a lower (110) layer. In an embodiment, a second oxide layer is formed overlying the first support silicon substrate. The method includes bonding the first substrate to the first support silicon substrate and cleaving the p-type heavily doped (110) silicon layer along the region leaving the lower layer bonded to the second silicon dioxide layer overlying the first support silicon substrate. The lower (110) layer is characterized by p-type conductivity and heavy doping. In a specific embodiment, the first support substrate is removed by grinding the silicon substrate, etching the remaining silicon substrate using the oxide layer as an etch stop, and etching the oxide layer using the p-type heavily doped (110) silicon layer as an etch stop.
In another embodiment, the first support substrate includes a silicon substrate characterized by (110) crystalline orientation, p-type conductivity, and light doping, and the p-type heavily doped (110) silicon layer is formed using an epitaxial process or an ion implantation process. In a specific embodiment, the first support substrate is removed by grinding the silicon substrate and etching the remaining silicon substrate using the heavily doped p-type silicon as a etch stop. For example, the first support silicon substrate can be removed using a wet etching process including KOH or EDP.
The heavily doped (110) p-type silicon layer provides a low resistance device region. In a specific embodiment, the heavily doped (110) p-type silicon layer is characterized by a doping concentration of about 6×1019 cm−3 higher. In another embodiment, the heavily doped (110) p-type silicon layer is characterized by a doping concentration of about 1×1017 cm−3 higher. The resistance can be further reduced by using a thin layer of the p-type heavily doped (110) silicon layer. For example, this layer can have a thickness between approximately 0.5 um to approximately 3 um. On the other hand, the bottom metal layer has sufficient thickness for supporting the semiconductor device. In a specific example, the bottom conductor layer has a thickness of about 50 um.
In an embodiment the high dielectric constant material has a dielectric constant higher than that of a silicon dioxide. Merely as examples, the high dielectric constant material has a thickness of about 5 nm to about 50 nm. The high dielectric constant material, such as HfO2, can be formed using an atomic layer deposition (ALD) process. In one embodiment, the gate dielectric layer includes a thin interfacial dielectric layer underlying the high dielectric constant material. The thin interfacial layer can include oxynitride, chemical oxide, or thermal oxide.
In accordance with another embodiment of the invention, a semiconductor device includes a bottom conductive layer and a first p-type semiconductor layer overlying the bottom conductor layer. The first p-type semiconductor layer is heavily doped and is characterized by a surface crystal orientation of (110) and a first conductivity. The semiconductor device includes a second p-type semiconductor layer having overlying the first p-type semiconductor layer. The second semiconductor layer is also p-type and is characterized by a lower conductivity than the first conductivity. Moreover, the semiconductor device has a gate dielectric layer including a high dielectric constant material. The gate dielectric layer is formed on a (110) crystalline plane in the second p-type semiconductor layer. A top metal layer overlies the second p-type semiconductor layer and forms a top contact to the device. In this semiconductor device, a current conduction from the top metal layer to the bottom metal layer and through the second p-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and on (110) crystalline plane.
In a specific embodiment of the semiconductor device, the first p-type semiconductor layer is characterized by a doping concentration of 1E17/cm3 or higher. In another embodiment, the first p-type semiconductor layer is characterized by a doping concentration higher than 6E19/cm3.
In a specific embodiment, the semiconductor device includes a trench gate MOSFET having a trench extends into the second p-type semiconductor region. A gate dielectric layer lines sidewalls and bottom of the trench. The trench gate MOSFET includes a gate electrode over the gate dielectric in the trench and p-type source regions flanking each side of the gate electrode in the trench. The MOSFET also includes a p-type drift region, an n-type body region extending over the drift region, and p-type source regions in the body region adjacent to the trench.
In another embodiment, the semiconductor device includes a shielded gate trench MOSFET having a trench extending into the second semiconductor layer. A shield dielectric lines sidewalls and a bottom surface of the trench. The shielded gate trench MOSFET includes a shield electrode in a lower portion of the trench and is insulated from the second semiconductor layer by the shield dielectric. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper portions of trench sidewalls. The shielded gate trench MOSFET also includes a gate electrode in an upper portion of the trench over the inter-electrode dielectric. The gate electrode is insulated from the second semiconductor layer by the gate dielectric. In one embodiment, the second semiconductor layer includes a p-type drift region, an n-type body region extending over the drift region, and p-type source regions in the body region adjacent to the trench.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantage of the present invention.
Embodiments of the present invention provide various techniques for forming semiconductor devices using p-type (110) oriented silicon material and high dielectric constant gate dielectrics that provide increased current conduction, improved gate dielectric quality, and reduced substrate resistance. Depending upon the embodiment, the present invention includes various features, which may be used. These features include the following. In embodiments of the present invention, high mobility p-channel devices are realized on the (110)/<110> crystallographicaly configured silicon wafer to achieve high hole mobility in the channel region. The symbol (110)/<110> is used herein to denote current conduction along a <110> crystalline orientation and on a (110) crystalline plane. In some embodiments, the contribution of the (110) silicon substrate to device on-resistance is reduced by using a thin heavily doped (110) substrate. Embodiments of the present invention also provide (110) oriented silicon silicon-on-metal (SOM) structures that allow substantially improved RDSon without increasing gate charge at the vertical power trench devices. Moreover, embodiments of the invention also provide a gate dielectric having high dielectric constant dielectric material formed by a deposition method for improving the quality of gate dielectric on the (110) silicon surface.
The above features may be in one or more of the embodiments to follow. These features are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
A focus for power MOSFET device technology development includes reducing both on-resistance (RDSon) and gate charge, especially gate-to-drain charge (Qgd). For example, in trench MOSFET, RDSon can be reduced with increasing trench density by reducing device pitch. This approach, however, often leads to higher Qgd. It also can increase difficulty in contact formation for both the heavy body region and source region. This pitch miniaturization also can lead to higher leakage failure rate due to the defect generated by heavy body process. Therefore, other methods for reducing channel resistance are desirable.
According to one embodiment of the invention, a method is provided to fabricate p-channel trench MOSFET device on (110)-oriented silicon wafers with flat (notch) in crystallographic <110> direction to reduce the channel resistance. It is known that the hole mobility in the inversion layer can be more than doubled on silicon (110) plane in <110> direction ((110)/<110>) than on (100) plane in <100> direction ((100)/<100>). A relationship between hole mobility and channel resistance can be expressed in the following equation.
where L is the channel length, Z is the channel width, Cox is the gate oxide capacitance per unit area, VG is the gate voltage, μp is the hole mobility in channel region, and VT is the threshold voltage. The p-channel devices built on (110)/<110> crystallographically configured wafers thus have much reduced the Rch due to improved μp.
As shown in
A challenge in applying the (110)/<110> wafers for power MOSFET devices is a lack of readily available heavily doped (110) oriented wafers resulted from difficulties associated with growing heavily boron doped (110) oriented Czochralski (CZ) silicon wafers. Due to very small boron segregation coefficient on (110) oriented silicon crystal, boron incorporation is very limited. The resistivity of such ingot is in the range of tens Ω-cm. To build the vertical power trench device, it is necessary to have a heavily boron doped (110) oriented substrate and a technology to reduce the substrate contribution to the device on-resistance. An example of heavily boron doped (110) oriented substrate has a resistivity on the order of 100 mΩ-cm or lower, whereas substrates having resistivity in the range of about tens Ω-cm and higher are considered to be lightly doped in embodiments of the present invention. In an embodiment, heavily boron doped (110) oriented substrate may have a doping concentration of 1×1017 cm−3 or higher. Embodiments the present invention provides methods for forming heavily doped (110)-oriented silicon layer for device application. In a specific embodiment, the invention also provides methods for further reducing drain resistance with a thin heavily doped (110)-oriented silicon layer on a metal substrate.
A process flow for forming a heavily doped p-type (110) layer according to an exemplary embodiment of the invention can be briefly summarized below. A heavily doped thin (110) silicon epi layer with a low resistivity is grown on the lightly doped (110) orientation silicon seed wafer (seed wafer). Alternatively, this heavily doped thin (110) silicon layer can be formed by ion implantation or diffusion on the lightly doped (110) silicon seed wafer. Then a thermal silicon dioxide layer is grown on the top of the thin heavily doped layer. Next, hydrogen ions/molecules are implanted through the silicon dioxide layer and into the heavily doped (110) seed wafer. The seed wafer is then bonded to a support substrate which is topped with a thermal silicon dioxide layer. The bonded wafer pair is then subjected to the two-step low temperature annealing procedure for the separation of the heavily boron doped (110)-layer of the seed wafer along a cleaving plane defined by the hydrogen implantation energy. The thickness of the transferred heavily doped p-type (110) layer can range from 0.5 to 1.5 μm in a specific embodiment. Various device structures can then be formed using this heavily doped p-type (110) silicon layer. A more detailed description for this method is provided below in connection with
In an alternative embodiment, a heavily doped thin (110) silicon layer can be formed on a the lightly doped (110) silicon seed wafer using an epitaxial process or an ion implantation process. Various devices structures can be formed using the heavily doped thin (110) layer as a starting material. Subsequently, the lightly doped substrate can be removed using a selective etching process. A more detailed description for this method is provided below in connection with
Another challenge in applying the (110)/<110> configured wafers for power trench MOSFET devices is the difficulty in forming high quality gate oxide on (110) plane. An issue is to reduce both fixed oxide charge and interface trap density (Dit) to achieve acceptable threshold voltage and threshold voltage stability. It has been established that the Dit is proportional to the density of available bonds on the surface. Table 1 summarizes the silicon properties of different crystallographic planes. The Dits at (100) and at (111) planes are 2×1010 and 2×1011/cm2-eV, respectively. The fact that available bonds per unit area on the (110) plane are between (100) and (111) planes indicates that the Dit of (110) plane will be between 2×1010 and 2×1011 1/cm2-eV although no data is available. According to embodiments of the invention, reducing oxide growth rate and adding additional hydrogen annealing can further reduce the Dit and fixed oxide charge and improve gate oxide integrity.
Physical properties of Silicon
Dit at mid-gap
6.8 × 1014
6.8 × 1014
2 × 1010
9.6 × 1014
9.6 × 1014
7.85 × 1014
11.8 × 1014
2 × 1011
With the continued miniaturization of integrated circuit, gate dielectrics have been scaled to ever smaller thicknesses. Because SiO2 has a relatively low dielectric constant of about 3.9, such scaling is leading to SiO2 layers so thin, in the range approaching ˜1.0 nm, that excessive leakage current can comprise device performance. As a result, higher dielectric constant (˜15-25) gate dielectrics have been proposed as alternatives. According to embodiments of the present invention, a dielectric including a high dielectric constant (high k) material overlying a thin underlayer is suitable as a gate dielectric over a (110) silicon surface. In a specific embodiment, a method is provided for a gate dielectric including a high k dielectric material formed by atomic layer deposition (ALD) over a thin underlayer. Such a gate dielectric can be used advantageously to overcome the difficulties encountered by thermal SiO2 gate dielectrics over a (110) silicon surface. Depending upon the embodiment, the high k dielectric material can include HfO2, ZrO2, Gd2O3, La2O3, CeO2, TiO2, Y2O3, Ta2O5 and Al2O3, or other films.
Depending on the embodiments, the underlayer can be a thin thermal SiO2, chemical oxide which is often formed in a chemical wafer cleaning process, or an oxynitride layer. In an embodiment, the thickness of the underlayer can be in the range of approximately 5-10 Å. Of course, there can be other variations and alternatives.
In an embodiment, an atomic layer deposition (ALD) process is used to form a conformal dielectric film relatively independent of the surface orientation of the underlying substrate. Further, atomic layer deposition can allow the control and selection of the dielectric constant. In ALD, gaseous precursors are introduced in the form of pulses to the substrate surface within a reaction chamber, which usually is under low pressure. Between the pulses, the reaction chamber is purged with an inert gas, and/or evacuated. In each reaction step, the precursor saturates at the substrate surface and is chemisorbed. Subsequent pulsing with a purging gas removes excess precursor from the reaction chamber. A further pulsing phase introduces a second precursor to the substrate where the growth reaction of the desired film takes place. After the growth reaction, excess precursor and reaction byproducts are purged from the reaction chamber.
In a specific embodiment, a high dielectric constant material such as an HfO2 film is grown using H2/HfCl4 chemistry in an ALD process. First, an underlayer is formed on a substrate. The underlayer is a thin interfacial dielectric layer underlying the high dielectric constant material. For example, the interfacial layer can be a thin oxynitride layer, a thin thermal oxide layer, or a chemical oxide layer. As an example, the chemical oxide can be formed in a wet chemical wafer cleaning process. In an embodiment, this interfacial layer serves to pacify the surface of the substrate.
After the underlayer preparation, the wafers are loaded into the ALD process chamber, where the HfO2 film is grown at 300° C. One cycle HfO2 growth can include a pulse of H2O, followed by a pulse of HfCl4, each carried by a flow of N2 and separated by several seconds. The total pressure during growth can be maintained at, for example, 1-10 Torr. The deposition temperature can be in the range of about 180-600° C. The thickness of the HfO2 film can be controlled by the number and duration of pulses of precursors. For example, the thickness can be from about 50 Å to about 500 Å, depending on the embodiments.
The process of forming heavily doped p-type (110) thin substrate and high dielectric constant gate dielectric formation according to the present invention can be applied to the process flow of a variety of different power MOSFET processes. In an embodiment, this process can be used in the manufacture of a trench MOSFET. Alternatively, the trench formation process can be used in forming other trench FET structure such as a shielded gate FET. Examples of a trench gate MOSFET and a shielded agate MOSFET are provided below.
As shown in
As noted in
Additionally, gate dielectric layer 108 in
Thus, this embodiment of the present invention shows that p-type trench gate MOSFET 100 provides enhanced hole mobility and improved gate oxide quality on the (110) crystalline plane compared to conventional p-type trench MOSFETs.
Similar to device 100 of
In one embodiment, the concentration of hydrogen ions is provided at a sufficient depth and energy potential to form a hydrogen rich region, or cleavable region, 405, having an exemplary thickness of between about 1-2 μm. Because of hydrogen embrittlement, the cleavable region 405 lattice is weaker than non-hydrogen doped silicon lattice.
Referring back to
Where SiO2(OH)2− is a soluble complex.
As discussed above in connection with
As described above,
In a specific embodiment, a hydrogen anneal process can be performed. The hydrogen anneal not only reduces the defect density of the silicon layers but it also causes the corners of trenches 102 to become rounded.
Note that the p-type trench gate device structure in
An example of a trench MOSFET process describing various steps before and after the trench formation process module can be found in U.S. patent application Ser. No. 11/140,567, entitled “Structure and Method for Forming a Minimum Pitch Trench-Gate FET with Heavy Body Region,” which is hereby incorporated by reference.
As shown in
Note that the p-type shielded gate device structure in
According to embodiments of the present invention, the shield electrode in a shielded gate FETs can be floating (i.e., is electrically unbiased), biased to the source potential (e.g., ground potential), or biased to the same potential as the gate electrode. The electrical contact between the gate and shield electrodes may be formed in any non-active region, such as in the termination or edge regions of the die.
While the above includes descriptions of specific embodiments of the present invention, various modifications, variations, and alternatives may be employed. For example, although silicon is given as an example of a substrate material, other materials may be used. The invention is illustrated using trench MOSFETs, but it could easily be applied to other trench-gate structures such as IGBTs by merely reversing the polarity of the substrate. Similarly, implantation is given as an example of introducing dopants, but other doping methods, such as a gas or topical dopant source may be used to provide dopants for diffusion, depending on the appropriate mask being used. The process sequences depicted are for p-channel FETs, but modifying these process sequences to form N-channel FETs would be obvious to one skilled in the art in view of this disclosure. Also, while some trenches discussed above are shown to terminate within the epitaxial layer, the trenches may alternatively extend through the epitaxial layer and terminate within the substrate region. Further, the invention is not limited to trench gate structures and may be used in forming other devices such as planar gate vertical MOSFETs, planar gate vertical IGBTs, diodes, and various types of thyristors.
Merely as an example,
As shown in
As noted above, it is desirable to have a thin layer of the highly doped p-type (110) semiconductor region 1002 to reduce resistance. However, heavily doped p-type (110) substrates are not generally available commercially. According to embodiments of the present invention, the drift region 1004 and its underlying highly doped semiconductor region 1002 can be formed using the various methods discussed above. In one embodiment, both drift region 1004 and its underlying highly doped semiconductor region 1002 are epitaxial layers. In another embodiment, the highly doped semiconductor region 1002 is an P+substrate can be formed by ion implantation into a lightly doped (110) p-type substrate. Various substrate transfer processes can be used to obtain the thin layer of the highly doped p-type (110) semiconductor region 1002. Some of the substrate transfer processes are described above in connections with
While certain embodiments of the invention have been illustrated and described, those skilled in the art with access to the present teachings will recognize that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art. Accordingly, it is to be understood that the invention is intended to cover all variations, modifications, and equivalents within the scope of the following claims.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8338886||Dec 16, 2011||Dec 25, 2012||Fairchild Semiconductor Corporation||Semiconductor device with (110)-oriented silicon|
|US8399915 *||Apr 28, 2008||Mar 19, 2013||Rohm Co., Ltd.||Semiconductor device|
|US8653560 *||Jan 5, 2012||Feb 18, 2014||Kabushiki Kaisha Toshiba||Semiconductor device and fabrication method thereof|
|US20100090258 *||Apr 28, 2008||Apr 15, 2010||Rohm Co., Ltd.||Semiconductor device|
|US20120139007 *||Jun 7, 2012||Kabushiki Kaisha Toshiba||Semiconductor device and fabrication method thereof|
|US20130334598 *||Mar 18, 2013||Dec 19, 2013||Kabushiki Kaisha Toshiba||Semiconductor device and method for manufacturing same|
|U.S. Classification||257/255, 257/330, 257/E29.255, 257/E29.004|
|International Classification||H01L29/04, H01L29/78|
|Cooperative Classification||H01L21/6835, H01L2924/3025, H01L2924/19043, H01L21/76254, H01L29/7813, H01L29/66734, H01L29/7802, H01L29/407, H01L2924/13091, H01L2221/6835, H01L29/045, H01L2221/68368, H01L2924/30105, H01L2924/13055|
|European Classification||H01L21/683T, H01L29/04B, H01L21/762D8B, H01L29/78B2, H01L29/78B2T, H01L29/66M6T6F14V4|
|Jun 24, 2010||AS||Assignment|
Owner name: FAIRCHILD SEMICONDUCTOR CORPORATION,MAINE
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Owner name: FAIRCHILD SEMICONDUCTOR CORPORATION, MAINE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NGAI, TAT;WANG, QI;SIGNING DATES FROM 20081219 TO 20081223;REEL/FRAME:024586/0947
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