|Publication number||US8058157 B2|
|Application number||US 12/505,894|
|Publication date||Nov 15, 2011|
|Filing date||Jul 20, 2009|
|Priority date||Nov 30, 2005|
|Also published as||CN1976059A, US7564081, US20070120154, US20090280626|
|Publication number||12505894, 505894, US 8058157 B2, US 8058157B2, US-B2-8058157, US8058157 B2, US8058157B2|
|Inventors||Huilong Zhu, Zhijiong Luo|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (118), Non-Patent Citations (26), Referenced by (9), Classifications (15), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of U.S. patent application Ser. No. 11/164,621, filed Nov. 30, 2005.
1. Field of the Invention
The invention relates generally to semiconductor structures. More particularly, the invention relates to enhanced semiconductor device performance through the use of mechanical stress effects and/or dopant redistribution effects within semiconductor structures.
2. Description of the Related Art
As semiconductor technology has advanced and semiconductor device density requirements have increased, there has been an increased need to fabricate semiconductor devices (e.g., MOSFET devices) with reduced dimensions, such as reduced gate electrode lengths of the devices. A novel semiconductor structure that accommodates increased density due to its considerably decreased dimensions is a double gate device that uses a finFET structure. A finFET structure provides a vertical channel device that includes a semiconductor fin set sideways upon a substrate. In order to obtain desirable control of short channel effects (SCEs), the semiconductor fin is thin enough in a device channel region to ensure forming fully depleted semiconductor devices. A pair of gate dielectric layers is typically located upon a pair of opposite semiconductor fin sidewalls. A gate electrode of an inverted U shape is typically located upon the semiconductor fin and covering the pair of gate dielectric layers. In some other instances, the gate electrode is not located atop the fin and thus it is restricted to the sidewalls of the fin.
Beyond finFET structures that provide space efficient transistor structures with desirable SCE control, semiconductor devices are now commonly designed to use a mechanical stress effect (MSE) and/or a dopant redistribution or mobility effect to enhance transistor performance. The MSE is generally engineered to provide enhanced charge carrier mobility within a semiconductor device. The enhanced charge carrier mobility typically leads to enhanced semiconductor device performance.
finFET structures may be fabricated with stressed components to improve performance of the finFET structures. For example, each of: (1) Rim, in U.S. Pat. No. 6,815,738; and (2) Lee et al., in Pub. No. 2004/0256647, teaches stressed semiconductor fin structures within finFETs. Each provides the stressed semiconductor fin structures by utilizing a lattice mismatch for layered components when forming the stressed semiconductor fin structures.
Since desirable SCE control and space efficiency advantages of finFET devices are likely to continue to be of considerable significance within semiconductor device technology, and since stressed structures similarly also continue to provide semiconductor devices with enhanced performance, the utilization of stressed structures within finFETs is likely to continue.
The invention provides a pair of finFET structures and a method for fabricating a finFET structure.
The first of the pair of finFET structures includes a semiconductor fin located over a substrate. The structure also includes a gate electrode located over the semiconductor fin. Within the first structure, the gate electrode has a first stress in a first region located nearer the semiconductor fin and a second stress, which is different than the first stress, in a second region located filter from the semiconductor fin.
The second of the pair of finFET structures includes a semiconductor fin located over a pedestal within a substrate. Preferably, the semiconductor fin is located aligned over the pedestal within the substrate.
The method derives from the first of the finFET structures. The method provides for forming a semiconductor fin over a substrate. It also provides for forming a gate electrode over the semiconductor fin, where the gate electrode has a first stress in a first region located nearer the semiconductor fin and a second stress, which is different than the first stress, in a second region located further from the semiconductor fin.
The objects, features and advantages of the invention are understood within the context of the Description of the Preferred Embodiment, as set forth below. The Description of the Preferred Embodiment is understood within the context of the accompanying drawings, which form a material part of this disclosure, wherein:
The invention provides a finFET structure with enhanced performance, and a method for fabricating the finFET structure.
The substrate 10 may comprise any of several materials, including but not limited to: a conductor material, a semiconductor material or a dielectric material. Typically, the substrate 10 comprises a semiconductor material. The semiconductor material may be selected from the group including, but not limited to: silicon (Si), germanium (Ge), silicon-germanium (SiGe) alloy, silicon carbide (SiC), silicon-germanium alloy carbide (SiGeC) and compound semiconductor materials, such as (III-VI) and (II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide and indium phosphide materials. Typically, the substrate 10 has a thickness from about 1 to about 3 mils.
The buried dielectric layer 12 typically comprises an oxide of a semiconductor material from which comprises the substrate 10, when the substrate 10 comprises a semiconductor material. Alternatively, the buried dielectric layer 12 may comprise a nitride, an oxynitride or an alternative dielectric material. The buried dielectric layer 12 may be formed utilizing methods as are conventional in the semiconductor fabrication art. Non-limiting examples of the methods include thermal annealing methods, chemical vapor deposition methods and physical vapor deposition methods. Typically, the buried dielectric layer 12 has a thickness from about 200 to about 10000 angstroms.
The semiconductor layer 14 may comprise any of several semiconductor materials as are also conventional in the art. The semiconductor materials may include, but are not limited to: silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium alloy carbide, GaAs, InAs, InP, as well as other compound (III-V) and (II-VI) semiconductor materials. The semiconductor layer 14 may also comprise an organic semiconductor material. Typically, the semiconductor layer 14 has a thickness from about 300 to about 1000 angstroms.
The substrate 10 (when comprising a semiconductor material), the buried dielectric layer 12 and the semiconductor layer 14 comprise in an aggregate a semiconductor-on-insulator substrate. Within the embodiment and the invention, the substrate 10 typically comprises a silicon or silicon-germanium alloy semiconductor material, the buried dielectric layer 12 typically comprises a corresponding silicon or silicon-germanium oxide material and the semiconductor layer 14 typically also comprises a corresponding silicon or silicon-germanium alloy semiconductor material. The semiconductor-on-insulator substrate may be formed utilizing any of several methods that are conventional in the semiconductor fabrication art. Non-limiting examples of such methods include layer transfer methods, laminating methods and, in particular, separation by implantation of oxygen (SIMOX) methods.
The hard mask layer 16 comprises a hard mask material as is otherwise generally conventional in the art. Non-limiting examples of hard mask materials include oxides, nitrides and oxynitrides, typically of silicon and/or germanium, but oxides, nitrides and oxynitrides of other elements may also be utilized, The aforementioned hard mask materials may be deposited utilizing methods including, but not limited to: thermal annealing methods, chemical vapor deposition methods and physical vapor deposition sputtering methods. Typically, the hard mask layer 16 has a thickness from about 200 to about 400 angstroms, although such a thickness does not limit the embodiment or the invention.
The patterned photoresist layer 18 may comprise photoresist materials that are conventional in the art. Non-limiting examples include positive photoresist materials, negative photoresist materials and hybrid photoresist materials. The resists may be processed to provide the patterned photoresist layer 18 utilizing spin coating, photoexposure and development methods and materials as are conventional in the art. Typically, the patterned photoresist layer 18 has a thickness from about 5000 to about 15000 angstroms.
The foregoing layers are preferably etched anisotropically to thus provide substantially straight sidewalls. Such etching typically utilizes a reactive ion etch plasma etchant or another anisotropic etchant, such as an ion beam etchant. Wet chemical etchant materials, while typically less common, may under certain circumstances also be utilized, although they are generally isotropic etchants. When utilizing a reactive ion etch plasma etchant, a fluorine containing etchant gas composition is typically utilized when etching a silicon containing hard mask material or a silicon containing dielectric material. A chlorine containing etchant gas composition is typically utilized when etching a silicon or germanium containing semiconductor material.
Similarly, while the schematic plan-view diagram of
The contiguous spacer layer 16′ as illustrated in
The pad dielectric layer 24 typically comprises any of several dielectric materials as are conventionally utilized for a pad dielectric layer. Non-limiting examples include silicon oxide, silicon nitride and silicon oxynitride materials. Silicon oxide materials are particularly common. The pad dielectric layer 24 may be formed utilizing any of several methods as are convention in the art. Non-limiting examples include thermal oxidation methods, chemical vapor deposition methods and physical vapor deposition methods. Preferably, the pad dielectric layer 24 is formed utilizing a thermal oxidation method to yield a silicon oxide material. Typically, the pad dielectric layer 24 has a thickness from about 10 to about 100 angstroms.
The stress imparting layer 26 may comprise any of several stress imparting materials, but from a practical perspective the stress imparting material must have thermal resistance characteristics that allow for higher temperature annealing absent deterioration of the stress imparting layer or any layers there beneath. Non-limiting examples of stress imparting materials include silicon nitride materials and silicon oxynitride materials. Silicon nitride materials are particularly preferred. The stress imparting layer 26 may have either a positive stress or a negative stress as appropriate for either an n-finFET or a p-finFET.
Also from a practical perspective, there are several process variables that may be utilized to influence stress when forming the stress imparting layer 26. Non-limiting examples include deposition temperature, starting materials, deposition rate and thickness. Typically, the stress imparting layer has a thickness from about 500 to about 2000 angstroms, although neither the embodiment nor the invention is so limited.
With respect to the recrystallized gate electrode 22′, the first stress therein may be less than the second stress or the first stress may be greater than the second stress. The first stress and the second stress may be both compressive or both tensile. Alternatively, one of the first stress and the second stress may be tensile and the other of the first stress and the second stress may be compressive.
Recrystallization of the partially amorphized gate electrode 22′ to form the recrystallized gate electrode 22″ may be undertaken utilizing any of several thermal annealing methods that are conventional in the semiconductor fabrication art. Non-limiting examples include furnace annealing methods and rapid thermal annealing methods. Typically, but not exclusively, the partially amorphized gate electrode 22′ is thermally annealed at a temperature from about 1000° to about 1200° C. for a time period from about 2 to about 6 hours. Typically, the thermal annealing is undertaken in an inert atmosphere, such as a helium, argon, krypton or nitrogen atmosphere, although this is not required. As is understood by a person skilled in the art, the foregoing thermal annealing conditions also provide for a recrystallizing of source/drain regions of the semiconductor fin 14 a and a drive-in of active dopants implanted therein.
Although the preferred embodiment illustrates the invention with the recrystallized gate electrode 22″ having two regions of different stress, neither the instant embodiment nor the invention is so limited. Rather, as is understood by a person skilled in the art the invention may be practiced with sequentially less and less deep ion implant amorphizations of a gate electrode, along with concurrent and sequential recrystallizations under multiple sequential stress imparting layer influence. The foregoing process sequence yields further additionally defined stress regions within a multiply recrystallized gate electrode.
Once source/drain region portions of the semiconductor fin 14 a are exposed, the pair of silicide layers 28 may be formed utilizing methods as are also conventional in the art. Typically, the pair of silicide layers 28 is formed utilizing a metal silicide forming metal layer deposition, thermal annealing and subsequent unreacted metal etch method (i.e. a salicide method). Alternative methods may be employed. Typical metal silicide forming metals include, but are not limited to: tungsten, cobalt, platinum, nickel and titanium. Thermal annealing conditions are typically about 350° to about 850° C. for a time period from about 1 second to about 10 minutes. Unreacted metal etchants are specific to particular metals and are typically wet chemical etchants, although this is not a requirement of the invention. Typically, each of the pair of silicide layers 28 has a thickness from about 50 to about 300 angstroms. They are optional within the invention.
Within the instant embodiment, the second stress imparting layer 30 may have a third stress different from either: (1) the first stress closer to the semiconductor fin 14 a within the unamorphized sub-layer 22 a of the recrystallized gate electrode 22″; or (2) the second stress further from the semiconductor fin 14 a within the recrystallized sub-layer 22 b′ of the recrystallized gate electrode 22″. The first stress, the second stress and the third stress may define a continuous stress progression (either increasing or decreasing). Alternatively, they may define a discontinuous stress progression. Each of the first stress, second stress and third stress may independently be a tensile stress or a compressive stress. Magnitudes of the first stress, second stress and third stress may also vary, but will typically range from about −3.5 GPa to 2.5 GPa.
The preferred embodiment of the invention is illustrative of the invention rather than limiting of the invention. Revisions and modifications may be made to methods, materials, structures and dimensions in accordance with the preferred embodiment of the invention while still providing an embodiment in accordance with the invention, further in accordance with the accompanying claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3602841||Jun 18, 1970||Aug 31, 1971||Ibm||High frequency bulk semiconductor amplifiers and oscillators|
|US4665415||Apr 24, 1985||May 12, 1987||International Business Machines Corporation||Semiconductor device with hole conduction via strained lattice|
|US4853076||Jul 9, 1987||Aug 1, 1989||Massachusetts Institute Of Technology||Semiconductor thin films|
|US4855245||Oct 4, 1988||Aug 8, 1989||Siemens Aktiengesellschaft||Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate|
|US4952524||May 5, 1989||Aug 28, 1990||At&T Bell Laboratories||Semiconductor device manufacture including trench formation|
|US4958213||Jun 12, 1989||Sep 18, 1990||Texas Instruments Incorporated||Method for forming a transistor base region under thick oxide|
|US5006913||Nov 2, 1989||Apr 9, 1991||Mitsubishi Denki Kabushiki Kaisha||Stacked type semiconductor device|
|US5060030||Jul 18, 1990||Oct 22, 1991||Raytheon Company||Pseudomorphic HEMT having strained compensation layer|
|US5081513||Feb 28, 1991||Jan 14, 1992||Xerox Corporation||Electronic device with recovery layer proximate to active layer|
|US5108843||Nov 27, 1989||Apr 28, 1992||Ricoh Company, Ltd.||Thin film semiconductor and process for producing the same|
|US5134085||Nov 21, 1991||Jul 28, 1992||Micron Technology, Inc.||Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories|
|US5310446||Jul 13, 1992||May 10, 1994||Ricoh Company, Ltd.||Method for producing semiconductor film|
|US5354695||Apr 8, 1992||Oct 11, 1994||Leedy Glenn J||Membrane dielectric isolation IC fabrication|
|US5371399||Aug 9, 1993||Dec 6, 1994||International Business Machines Corporation||Compound semiconductor having metallic inclusions and devices fabricated therefrom|
|US5391510||Apr 7, 1994||Feb 21, 1995||International Business Machines Corporation||Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps|
|US5459346||Nov 17, 1994||Oct 17, 1995||Ricoh Co., Ltd.||Semiconductor substrate with electrical contact in groove|
|US5471948||May 11, 1994||Dec 5, 1995||International Business Machines Corporation||Method of making a compound semiconductor having metallic inclusions|
|US5557122||May 12, 1995||Sep 17, 1996||Alliance Semiconductors Corporation||Semiconductor electrode having improved grain structure and oxide growth properties|
|US5561302||Sep 26, 1994||Oct 1, 1996||Motorola, Inc.||Enhanced mobility MOSFET device and method|
|US5565697||Jun 2, 1995||Oct 15, 1996||Ricoh Company, Ltd.||Semiconductor structure having island forming grooves|
|US5571741||Jun 7, 1995||Nov 5, 1996||Leedy; Glenn J.||Membrane dielectric isolation IC fabrication|
|US5592007||Jun 7, 1995||Jan 7, 1997||Leedy; Glenn J.||Membrane dielectric isolation transistor fabrication|
|US5592018||Jun 7, 1995||Jan 7, 1997||Leedy; Glenn J.||Membrane dielectric isolation IC fabrication|
|US5670798||Mar 29, 1995||Sep 23, 1997||North Carolina State University||Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same|
|US5679965||Nov 9, 1995||Oct 21, 1997||North Carolina State University||Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same|
|US5683934||May 3, 1996||Nov 4, 1997||Motorola, Inc.||Enhanced mobility MOSFET device and method|
|US5840593||Mar 10, 1997||Nov 24, 1998||Elm Technology Corporation||Membrane dielectric isolation IC fabrication|
|US5861651||Feb 28, 1997||Jan 19, 1999||Lucent Technologies Inc.||Field effect devices and capacitors with improved thin film dielectrics and method for making same|
|US5880040||Apr 15, 1996||Mar 9, 1999||Macronix International Co., Ltd.||Gate dielectric based on oxynitride grown in N2 O and annealed in NO|
|US5940716||Mar 14, 1997||Aug 17, 1999||Samsung Electronics Co., Ltd.||Methods of forming trench isolation regions using repatterned trench masks|
|US5940736||Mar 11, 1997||Aug 17, 1999||Lucent Technologies Inc.||Method for forming a high quality ultrathin gate oxide layer|
|US5946559||Jun 7, 1995||Aug 31, 1999||Elm Technology Corporation||Membrane dielectric isolation IC fabrication|
|US5960297||Jul 2, 1997||Sep 28, 1999||Kabushiki Kaisha Toshiba||Shallow trench isolation structure and method of forming the same|
|US5989978||Jul 16, 1998||Nov 23, 1999||Chartered Semiconductor Manufacturing, Ltd.||Shallow trench isolation of MOSFETS with reduced corner parasitic currents|
|US6008126||Feb 23, 1998||Dec 28, 1999||Elm Technology Corporation||Membrane dielectric isolation IC fabrication|
|US6025280||Apr 28, 1997||Feb 15, 2000||Lucent Technologies Inc.||Use of SiD4 for deposition of ultra thin and controllable oxides|
|US6046464||Aug 13, 1997||Apr 4, 2000||North Carolina State University||Integrated heterostructures of group III-V nitride semiconductor materials including epitaxial ohmic contact comprising multiple quantum well|
|US6066545||Dec 7, 1998||May 23, 2000||Texas Instruments Incorporated||Birdsbeak encroachment using combination of wet and dry etch for isolation nitride|
|US6090684||Jul 29, 1999||Jul 18, 2000||Hitachi, Ltd.||Method for manufacturing semiconductor device|
|US6107143||Sep 10, 1998||Aug 22, 2000||Samsung Electronics Co., Ltd.||Method for forming a trench isolation structure in an integrated circuit|
|US6117722||Feb 18, 1999||Sep 12, 2000||Taiwan Semiconductor Manufacturing Company||SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof|
|US6133071||Oct 15, 1998||Oct 17, 2000||Nec Corporation||Semiconductor device with plate heat sink free from cracks due to thermal stress and process for assembling it with package|
|US6165383||Oct 15, 1998||Dec 26, 2000||Organic Display Technology||Useful precursors for organic electroluminescent materials and devices made from such materials|
|US6180501||Oct 14, 1999||Jan 30, 2001||Chartered Semiconductor Manufacturing Ltd.||Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process|
|US6221735||Feb 15, 2000||Apr 24, 2001||Philips Semiconductors, Inc.||Method for eliminating stress induced dislocations in CMOS devices|
|US6228694||Jun 28, 1999||May 8, 2001||Intel Corporation||Method of increasing the mobility of MOS transistors by use of localized stress regions|
|US6246095||Sep 3, 1998||Jun 12, 2001||Agere Systems Guardian Corp.||System and method for forming a uniform thin gate oxide layer|
|US6255169||Feb 22, 1999||Jul 3, 2001||Advanced Micro Devices, Inc.||Process for fabricating a high-endurance non-volatile memory device|
|US6261964||Dec 4, 1998||Jul 17, 2001||Micron Technology, Inc.||Material removal method for forming a structure|
|US6265317||Jan 9, 2001||Jul 24, 2001||Taiwan Semiconductor Manufacturing Company||Top corner rounding for shallow trench isolation|
|US6274444||Aug 10, 1999||Aug 14, 2001||United Microelectronics Corp.||Method for forming mosfet|
|US6281532||Jun 28, 1999||Aug 28, 2001||Intel Corporation||Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering|
|US6284623||Oct 25, 1999||Sep 4, 2001||Peng-Fei Zhang||Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect|
|US6284626||Apr 6, 1999||Sep 4, 2001||Vantis Corporation||Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench|
|US6319794||Oct 14, 1998||Nov 20, 2001||International Business Machines Corporation||Structure and method for producing low leakage isolation devices|
|US6361885||Nov 19, 1998||Mar 26, 2002||Organic Display Technology||Organic electroluminescent materials and device made from such materials|
|US6362082||Jun 28, 1999||Mar 26, 2002||Intel Corporation||Methodology for control of short channel effects in MOS transistors|
|US6368931||Mar 27, 2000||Apr 9, 2002||Intel Corporation||Thin tensile layers in shallow trench isolation and method of making same|
|US6373088||Jun 10, 1998||Apr 16, 2002||Texas Instruments Incorporated||Edge stress reduction by noncoincident layers|
|US6380008 *||Dec 14, 2000||Apr 30, 2002||Texas Instruments Incorporated||Edge stress reduction by noncoincident layers|
|US6403486||Apr 30, 2001||Jun 11, 2002||Taiwan Semiconductor Manufacturing Company||Method for forming a shallow trench isolation|
|US6403975||Apr 8, 1997||Jun 11, 2002||Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev||Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates|
|US6406973||Jun 29, 2000||Jun 18, 2002||Hyundai Electronics Industries Co., Ltd.||Transistor in a semiconductor device and method of manufacturing the same|
|US6461936||Jan 4, 2002||Oct 8, 2002||Infineon Technologies Ag||Double pullback method of filling an isolation trench|
|US6476462||Dec 7, 2000||Nov 5, 2002||Texas Instruments Incorporated||MOS-type semiconductor device and method for making same|
|US6483171||Aug 13, 1999||Nov 19, 2002||Micron Technology, Inc.||Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same|
|US6493497||Sep 26, 2000||Dec 10, 2002||Motorola, Inc.||Electro-optic structure and process for fabricating same|
|US6498358||Jul 20, 2001||Dec 24, 2002||Motorola, Inc.||Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating|
|US6501121||Nov 15, 2000||Dec 31, 2002||Motorola, Inc.||Semiconductor structure|
|US6506652||Dec 9, 1999||Jan 14, 2003||Intel Corporation||Method of recessing spacers to improved salicide resistance on polysilicon gates|
|US6509618||Jan 4, 2000||Jan 21, 2003||Intel Corporation||Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates|
|US6521964||Aug 30, 1999||Feb 18, 2003||Intel Corporation||Device having spacers for improved salicide resistance on polysilicon gates|
|US6531369||Feb 14, 2002||Mar 11, 2003||Applied Micro Circuits Corporation||Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)|
|US6531740||Jul 17, 2001||Mar 11, 2003||Motorola, Inc.||Integrated impedance matching and stability network|
|US6621392||Apr 25, 2002||Sep 16, 2003||International Business Machines Corporation||Micro electromechanical switch having self-aligned spacers|
|US6635506||Nov 7, 2001||Oct 21, 2003||International Business Machines Corporation||Method of fabricating micro-electromechanical switches on CMOS compatible substrates|
|US6717216||Dec 12, 2002||Apr 6, 2004||International Business Machines Corporation||SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device|
|US6825529||Dec 12, 2002||Nov 30, 2004||International Business Machines Corporation||Stress inducing spacers|
|US6831292||Sep 20, 2002||Dec 14, 2004||Amberwave Systems Corporation||Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same|
|US6855990||Nov 26, 2002||Feb 15, 2005||Taiwan Semiconductor Manufacturing Co., Ltd||Strained-channel multiple-gate transistor|
|US6974981||Dec 12, 2002||Dec 13, 2005||International Business Machines Corporation||Isolation structures for imposing stress patterns|
|US6977194||Oct 30, 2003||Dec 20, 2005||International Business Machines Corporation||Structure and method to improve channel mobility by gate electrode stress modification|
|US7015082||Nov 6, 2003||Mar 21, 2006||International Business Machines Corporation||High mobility CMOS circuits|
|US20010009784||Feb 14, 2001||Jul 26, 2001||Yanjun Ma||Structure and method of making a sub-micron MOS transistor|
|US20020048861||Oct 25, 2001||Apr 25, 2002||Lg Electronics Inc.||Thin-film transistor and method of making same|
|US20020063292||Nov 29, 2000||May 30, 2002||Mark Armstrong||CMOS fabrication process utilizing special transistor orientation|
|US20020074598||Nov 9, 2001||Jun 20, 2002||Doyle Brian S.||Methodology for control of short channel effects in MOS transistors|
|US20020086472||Dec 29, 2000||Jul 4, 2002||Brian Roberds||Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel|
|US20020086497||Dec 6, 2001||Jul 4, 2002||Kwok Siang Ping||Beaker shape trench with nitride pull-back for STI|
|US20020090791||Jun 28, 1999||Jul 11, 2002||Brian S. Doyle||Method for reduced capacitance interconnect system using gaseous implants into the ild|
|US20030032261||Aug 8, 2001||Feb 13, 2003||Ling-Yen Yeh||Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation|
|US20030040158||Aug 21, 2002||Feb 27, 2003||Nec Corporation||Semiconductor device and method of fabricating the same|
|US20030057184||Sep 22, 2001||Mar 27, 2003||Shiuh-Sheng Yu||Method for pull back SiN to increase rounding effect in a shallow trench isolation process|
|US20030067035||Sep 28, 2001||Apr 10, 2003||Helmut Tews||Gate processing method with reduced gate oxide corner and edge thinning|
|US20040113174||Dec 12, 2002||Jun 17, 2004||International Business Machines Corporation||Isolation structures for imposing stress patterns|
|US20040113217||Dec 12, 2002||Jun 17, 2004||International Business Machines Corporation||Stress inducing spacers|
|US20040238914||Jan 5, 2004||Dec 2, 2004||International Business Machines Corporation||STI stress modification by nitrogen plasma treatment for improving performance in small width devices|
|US20040262784||Jun 30, 2003||Dec 30, 2004||International Business Machines Corporation||High performance cmos device structures and method of manufacture|
|US20050040460||Sep 7, 2004||Feb 24, 2005||Dureseti Chidambarrao||Stress inducing spacers|
|US20050082634||Oct 16, 2003||Apr 21, 2005||International Business Machines Corporation||High performance strained cmos devices|
|US20050093030||Oct 30, 2003||May 5, 2005||Doris Bruce B.||Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers|
|US20050093074||Nov 5, 2003||May 5, 2005||International Business Machines Corporation||Method of fabricating a finfet|
|US20050098829||Nov 6, 2003||May 12, 2005||Doris Bruce B.||High mobility CMOS circuits|
|US20050106799||Nov 14, 2003||May 19, 2005||International Business Machines Corporation||Stressed semiconductor device structures having granular semiconductor material|
|US20050145954||Jan 5, 2004||Jul 7, 2005||International Business Machines Corporation||Structures and methods for making strained mosfets|
|US20050148146||Feb 18, 2005||Jul 7, 2005||Doris Bruce D.||High performance strained CMOS devices|
|US20050194699||Mar 3, 2004||Sep 8, 2005||International Business Machines Corporation||Mobility enhanced cmos devices|
|US20050236668||Apr 23, 2004||Oct 27, 2005||International Business Machines Corporation||STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI CMOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C|
|US20050245017||Jul 7, 2005||Nov 3, 2005||Belyansky Michael P||Structure and method to improve channel mobility by gate electrode stress modification|
|US20050280051||Aug 10, 2005||Dec 22, 2005||Dureseti Chidambarrao||Isolation structures for imposing stress patterns|
|US20050282325||Aug 11, 2005||Dec 22, 2005||Belyansky Michael P||Structure and method to improve channel mobility by gate electrode stress modification|
|US20060022268||Jul 26, 2005||Feb 2, 2006||Chang-Woo Oh||Semiconductor devices including stress inducing layers|
|US20060027868||Oct 6, 2005||Feb 9, 2006||Ibm Corporation||High mobility CMOS circuits|
|US20060057787||Nov 25, 2002||Mar 16, 2006||Doris Bruce B||Strained finfet cmos device structures|
|US20060060925||Sep 17, 2004||Mar 23, 2006||International Business Machines Corporation||Semiconductor device structure with active regions having different surface directions and methods|
|US20070048958 *||Aug 23, 2005||Mar 1, 2007||Wen-Shiang Liao||Three-dimensional multi-gate device and fabricating method thereof|
|US20080099847||Dec 14, 2007||May 1, 2008||Micron Technology, Inc.||Integrated Circuits and Methods of Forming a Field Effect Transistor|
|CN1695227A||Nov 25, 2002||Nov 9, 2005||国际商业机器公司||Strained FinFET CMOS device structures|
|1||Application No. 200610139559.8 Title: FinFet Structure With Multiply Stressed Gate Electrode Zhu, Huilong, et al. Notice of Rejection dated May 15, 2009.|
|2||Bean et al., "GEx Si1-x/Si Strained-Layer Superlattice Grown by Molecular Beam Epitaxy", J. Vac. Sci. Technol., 1984, pp. 436-440, vol. A 2, No. 2.|
|3||Doyle et al., "Recovery of Hot-Carrier Damage in Reoxidized Nitrided Oxide MOSFET's" Electron Device Letters, IEEE, 1992, pp. 38-40, vol. 13, No. 1.|
|4||Houghton et al., "Equilibrium Critical Thickness for Si1-xGex Strained Layers on (100) Si", Appl. Phys. Lett., 1990, pp. 460-462, vol. 56, No. 29.|
|5||Huang et al., "Temperature Dependence and Post-Stress Recovery of Hot Electron Degradation Effects in Bipolar Transistors", Bipolar Circuits and technology Meeting 7.5, IEEE, 1991, pp. 170-173.|
|6||Ito et al., "Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design", International Electron Devices Meeting, IEEE, 2000, 10.7.1-10.7.4.|
|7||Iyer et al., "Heterojunction Bipolar Transistors Using Si-Ge Alloys", Transactions on Electron Devices, IEEE, 1989, pp. 2043-2064, vol. 36, No. 10.|
|8||Khater et al., "SiGe HBT Technology with Fmax/Ft = 350/300 GHz and Gate Delay Below 3.3 ps", IEEE, 2004.|
|9||Li et al., "Design of W-Band VCOs with high Output Power for Potential Application in 77GHz Automotive Radar Systems", GaAs Digest, IEEE, 2003, pp. 263-266.|
|10||Matthews et al., "Defects in Epitaxial Multilayers", Journal of Crystal Growth, 1974, pp. 118-125, vol. 27.|
|11||Momose et al., "Analysis of the Temperature Dependence of Hot-Carrier-Induced Degradation in Bipolar Transistors for Bi-CMOS", Transactions on Electron Devices, IEEE, 1994, pp. 978-987, vol. 41, No. 6.|
|12||Momose et al., "Temperature Dependence of Emitter-Base Reverse Stress Degradation and its Mechanism Analyzed by MOS Structures", IEEE, Paper 6.2, 1989, pp. 140-143.|
|13||Ootsuka et al., "A Highly Dense, High-Performance 130nm Node CMOS Technology for Large Scale System-on-a-Chip Applications", International Electron Devices Meeting, IEEE, 2000, 23.5.1-23.5.4.|
|14||Ota et al., "Novel Locally Strained Channel Technique for High Performance 55nm CMOS", International Electron Devices Meeting, IEEE, 2002, pp. 27-30, 2.2.1-2.2.4.|
|15||Ouyang et al., "Two-Dimensional Bandgap Engineering in a Novel Si/SiGe pMOSFET With Enhanced Device Performance and Scalability," IEEE, 2000, pp. 151-154.|
|16||Rim et al., "Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs", Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2002, pp. 98-99.|
|17||Rim et al., "Transductance Enhancement in Deep Submicron Strained-Si n-MOSFETs", International Electron Devices Meeting, IEEE, 1998, 26.8.1-26.8.4.|
|18||Scott et al., NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress, International Electron Devices Meeting, IEEE, 1999, 34.4.1-34.4.4.|
|19||Sheng et al., "Degradation and Recovery of SiGe HBTs Following Radiation and Hot-Carrier Stressing", pp. 14-15.|
|20||Shimizu et al., "Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement", International Electron Devices Meeting, IEEE, 2001, 19.4.1-19.4.4.|
|21||Van De Leur et al., "Critical Thickness for Pseudomorphic Growth of Si/Ge Alloys and Superlattices", J. Appl. Phys., 1988, pp. 3043-3050, vol. 64, No. 6.|
|22||Van Der Merwe, "Regular Articles", Journal of Applied Physics, 1963, pp. 117-122, vol. 34, No. 1.|
|23||Wurzer et al. "Annealing of Degraded npn-Transistors-Mechanisms and Modeling", Transactions on Electron Devices, IEEE, 1994, pp. 533-538, vol. 41, No. 4.|
|24||Yang et al., "Avalanche Current Induced Hot Carrier Degradation in 200GHz SiGe Heterojunction Bipolar Transistors".|
|25||Zhang et al. "A New ‘Mixed-Mode’ Reliability Degradation Mechanism in Advanced Si and SiGe Bipolar Transistors", IEEE, 2002, pp. 2151-2156.|
|26||Zhang et al. "A New 'Mixed-Mode' Reliability Degradation Mechanism in Advanced Si and SiGe Bipolar Transistors", IEEE, 2002, pp. 2151-2156.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8236709 *||Jul 29, 2009||Aug 7, 2012||International Business Machines Corporation||Method of fabricating a device using low temperature anneal processes, a device and design structure|
|US8490029||Mar 15, 2012||Jul 16, 2013||International Business Machines Corporation||Method of fabricating a device using low temperature anneal processes, a device and design structure|
|US9105662||Jan 23, 2014||Aug 11, 2015||International Business Machines Corporation||Method and structure to enhance gate induced strain effect in multigate device|
|US9263587 *||Sep 4, 2014||Feb 16, 2016||Globalfoundries Inc.||Fin device with blocking layer in channel region|
|US9293464||May 6, 2015||Mar 22, 2016||International Business Machines Corporation||Structure to enhance gate induced strain effect in multigate devices|
|US9362311||Jul 24, 2015||Jun 7, 2016||Samsung Electronics Co., Ltd.||Method of fabricating semiconductor device|
|US9373706||Jan 20, 2015||Jun 21, 2016||Samsung Electronics Co., Ltd.||Methods of forming semiconductor devices, including forming a semiconductor material on a fin, and related semiconductor devices|
|US20110027956 *||Jul 29, 2009||Feb 3, 2011||International Business Machines Corporation||Method of Fabricating a Device Using Low Temperature Anneal Processes, a Device and Design Structure|
|US20150221751 *||Apr 16, 2015||Aug 6, 2015||Taiwan Semiconductor Manufacturing Company, Ltd.||Method of making a finfet device|
|U.S. Classification||438/517, 438/533, 438/528, 438/479, 438/530, 438/527|
|Cooperative Classification||H01L29/42384, H01L29/7842, H01L29/785, H01L29/66795|
|European Classification||H01L29/423D2B8, H01L29/78S, H01L29/66M6T6F16F, H01L29/78R|
|Jun 16, 2015||FPAY||Fee payment|
Year of fee payment: 4
|Jun 16, 2015||SULP||Surcharge for late payment|
|Sep 3, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001
Effective date: 20150629
|Oct 5, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001
Effective date: 20150910
|Feb 22, 2017||AS||Assignment|
Owner name: AURIGA INNOVATIONS, INC., CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:041777/0233
Effective date: 20161207