Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS8063623 B2
Publication typeGrant
Application numberUS 12/299,305
PCT numberPCT/EP2007/053968
Publication dateNov 22, 2011
Filing dateApr 24, 2007
Priority dateMay 3, 2006
Also published asCN101485088A, CN101485088B, EP2018704A1, US20090315532, WO2007128682A1
Publication number12299305, 299305, PCT/2007/53968, PCT/EP/2007/053968, PCT/EP/2007/53968, PCT/EP/7/053968, PCT/EP/7/53968, PCT/EP2007/053968, PCT/EP2007/53968, PCT/EP2007053968, PCT/EP200753968, PCT/EP7/053968, PCT/EP7/53968, PCT/EP7053968, PCT/EP753968, US 8063623 B2, US 8063623B2, US-B2-8063623, US8063623 B2, US8063623B2
InventorsAndy Negoi, Michel Zecri
Original AssigneeSynopsys, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Analog compensation circuit
US 8063623 B2
Abstract
The present disclosure relates to a compensation circuit for providing compensation over PVT variations within an integrated circuit. Using a low voltage reference current source, the compensation circuit generates directly, from an on-chip reference low voltage supply (VDD), a reference current (Iref) that is constant over PVT variations, whereas a detection current (Iz) that is variable over PVT variations is generated by a sensing circuit, which is based on a current conveyor, from a low voltage supply (VDDE−VDD) applied across a single diode-connected transistor (M10) corresponding to a voltage difference between two reference low voltage supplies. Both currents (Iref, Iz) are then compared inside a current mode analog-to-digital converter that outputs a plurality of digital bits. These digital bits can be subsequently used to compensate for PVT variations in an I/O buffer circuit.
Images(5)
Previous page
Next page
Claims(20)
1. A compensation circuit for providing compensation for one of process, voltage and temperature (PVT) variations within an integrated circuit, said compensation circuit comprising at least:
a reference circuit for generating a reference current that is constant over PVT variations, said reference circuit being configured to directly generate said reference current from a first voltage supply, which is internal to said integrated circuit and configured to provide a low voltage supply, wherein the generation of the reference current is based on a sum of a current having a positive temperature coefficient and another current having a negative temperature coefficient in order to compensate temperature change; and
a sensing circuit, which comprises an output terminal and which is configured to provide at said output terminal a detection current (Iz) that is variable over PVT variations, and to sense said PVT variations through said detection current.
2. A compensation circuit according to claim 1, wherein said reference circuit comprises:
a proportional-to-absolute-temperature (PTAT) circuit, which comprises a first diode element and a series arrangement of a second diode element and a second resistor, said first diode element and said series arrangement being configured to allow said PTAT circuit to exhibit a positive temperature coefficient (PTC) through a voltage difference across said second resistor between a voltage across said first diode element and a voltage across said series arrangement;
first and third resistive elements, which are respectively connected in parallel with said first diode element and said series arrangement, said first and third resistive elements being respectively passed through by a first current and a third current both exhibiting a negative temperature coefficient (NTC) by being proportional to said voltage across said first diode element;
a current mirror, which comprises a drive input and at least first, second, and third current sources being supplied by said first voltage supply and having first, second, and third transistors respectively, said current mirror being configured to replicate a fifth current that passes through said first transistor into a sixth current that passes through said second transistor, and said sixth current into said reference current that passes through said third transistor, said fifth current and sixth current being constant over PVT variations; and
an operational amplifier, which comprises at least a non-inverting input terminal and an inverting input terminal, said operational amplifier being connected to said current mirror and said PTAT circuit such that said non-inverting input terminal has a same voltage level as said voltage across said first diode element and said inverting input terminal has a same voltage level as that of said series arrangement, and configured to drive said current mirror through said drive input.
3. A compensation circuit according to claim 1, wherein said sensing circuit comprises:
a current conveyor for conveying a current from an input terminal towards said output terminal, said current conveyor further comprising a reference terminal, which is connected to a reference voltage supply; and
a diode-connected transistor for generating a low positive voltage drop across it, said diode-connected transistor being connected between a second voltage supply and said input terminal.
4. A compensation circuit according to claim 3, wherein said voltage drop is equal to a voltage difference between said second voltage supply and said reference voltage supply.
5. A compensation circuit according to claim 3, wherein said compensation circuit further comprises: an analog-to-digital converter, which is configured to provide at its output a plurality of digital bits based on a comparison between said reference current and said detection current.
6. A compensation circuit according to claim 5, wherein said compensation circuit further comprises: a buffer circuit, which is configured to receive at its input said plurality of digital bits.
7. A compensation circuit according to claim 1, wherein said first voltage supply is a digital core voltage supply.
8. A compensation circuit according to claim 4, wherein said reference voltage supply is said first voltage supply.
9. A compensation circuit according to claim 2, wherein said second diode element is a set of N parallel-connected diode elements, wherein N is an integer greater than unity.
10. A compensation circuit according to claim 2, wherein said fifth current is split into said first current and a fourth current that flows through said first diode element, and said sixth current is split into said third current and a second current that flows through said series arrangement.
11. A compensation circuit according to claim 2, wherein each one of said first and second diode elements is a diode-connected transistor.
12. A compensation circuit according to claim 3, wherein said current conveyor is a first generation current conveyor.
13. A method for providing compensation for at least one of process, voltage and temperature (PVT) variations within an integrated circuit, said method comprising at least the steps of:
generating a reference current which is constant over PVT variations, said reference current being generated directly from a first voltage supply, which is internal to said integrated circuit and configured to provide a low voltage supply, wherein the generation of the reference current is based on a sum of a current having a positive temperature coefficient and another current having a negative temperature coefficient in order to compensate temperature change; and
sensing PVT variations through a detection current which is variable over PVT variations, said detection current being provided by said sensing circuit.
14. A method according to claim 13, wherein said method further comprises the steps of:
comparing said reference current and said detection current; and
outputting a plurality of digital bits towards a buffer circuit for PVT compensation.
15. A method according to claim 13, wherein said sensing step comprises the steps of:
conveying a current from an input terminal at low impedance level towards an output terminal at high impedance level, said input terminal being at a voltage level equal to that of a reference voltage supply; and
generating a low positive voltage drop across a diode-connected transistor, said diode-connected transistor being connected between a second voltage supply and said input terminal.
16. A compensation circuit for providing compensation for one of process, voltage and temperature (PVT) variations within an integrated circuit, said compensation circuit comprising
a reference circuit means for generating a reference current that is constant over PVT variations, said reference circuit means being configured to directly generate said reference current from a first voltage supply, which is internal to said integrated circuit and configured to provide a low voltage supply, wherein the generation of the reference current is based on a sum of a current having a positive temperature coefficient and another current having a negative temperature coefficient in order to compensate temperature change; and
sensing circuit means comprising an output terminal, for providing at said output terminal a detection current (Iz) that is variable over PVT variations, and for sensing said PVT variations through said detection current.
17. A compensation circuit according to claim 16, wherein said reference circuit means comprises:
a proportional-to-absolute-temperature (PTAT) circuit, which comprises
a first diode element and a series arrangement of a second diode element and a second resistor, said first diode element and said series arrangement being configured to allow said PTAT circuit to exhibit a positive temperature coefficient (PTC) through a voltage difference across said second resistor between a voltage across said first diode element and a voltage across said series arrangement;
first and third resistive elements, which are respectively connected in parallel with said first diode element and said series arrangement, said first and third resistive elements being respectively passed through by a first current and a third current both exhibiting a negative temperature coefficient (NTC) by being proportional to said voltage across said first diode element;
a current mirror, which comprises a drive input and at least first, second, and third current sources being supplied by said first voltage supply and having first, second, and third transistors respectively, said current mirror being configured to replicate a fifth current that passes through said first transistor into a sixth current that passes through said second transistor, and said sixth current into said reference current that passes through said third transistor, said fifth current and sixth current being constant over PVT variations; and
an operational amplifier, which comprises at least a non-inverting input terminal and an inverting input terminal, said operational amplifier being connected to said current mirror and said PTAT circuit such that said non-inverting input terminal has a same voltage level as said voltage across said first diode element and said inverting input terminal has a same voltage level as that of said series arrangement, and configured to drive said current mirror through said drive input.
18. A compensation circuit according to claim 16, wherein said sensing circuit means comprises:
a current conveyor for conveying a current from an input terminal towards said output terminal, said current conveyor further comprising a reference terminal, which is connected to a reference voltage supply; and
a diode-connected transistor for generating a low positive voltage drop across it, said diode-connected transistor being connected between a second voltage supply and said input terminal.
19. A compensation circuit according to claim 18, wherein said voltage drop is equal to a voltage difference between said second voltage supply and said reference voltage supply.
20. A compensation circuit according to claim 18, wherein said compensation circuit further comprises: an analog-to-digital converter means, which is configured to provide at its output a plurality of digital bits based on a comparison between said reference current and said detection current.
Description

The present invention relates to an analog compensation circuit, and more particularly to a very low power analog compensation circuit for providing compensation over process, voltage and temperature (PVT) variations within an integrated circuit.

Output buffer circuits (e.g., input/output (I/O) circuits), are widely used to facilitate the transfer of data and/or signals from a component to another component within a given chip or from a chip to another chip, while being routed using links or transmission lines such as buses, printed circuit board (PCB) traces, or any other electrically conductive similar structures.

Due to the ever-increasing speed of the integrated circuits (IC), these links behave nowadays as transmission lines, the characteristic impedance (typically ranged from 50 to 75 ohms) of which will be required to continuously match the impedance of the output buffer circuits or transmitters, in order to avoid the undesirable reflections and ringing which result in reduced noise immunity and timing skew.

However, a buffer circuit may be subjected to variations in supply voltage, manufacturing process and temperature (PVT). For example, process variations resulting from IC fabrication can affect the threshold voltage, channel length and width, doping, carrier mobility, and so one. These variations are thus unavoidable and result in departure from optimal performance of the buffer circuits, such that PVT compensation techniques are required.

Moreover, the performance will be also detracted by the dynamic power consumption in the buffer circuits which directly depends on the capacitive switching operation, as well as the interferences through the ground and supply lines caused by any fast and simultaneous switching operation.

Several prior art solutions have been devised to compensate for PVT variations in a buffer circuit. For example, U.S. Pat. No. 6,087,853 entitled “Controlled Output Impedance Buffer Using CMOS Technology” describes a way to sense the PVT condition and match the output impedance of each output buffer circuit within an output buffer driver to the impedance of a transmission line by switching on or off various output buffer circuits. The detection of the PVT condition is made by injecting a PVT-independent reference current through a transistor of a predefined size before converting the resulting drain-source voltage into a digital code. However, this approach has the disadvantage of consuming a lot of energy through the voltage conversion and generating the reference current in a manner that is weakly versatile.

Another example can be given by U.S. Pat. No. 2002/0109490A1 entitled “Reference Current Source Having MOS Transistors”, which describes a way to produce a reference current by adding two other currents that depend on the PVT condition in a reverse manner. However, this approach still presents several disadvantages. It consumes not only a lot of energy through the use of two voltage sources and a voltage-to-current converter, but also area through the use of integrated resistors for generating the reference current. Additionally, these integrated resistors have very often a large variation under modem processes.

FIG. 1 illustrates a block diagram of a compensation circuit 10 for a buffer circuit 15 such as commonly found in the prior art. A reference voltage generator 11 generates from an external power supply (Vext) a reference voltage which is converted into a reference current through a voltage-to-current converter 12. The reference current is then compared through an analog-to-digital converter 14 to a current, which is variable over PVT variations and supplied by a current generating means 13. The most used way to generate such a reference current is to use a bandgap type voltage reference block providing a bandgap reference voltage of less than 1.21 V that is constant over PVT variations, in addition to an integrated resistor or high precision external resistor for allowing conversion into current. However, integrated resistors usually exhibit a large variation in the modern processes and cover a lot of space on the chip. Using high precision or trimmed external resistors also present the disadvantage of increasing production costs.

It is therefore preferred to provide a very low power analog compensation circuit for providing compensation over process, voltage and temperature (PVT) variations within an integrated circuit and for a buffer circuit in particular.

In a first aspect, the invention provides a compensation circuit for providing compensation for at least one of process, voltage and temperature (PVT) variations within an integrated circuit, said compensation circuit comprising at least:

a) a reference circuit for generating a reference current (Iref) that is constant over PVT variations, said reference circuit being configured to directly generate said reference current (Iref) from a first voltage supply (VDD), which is internal to said integrated circuit and configured to provide a low voltage supply;

b) a sensing circuit, which comprises an output terminal (Z) and which is configured to provide at said output terminal (Z) a detection current (Iz) that is variable over PVT variations, and to sense said PVT variations through said detection current (Iz).

The compensation circuit according to the first aspect of the invention comprises a reference circuit for directly generating from a first voltage supply, which is an on-chip low voltage supply, a reference current that is constant over PVT variations. Thereby, a bandgap type voltage reference block for generating a bandgap reference voltage as well as an integrated or high precision external resistor for converting said bandgap reference voltage into a reference current, are not needed, which enables to save energy, silicon area on the chip and cost.

The compensation circuit according to the first aspect of the invention further comprises a sensing circuit for sensing PVT variations through a detection current generated by this sensing circuit. Thereby, PVT variations can be detected.

In a second aspect, the invention provides a method for providing compensation for at least one of process, voltage and temperature (PVT) variations within an integrated circuit, said method comprising at least the steps of:

a) generating a reference current (Iref) which is constant over PVT variations, said reference current (Iref) being generated directly from a first voltage supply (VDD), which is internal to said integrated circuit and configured to provide a low voltage supply;

b) sensing PVT variations through a detection current (Iz) which is variable over PVT variations, said detection current (Iz) being provided by said sensing circuit.

In the following, advantageous embodiments will be described, which are also defined in the dependent claims. The embodiments can be combined with each other, unless explicitly stated otherwise.

Thus, the reference circuit may comprise at least a proportional-to-absolute-temperature (PTAT) circuit having a first diode element and a series arrangement of a second diode element and a second resistor, which are configured in such a manner that a voltage difference across said second resistor between a voltage across said first diode element and a voltage across said series arrangement exists. Thereby, a positive temperature coefficient (PTC) current can be generated through said first and second diode elements.

Moreover, said first and second diode elements may alternatively be diode-connected transistors, and said second diode element may additionally be replaced by a set of several parallel-connected diode elements for enabling a distribution of the second current that flows through said second diode element.

The reference circuit further preferably comprises first and third resistive elements, which are configured in such a manner that a negative temperature coefficient (NTC) current can be generated through said first and third resistive elements.

In another embodiment, the reference circuit further comprises a current mirror being supplied by said reference voltage and having at least three transistors for mirroring a fifth current that is constant over PVT variations into a sixth current that is constant over PVT variations, which is in turn mirrored for thereby generating said reference circuit.

In a further embodiment, the reference circuit further comprises an operational amplifier with at least two complementary input terminals, which is configured to drive said current mirror through the drive input of the transistors that form said current mirror. Due to high impedance of the drive input, said two complementary input terminals will be thereby maintained at a same voltage potential.

Moreover, the sensing circuit may comprise a current conveyor, such as a first generation current conveyor, having its reference terminal connected to said first voltage supply or a suitable reference voltage, and a diode-connected transistor connected between the input terminal of said current conveyor and a second voltage supply. Due to the well-known current conveyor configuration, said input and reference terminals will be virtually shorted for thus generating a low voltage difference across said single diode-connected transistor that will be then passed through by a low current. This current will be sufficiently low in order to not need to be restricted using a series arrangement of several diode-connected transistors, whose variation range of the process parameters (threshold voltage, carrier mobility, etc.) is rather large. Furthermore, since the influence of the process parameters, supply voltage, and temperature is monitored by said single diode-connected transistor, the power consumption of said current conveyor will be drastically reduced.

The compensation circuit may further comprise an analog-to-digital converter for thus comparing said reference and said detection currents between each other and converting the result into a multi-bit compensation code.

This compensation code may then be used by a buffer circuit for allowing it to adapt its driving strength.

The present invention will be now described based on preferred embodiments with reference to the accompanying drawings in which:

FIG. 1 shows a block diagram of a compensation circuit for a buffer circuit according to the prior art;

FIG. 2 shows a block diagram of a compensation circuit for a buffer circuit according to a preferred embodiment of the invention;

FIG. 3 shows a schematic diagram of a reference current source such as used in the compensated buffer circuit of FIG. 2;

FIG. 4 shows a schematic diagram of a sensing circuit based on a current conveyor such as used in the compensated buffer circuit of FIG. 2.

FIG. 2 is a block diagram of a compensation circuit 100 for a buffer circuit 500 according to a preferred embodiment of the invention. A reference current Iref, which is by definition a current constant over PVT variations, is directly generated by a low power reference current source 200 from a reference low voltage supply VDD, such as the digital core voltage supply, for example, which is present on every integrated circuit with a constant value ranging around 1.0 V. A detection current Iz, which is a current variable over PVT variations, is generated by a sensing circuit 300, the configuration of which is based on a current conveyor 310, from a low voltage supply (VDDE−VDD) corresponding to a voltage difference ΔV between a reference high voltage supply VDDE, such as a high input/output (I/O) voltage supply for example ranging between 1.8 V and 2.5 V, and the lower voltage supply VDD. Both analog currents Iref, Iz are subsequently compared at any time through a plurality of comparators inside a current mode analog-to-digital converter (ADC) 400 that may be a parallel analog-to-digital converter, such as a flash converter for example, and outputs a plurality of digital bits for constituting a PVT compensation code. Such a code can thus be used by a pre-driver and output section (not shown) of an I/O buffer circuit 500 in order to control, for example, output impedance and/or slew rate.

FIG. 3 depicts a schematic diagram of a reference current source 200 such as used in the compensation circuit 100 according to the preferred embodiment of the invention. Such a reference current source 200 includes at least a current mirror circuit 220 made up of first, second, third, and fourth transistors M1, M2, M3, and M4 having identical polarity and wherein the first, second, and third transistors M1-M3 have an aspect ratio (W/L, W and L representing the channel width (W) and length (L) respectively) that is identical to each other but different with respect to the fourth transistor M4, a proportional-to-absolute-temperature (PTAT) circuit 230 consisting of a first diode D1 and a second resistor R2 in series with and a second diode D2, each of these diodes being differently sized with a ratio of the area of diode D2 to the area of diode D1 equal to N, first and third resistors R1 and R3, and an operational amplifier 210 that may be a CMOS amplifier, namely designed using CMOS transistors, in order to minimize power consumption.

The operational amplifier 210, which is self-biased by the fourth transistor M4, drives the current mirror circuit 220 through its output terminal OUT that is coupled to the gate terminals G of the four transistors M1-M4. The operational amplifier 210 has two complementary input terminals, namely a non-inverting input terminal IN+ at a voltage potential Vin+ and an inverting input terminal IN− at a voltage potential Vin−. The first resistor R1, which is connected in parallel across the first diode D1, has a first terminal connected to the non-inverting terminal IN+ and a second terminal connected to a negative power supply terminal, which may be at VSS. The first diode D1 has its anode terminal connected to the non-inverting terminal and its cathode terminal connected to VSS. The second resistor R2, which is in series with the second diode D2, has a third terminal connected to the inverting input terminal IN− and a fourth terminal connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to VSS. The third resistor R3 is connected in parallel across the branch (R2, D2), i.e. between the third terminal and VSS. The source S of each of the four transistors M1-M4 is connected to a positive power supply terminal, which may be at a constant reference level, such as VDD. The drain of the first transistor M1 is connected to the non-inverting input terminal IN+, whereas the drain of the second transistor M2 is connected to the inverting input terminal IN−. The current I1 that flows through the first transistor M1 is split into a current I1a through the first diode D1 and a current I1 b through the first resistor R1. The current I2 that flows through the second transistor M2 is split into a current I2a through the series branch (R2, D2) and a current I2b through the third resistor R3. Due to the current mirror arrangement with transistors M1-M4 having the same aspect ratio (W/L), the transistors M1-M2 source the same amount of currents I1, I2 which is mirrored to the third transistor M3, such that the output current Iref is identical to I1 and I2.

The principle of this reference current source 200 lies on the generation of a reference current Iref that is both the sum (I1a+I1b, I2a+I2b) of a current I1a, I2a having a positive temperature coefficient (PTC) and another current I1b, I2b having a negative temperature coefficient (NTC) in order to compensate temperature change.

The current If that flows through a forward-biased diode can be given by the well-known Shockley ideal diode equation, according to as follows:

I f = I s ( V f V T - 1 ) ( 1 )

where Is is called saturation current, Vf is the voltage across the forward-biased diode which has a negative temperature coefficient (NTC), and VT is the thermal voltage which exhibits a positive temperature coefficient (PTC) as defined by the following dependence relation with the temperature T:

V T = kT q ( 2 )

where q is the elementary charge (1.602×10−19 C), k is Boltzmann's constant (1.3807×10−23 J/K), and T is the absolute temperature of the P-N junction of a diode.

Due to the fact that VT can usually be neglected with respect to the voltage Vf, equation (1) can further be approximated as:

I f I s ( V f V T ) V f V T ( 3 )

from which we can derive the voltage Vf given by:

V f = V T ln I f I s ( 4 )

The equality between the currents I1 and I2 can be expressed as:
I 1a +I 1b =I 2a +I 2b  (5)

During operation, the operational amplifier 210 forces its two complementary input terminals IN+ and IN− to a same voltage potential in the steady state, which yields:
Vin+=Vin−  (6)

According to conventional practice and easier manipulation of the numbers, the resistors R1 and R3 will be also set equal to each other, such that:
R1=R3  (7)

Under these conditions, we obtain:
I1b=I2b  (8)

Reporting equation (8) into equation (5), it results that:
I1a=I2a  (9)

As illustrated in FIG. 3 and using equation (4), we get:

V i n - = V i n + = V f 1 ( 10 ) I 1 a = I 2 a = Δ V f R 2 = V f 1 - V f 2 R 2 = V T ln ( N I 1 a I 2 a ) R 2 = V T ln ( N ) R 2 ( 11 ) I 1 b = I 2 b = V f 1 R 3 = V T ln ( I 1 a I s ) R 3 ( 12 )

where Vf1 is the voltage across the forward-biased diode D1, Vf2 is the voltage drop across the forward-biased diode D2, and N is the ratio of the area of diode D2 to the area of diode D1. It is also noted that the diode D2 may be replaced by a set of N parallel-connected diodes D2 i having the same size as the diode D1, such that each of the diodes D2 i is passed through by a current equal to I2a/N, with N being an integer at least equal to two.

From equation (11), it can be seen that the currents I1a or I2a that are provided by the PTAT circuit 230 exhibit a positive temperature coefficient (PTC) while being a function of the difference ΔVf, also called voltage proportional to absolute temperature (VPTAT), between the forward-biased voltages Vf1 and Vf2, which is proportional to the thermal voltage VT.

From equation (12), it can be seen that the currents I1b or I2b are a function of the forward-biased voltage Vf1 that exhibits a negative temperature coefficient (NTC) while having its voltage Vf1 decreasing with increasing temperature.

Thus, the PTC of ΔVf and NTC of the built-in voltage Vf are compensated, such that the reference current source 200 outputs a temperature-compensated reference current Iref(=I1a+I1b=I2a+I2b) from its output terminal REF.

Moreover, such a reference current source 200 shows a sensitivity with respect to changes in process parameters that is quite low.

Additionally, the positive power supply that provides a constant reference voltage VDD will be preferably an internal low voltage supply, such as the digital core voltage supply, for example, which is present on-chip, namely on every integrated circuit, with a constant value ranging usually around 1.0 V.

Finally, the reference current source 200 can be considered as a low voltage bandgap current reference circuit outputting a reference current Iref that is independent of the PVT variations.

It should be noted that the term “diode” is being used herein to denote any device that behaves like a forward-biased semiconductor P-N junction device. A typical example of such a device would be a diode-connected dynamic threshold channel-P metal oxide semiconductor field effect transistor (P-MOSFET) with the n-well connected to the gate, short-circuiting the gate, n-well, and drain to ground and the source of said P-MOSFET being the anode, or the collector and the base of a bipolar junction transistor (BJT).

It should additionally be noted that although the transistors M1-M4 shown in FIG. 3 are of type channel-P metal oxide semiconductor (PMOS) transistors, channel-N metal oxide semiconductor (NMOS) transistors could also be used while reversing the direction of current flow and polarity of the remainder of the circuit 200.

It should furthermore be noted that the transistors M1-M4 shown in FIG. 3 will be preferably transistors designed for low-voltage operation, namely exhibiting reduced threshold voltages, such as native transistors for example.

FIG. 4 illustrates a schematic diagram of a sensing circuit 300 such as used in the compensation circuit 100 according to the preferred embodiment of the invention. Such a low power sensing circuit 300 is based on a current conveyor 310, such as a first generation current conveyor (CCI) wherein the node Y is a finite impedance node with a current Iy flowing into it. The node Y is connected to a positive power supply terminal which may be at a constant reference level such as VDD for example. A diode-connected transistor M10, which has the same polarity as the diode-connected transistor M8 and transistor M7, is connected between the node X and another positive power supply terminal at VDDE, which will be higher than VDD (±1.0 V) while being ranged, for an Input/Output supply voltage for example, between 1.8 V and 2.5 V. Due to the current mirror arrangement formed by the transistors M5, M6 and M9 having the same aspect ratio (W/L) and a reverse polarity with respect to the diode-connected transistor M10, the current Ix that flows through the transistors M10, M7, M6, the current Iy that flows through the transistors M8, M5, and the detection current Iz that flows through the transistor M9 are all identical, and this regardless of the voltage potential being applied at node Y. The diode-connected transistor M8, that is passed through by the same current as the transistor M7 whose size is identical, will then guarantee that the voltage VGS across the source and gate terminals is the same for both transistors M8, M7, which share the same gate terminal G and thus form a current mirror. Since the source terminal S of the diode-connected transistor M8 is also connected to the node Y, it results that the node X will be at the same voltage potential as the node Y, namely that the nodes X and Y will be as virtually short-circuited. It should be noted that the virtual voltage potential appearing at node X will not be affected by the value of the current Ix, such that the first generation current conveyor (CCI) has a zero input impedance. Finally, a low voltage difference ΔV between both positive power supplies at VDDE and VDD is applied across the single diode-connected transistor M10, such that it is passed through by a low level of current Ix and it is hence not necessary to have a series arrangement of several diode-connected transistors for reasonably reducing this current Ix. The influence of the process parameters (threshold voltage, carrier mobility, . . . ), supply voltage, and temperature is then monitored by the single diode-connected transistor, such that the power consumption of said current conveyor will be drastically reduced. The low current Ix, which is sourced from the node X at a low impedance level, is then replicated into the detection current Iz, which is dependent on PVT variations and supplied by the transistor M9 from the node Z at a high impedance level to the current mode ADC 400.

It should be noted that although the first group of transistors M7, M8, M10 shown in FIG. 4 is of type PMOS transistors, and the second group of transistors M5, M6, M9 is of type NMOS transistors, implementation of such transistor groups can also be carried out with a reverse polarity, while inverting the direction of current flow and polarity of the remainder of the circuit 300.

Furthermore, it should be noted that the present invention is not limited to any particular buffer circuit. Rather, the invention is more generally applicable to any circuit arrangement in which it is desirable to provide improved compensation techniques for accurately compensating for at least process, voltage and temperature variations in the circuit.

In summary, a compensation circuit 100 for providing compensation over process, voltage and temperature (PVT) variations within an integrated circuit has been described. Using a low voltage reference current source 200, the compensation circuit 100 generates directly, from an on-chip reference low voltage supply VDD, a reference current Iref that is constant over PVT variations, whereas a detection current Iz that is variable over PVT variations is generated by a sensing circuit 300, which is based on a current conveyor 310, from a low voltage supply (VDDE−VDD) applied across a single diode-connected transistor M10 corresponding to a voltage difference between two reference low voltage supplies. Both currents Iref, Iz are then compared inside a current mode analog-to-digital converter 400 that outputs a plurality of digital bits. These digital bits can be subsequently used to compensate for PVT variations in an I/O buffer circuit 500.

When interpreting the present description and its associated claims, expressions such as “comprise”, “include”, “incorporate”, “contain”, “is”, and “have” are to be construed in a non-exclusive manner, namely construed to allow for other items or components, which are not explicitly defined, also to be present. Reference to the singular is also to be construed to be a reference to the plural and vice versa.

Furthermore, the invention may also be embodied with less components than provided in the embodiments described here, wherein one component carries out multiple functions. Just as well may the invention be embodied using more elements than depicted in the Figures, wherein functions carried out by one component in the embodiment provided are distributed over multiple components.

A person skilled in the art will readily appreciate that various parameters disclosed in the description may be modified and that various embodiments disclosed and/or claimed may be combined without departing from the scope of the invention.

It is stipulated that the reference signs in the claims do not limit the scope of the claims, but are merely inserted to enhance the legibility of the claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5047670Sep 6, 1990Sep 10, 1991Texas Instruments IncorporatedBiCMOS TTL input buffer
US6087853Jun 22, 1998Jul 11, 2000Lucent Technologies, Inc.Controlled output impedance buffer using CMOS technology
US6556022Jun 29, 2001Apr 29, 2003Intel CorporationMethod and apparatus for local parameter variation compensation
US6697283 *Aug 27, 2002Feb 24, 2004Micron Technology, Inc.Temperature and voltage compensated reference current generator
US7336117 *Jul 14, 2006Feb 26, 2008Stmicroelectronics S.R.L.Enhancement of power on reliability in a dual power supply digital device with down converter
US20020109490Aug 30, 2001Aug 15, 2002Bernhard EnglReference current source having MOS transistors
US20020130684May 17, 2002Sep 19, 2002U.S. Philips CorporationCMOS output amplifier independent of temperature, supply voltage and manufacturing quality of transistors
US20030169081Mar 5, 2002Sep 11, 2003Zhigang HanImpedance controlled double data rate input buffer
US20050134364Dec 23, 2003Jun 23, 2005Dipankar BhattacharyaReference compensation circuit
EP0184875A1Nov 19, 1985Jun 18, 1986Philips Electronics N.V.Adaptive electronic buffer amplifier system
JPH061899A Title not available
Non-Patent Citations
Reference
1A Delay-Based PVT Detection Mechanism Sep. 21, 2005.
2Australian Patent Office, Examination Report dated Dec. 8, 2009 for Singapore patent application No. SG 200808099-6.
3European Patent Office, Communication pursuant to Article 94(3) EPC dated Sep. 24, 2009 for European patent application No. 07728424.8.
4ISA/EP, International Search Report and Written Opinion dated Oct. 18, 2007 for international application No. PCT/EP2007/053968.
5Korean Patent Office, English translation of the Notice of Preliminary Rejection for Korean Office action dated Jul. 13, 2010 for Korean patent application No. 2008-7029458.
6The International Bureau of WIPO, International Preliminary Report on Patentability dated Nov. 4, 2008 for international application No. PCT/EP2007/053968.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8159262 *Feb 18, 2011Apr 17, 2012Dipankar BhattacharyaImpedance compensation in a buffer circuit
US8531243Feb 9, 2012Sep 10, 2013Samsung Electro-Mechanics Co., Ltd.Bias controlling apparatus
US20110255568 *Jun 30, 2011Oct 20, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Thermal sensors and methods of operating thereof
Classifications
U.S. Classification323/312, 323/907
International ClassificationG05F3/04
Cooperative ClassificationY10S323/907, H03K19/00384
European ClassificationH03K19/003K4
Legal Events
DateCodeEventDescription
Nov 6, 2013ASAssignment
Effective date: 20131101
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031591/0266
Jun 18, 2013ASAssignment
Effective date: 20130521
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030633/0424
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR
Nov 5, 2012ASAssignment
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEGOI, ANDY C.;REEL/FRAME:029243/0273
Effective date: 20120523
Owner name: NPX B.V., NETHERLANDS
Oct 8, 2010ASAssignment
Owner name: SYNOPSYS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VIRAGE LOGIC CORPORATION;VL C.V.;ARC CORES LIMITED;AND OTHERS;REEL/FRAME:025105/0907
Effective date: 20100902
May 13, 2010ASAssignment
Owner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100518;REEL/FRAME:24397/1
Effective date: 20100413
Owner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100521;REEL/FRAME:24397/1
Effective date: 20100413
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:24397/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:24397/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001
Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK
Apr 23, 2010ASAssignment
Owner name: VL C.V.,CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NXP B. V;US-ASSIGNMENT DATABASE UPDATED:20100423;REEL/FRAME:24278/84
Effective date: 20091116
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NXP B. V;REEL/FRAME:024278/0084
Owner name: VL C.V., CALIFORNIA
Mar 15, 2010ASAssignment
Owner name: CITIBANK, N.A.,NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100323;REEL/FRAME:24085/1
Effective date: 20100219
Owner name: CITIBANK, N.A.,NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100317;REEL/FRAME:24085/1
Effective date: 20100219
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100318;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100325;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100329;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100330;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100401;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100406;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100408;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100413;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100415;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100420;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100422;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100429;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100504;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100511;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100513;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100518;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:24085/1
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024085/0001
Owner name: CITIBANK, N.A., NEW YORK
Mar 12, 2009ASAssignment
Owner name: CITIBANK, N.A.,NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100304;REEL/FRAME:22380/409
Effective date: 20090216
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100311;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100323;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100330;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100401;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100408;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100413;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100415;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100422;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100429;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100513;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100520;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:22380/409
Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:022380/0409
Owner name: CITIBANK, N.A., NEW YORK