|Publication number||US8065583 B2|
|Application number||US 11/774,377|
|Publication date||Nov 22, 2011|
|Filing date||Jul 6, 2007|
|Priority date||Jul 6, 2007|
|Also published as||US8239725, US20090013234, US20120042225, WO2009009303A2, WO2009009303A3|
|Publication number||11774377, 774377, US 8065583 B2, US 8065583B2, US-B2-8065583, US8065583 B2, US8065583B2|
|Inventors||William H. Radke|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (34), Non-Patent Citations (8), Referenced by (83), Classifications (10), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is related to commonly-owned and copending application titled ERROR RECOVERY STORAGE ALONG A NAND-FLASH STRING, Ser. No. 11/777,316, filed on the same date as the present application, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
Embodiments of the invention generally relate to integrated circuits. In particular, embodiments of the invention relate to memory circuits.
2. Description of the Related Art
Flash memory is a form of erasable and reprogrammable non-volatile memory. In a flash memory, memory cells are arranged in “blocks” for erasure. After a block has been erased, it is ready for programming if desired. NOR flash memory is a type of flash memory that offers access to individual bytes for retrieval of data, but has relatively low density.
NAND flash memory is a type of flash memory that offers relatively high density. The high density is achieved in part by forming columns of cells connected in series. In addition, with NAND flash memory, data is programmed and accessed in relatively large groups of bytes, such as a page of data. For example, a page can correspond to a row or to a portion of a row in an array.
For example, a memory array of cells for storing data is typically arranged in a 2-dimensional array of rows and columns. These arrays can vary greatly in size. When the cells of the array are capable of holding 2 or more levels, that is, multiple levels or two or more bits of data per cell, the array effectively holds data in 3 dimensions.
In a typical array for NAND flash memory, sources and drains of flash cells are arranged in series (source to drain) and referred to as columns. Along rows are “word lines” that control the gates of cells. Data is typically accessed a row at a time, with one bit from each column. The word line for the row to be read is set to a particular voltage for reading the stored state(s) of the cells. Different voltage levels can be used for multiple-level cells. The other row lines for the other cells of the columns are set to turn “on” the cells to permit the reading of the stored state(s) of the cells of the row through the corresponding cells in the columns.
The number of bytes per row can vary in a very wide range as can the number of bytes in a “page.” Some manufacturers define a page by a certain amount of data, so that, for example, two pages of data can correspond to one word line (row). For the purposes described herein, a “page” of data corresponds to the amount of data that is written to or read from the NAND flash memory array during a write cycle or read cycle. In one example, 2,112 bytes are retrieved by activation of a word line. Of these 2,112 bytes, 2,048 are data bytes and 64 are spare bytes, which are typically used for error correction codes (ECC), wear-leveling information, logical address mapping, or other overhead data. Error correction codes increase the robustness of the stored data. Typically, a form of block code is used to generate the error correction codes, such as cyclic redundancy check (CRC) checksums, Reed-Solomon error correction, or the like. These error correction codes detect if there were errors in the reading of the data bytes and can typically correct errors in the data bytes provided that the errors do not exceed the capability of the error correction code.
Flash memory has many uses. Examples include flash memory hard drives (replacements for hard drives), USB flash drives or thumb drives, mobile phones, digital cameras, digital media players, games, memory cards, navigation devices, personal digital assistants, computers, or the like. Within limits, the error correction codes can correct many errors in the data in the data bytes. However, beyond these limits, data with errors cannot typically be corrected. For example, if a word line fails, then there can be problems reading data for the entire row. This typically results in too many errors for the error correction codes to correct. Depending on the criticality of the data, the effects of uncorrectable errors in data can range from inconvenient to catastrophic.
These drawings and the associated description herein are provided to illustrate specific embodiments of the invention and are not intended to be limiting.
Although particular embodiments are described herein, other embodiments of the invention, including embodiments that do not provide all of the benefits and features set forth herein, will be apparent to those of ordinary skill in the art.
In one embodiment, the memory array 110 corresponds to a NAND flash memory array. The NAND flash memory array can be of single level, multi-level, or can even correspond to multiple arrays. While particular embodiments will be described in the context of NAND flash memory, the principles and advantages described herein are applicable to other types of memories. A very wide range of non-volatile solid state memory types can be used for the memory array 110. For example, the memory array 110 can correspond to other forms of flash (e.g., NOR type), electrically erasable programmable read only memory (EEPROM), magnetoresistive random access memory (MRAM), programmable conductor memory, ferroelectric memory, and the like.
The block code coder 106 generates the outer block code. The stream-based code coder 108 generates the inner stream-based code, e.g., convolutional code. The stream-based code decoder 112 decodes the inner stream-based code, and the block code decoder 114 decodes the outer block code. The concatenation of the outer block code and the inner stream-based code improves the integrity of the stored data and increases the likelihood of recovering correctable data. For example, the use of the inner stream-based code can lower the bit error rate (BER) associated with the memory device 100. The reduction in the BER is observed by the device using the memory device 100, such as a host or the CPU 102.
The CPU 102 or controller provides data to the write buffer 104 for storage to the memory array 110. Typically, for NAND flash, a page of data is written to the memory array 110 at a time. This page of data can vary in size. Typical page sizes include, but are not limited to, 512 bytes, 1024 bytes, 2048 bytes, and the like. In the schematic, a variable N represents the number of bytes for a page.
This N number of bytes is encoded by the block code coder 106. Examples of block codes include, but are not limited to, a Hamming code, a Reed-Solomon error correction code, a Bose, Chaudhuri, Hocquenghem (BCH) code, or the like. Within limits, these block error correction codes can detect and correct many errors in the data. The error correction codes from the block codes occupy additional bytes represented in
In the illustrated embodiment, the stream-based code coder 108 performs a stream-based coding process on the N+y bytes of data. The stream-based coding increases the amount of data stored by a factor z such that z(N+y) bytes are stored in the memory array 110 for the concatenated page of data. With stream-based coding, the resulting z(N+y) bytes are typically unique from the original N or N+y bytes of data, i.e., the N or N+y bytes of data are not recognizable without decoding. This can render decoding relatively difficult as compared to decoding of block codes. However, techniques such as the Viterbi algorithm can be used to decode convolutional codes in a relatively efficient manner.
This factor z can vary. For example, the code rate (m/n) and the constraint length k for a convolutional code can affect the size of the factor z. The factor z can vary in a very broad range, but will be greater than 1. In one embodiment, the stream-based code is a convolutional code, and the factor z is 2. A simple convolutional coding example will be described later in connection with
For clarity, familiar components such as buffers, row decoders, sense/amplifier circuits and the like are not shown in
The block code decoder 114 decodes the z(N+y) bytes of block-coded data and generates N bytes of corrected data (unless the errors are uncorrectable). The N bytes of corrected data are placed in the read buffer 116 for access by the CPU 102.
Data 204 indicates the N+y bytes of data from the block code coder 106 that would normally be stored in a conventional memory device. Data 206 indicates the convolutional coded z(N+y) bytes of data generated by convolution coding of data 204. In the simple example, data 204 is convolved using a register 208 and an exclusive-OR (XOR) gate 210.
In the illustrated example, the lower number bits are written earlier than the higher numbered bits. The register 208 can be initialized to zero for the first data bit (first memory cell of the string), or can be initialized to one.
The memory device 302 is operatively coupled to a controller 304, which is in communication with a host 306. For example, the host 306 and the controller 304 can be of a legacy specification. The controller 304 can be part of the host 306 or can be part of the memory device 302. For example, in the context of memory cards, e.g., SmartMedia, Secure Digital, or the like, some memory card formats specify the controller 304 to be onboard the memory device 302, while other formats specify the controller 304 to be part of the host 306.
In the illustrated example, the memory device 302 includes the stream-based code coder 108, the memory array 110, and the stream-based code decoder 112. These components were described earlier in connection with
While it may appear that the allocation of available memory space for additional error correction would be counter productive to the low-cost production of memory chips at low cost, the reverse can be true in certain situations. One example is compatibility with relatively old, i. e., legacy, memory system requirements.
The difference in density between a relatively new memory array and a relatively old memory array can be fairly dramatic. For example, the geometry feature size of a relatively new memory array is about ⅓ of that of a relatively old memory array. This increases the chip density by a factor of about 10. However, as the individual memory cells shrink, they also typically become individually less reliable and more susceptible to noise. This can render relatively new memory devices with small geometry unusable with the legacy specifications. With the legacy amount of error correction coding, the relatively small geometry devices would typically fail the bit error rate (BER) specification. This problem can be addressed by changing a specification to increase the amount of block coding; however, the increase in block coding would then negate compatibility with an existing specification.
One embodiment transparently applies the inner stream-based code to the block-coded data such that a host is unaware that a stream-based code is being used. This advantageously permits a relatively new and low-cost memory device to meet the bit error rate (BER) requirements while outwardly using only the block coded data specified for a legacy device. For example, even if half of the memory capacity were to be used, a small-geometry memory device of about 10 times the density would still be about 5 times more dense and thus cheaper than a larger-geometry device. This can further permit a manufacturer to build products for a wider range of product lines from relatively fewer production lines.
In one embodiment, the stream-based code coder 108 initiates the coding process after the page of data has been loaded into the second page latch 404. An indication, such as a “program page” signal can be used to indicate the readiness of the data. For an ordinary memory device, the program page signal from the host 306 or controller 304 (
For a page of N data bytes, the second page latch 404 typically stores N+y data bytes. Advantageously, as the N+y data bytes are stored in the second page latch 404, the memory device 302 can receive the data bytes for the page without a specific order. After the data for the page has been received, the stream-based code coder 108 encodes the N+y data bytes to the z(N+y) bytes with stream-based coding, such as convolutional coding. These z(N+y) bytes are stored in the first page latch 402 for writing to the memory array 110.
One embodiment is an apparatus, wherein the apparatus includes: one or more memory arrays for storage of data; a stream-based coder configured to generate a page of forward error correction coded data of a page of original data intended for storage in the one or more memory arrays such that the coded page of data is larger than the page of original data and such that the original data is not recognizable in the coded data without decoding the coded data; a page latch operatively coupled to the stream-based coder, wherein the page latch is at least large enough to hold the page of coded data for writing to the one or more memory arrays; and a stream-based decoder configured to decode coded data retrieved from the one or more memory arrays to generate decoded data.
One embodiment is a method for storing data in a device having one or more memory arrays, wherein the method includes: receiving block-coded data for storage in the one or more memory arrays; concatenating the block-coded data with a forward error correction code to generate a concatenated code that is larger in size than the original block-coded data; and storing the concatenated code in the one or more memory arrays.
One embodiment is a method of retrieving a first data stored in a memory device, wherein the method includes: receiving a request for the first data; retrieving a concatenated data from one or more memory arrays, wherein the concatenated data corresponds to the first data and a first block code of the first data concatenated with a second forward error correction code; and decoding the concatenated data to generate the first data and block codes.
Various embodiments have been described above. Although described with reference to these specific embodiments, the descriptions are intended to be illustrative and are not intended to be limiting. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined in the appended claims.
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|U.S. Classification||714/752, 714/746, 714/758|
|Cooperative Classification||H03M13/2933, H03M13/2906, G06F11/1068, G11C7/1006|
|European Classification||G11C7/10L, G06F11/10M8|
|Jul 6, 2007||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RADKE, WILLIAM H.;REEL/FRAME:019525/0208
Effective date: 20070628
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