US8067268B2 - Stacked integrated circuit package system and method for manufacturing thereof - Google Patents
Stacked integrated circuit package system and method for manufacturing thereof Download PDFInfo
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- US8067268B2 US8067268B2 US12/782,992 US78299210A US8067268B2 US 8067268 B2 US8067268 B2 US 8067268B2 US 78299210 A US78299210 A US 78299210A US 8067268 B2 US8067268 B2 US 8067268B2
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- integrated circuit
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Definitions
- the present invention relates generally to an integrated circuit package system, and more particularly to a system with a stacked integrated circuit package system.
- Electronic devices such as smart phones, personal digital assistants, location based devices, digital cameras, music players, computers, or transportation, have become an integral part of many daily activities. Key components of these electronic devices are integrated circuit devices. These tiny integrated circuits must perform during daily activities including a wide variety of environmental conditions as well as potentially damaging forces. Many and varied types of packaging, intended for protection, interconnection or mounting, have been developed for integrated circuit devices.
- Integrated circuit dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the integrated circuit die and an underlying substrate such as a printed circuit board (PCB).
- the elements of such a package include: a lead frame or substrate, an integrated circuit die, bonding material to attach the integrated circuit die to the lead frame or substrate, bond wires or other connectors that electrically connect pads on the integrated circuit die to the lead frame or substrate.
- the package can also include a plastic or other insulating material that covers the components and forms the exterior of the package.
- Wafer manufacturing strives to reduce transistor or capacitor feature size in order to increase circuit density and enhance functionality.
- Device geometries with sub-micron line widths are so common that individual chips routinely contain millions of electronic devices.
- Reduced feature size has been quite successful in improving electronic systems, and continuous development is expected in the future.
- significant obstacles to further reduction in feature size are being encountered. These obstacles include defect density control, optical system resolution limits, and availability of processing material and equipment. Attention has therefore increasingly shifted to semiconductor packaging as a means to fulfill the relentless demands for enhanced system performance.
- Drawbacks of conventional designs include a relatively large footprint of the package on the mounting surface of motherboard.
- the footprint reflects dimensions that are typically the maximum of the package, namely, the maximum x-y dimensions of the package.
- a large footprint is undesirable.
- manufacturers have been stacking two or more die within a single package. Unfortunately, sufficient overlap for electrical interconnect, large footprint top packages, increased device integration, pre-testing, and interconnect lengths have plagued previous package designs.
- the present invention provides a method for manufacturing of a stacked integrated circuit package system including: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer; and mounting a top integrated circuit package over the intermediate integrated circuit package.
- the present invention provides a stacked integrated circuit package system including: a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; an intermediate integrated circuit package mounted over the base interposer; and a top integrated circuit package mounted over the intermediate integrated circuit package.
- FIG. 1 is a top view of a stacked integrated circuit package system in a first embodiment of the present invention
- FIG. 2 is a cross-sectional view of the stacked integrated circuit package system along line 2 - 2 of FIG. 1 ;
- FIG. 3 is a cross-sectional view of a stacked integrated circuit package system exemplified by the top view of FIG. 1 in a second embodiment of the present invention
- FIG. 4 is a top view of a stacked integrated circuit package system in a third embodiment of the present invention.
- FIG. 5 is a cross-sectional view of the stacked integrated circuit package system along line 5 - 5 of FIG. 4 ;
- FIG. 6 is a cross-sectional view of a stacked integrated circuit package system exemplified by the top view of FIG. 1 in a fourth embodiment of the present invention.
- FIG. 7 is a flow chart of a stacked integrated circuit package system for manufacturing of the stacked integrated circuit package system in an embodiment of the present invention.
- the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit, regardless of its orientation.
- the term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane.
- the term “on” means there is direct contact among elements.
- processing as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure.
- system as used herein means and refers to the method and to the apparatus of the present invention in accordance with the context in which the term is used.
- FIG. 1 therein is shown a top view of a stacked integrated circuit package system 100 in a first embodiment of the present invention.
- the top view depicts a top package encapsulation 101 , such as a cover including an epoxy molding compound.
- the top package encapsulation 101 is optional.
- FIG. 2 therein is shown a cross-sectional view of the stacked integrated circuit package system 100 along line 2 - 2 of FIG. 1 .
- the cross-sectional view depicts a base integrated circuit package 202 having a base encapsulation 204 , such as cover including an epoxy molding compound, with a cavity 206 therein.
- a base interposer 208 such as a laminated substrate is exposed by the cavity 206 .
- the base integrated circuit package 202 includes a base package carrier 210 .
- the cavity 206 is above the base package carrier 210 .
- the base integrated circuit package 202 includes a first base integrated circuit device 212 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the first base integrated circuit device 212 can be under the base interposer 208 .
- the base integrated circuit package 202 can include additional integrated circuit devices such one or more flip chips, wire bonded chips, or packaged integrated circuits.
- a second base integrated circuit device 214 can be over the base package carrier 210 .
- an external interconnect 216 can attach to the stacked integrated circuit package system 100 for connection to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.
- the external interconnect 216 is attached below and to the base package carrier 210 .
- the base package carrier 210 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- the intermediate integrated circuit package 218 is mounted over the base interposer 208 .
- the intermediate integrated circuit package 218 includes an intermediate package carrier 220 such as a laminated substrate or an interposer.
- the intermediate package carrier 220 and the base interposer 208 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- a base intra-stack interconnect 222 such as a solder ball, forms a base electrical interconnection between the base integrated circuit package 202 and the intermediate integrated circuit package 218 .
- the base intra-stack interconnect 222 examples include column grid arrays, pin interconnects, post interconnects, interconnects formed using folded printed circuit boards (PCBs) or combinations thereof.
- the base intra-stack interconnect 222 is mounted over the base interposer 208 and couples the base integrated circuit package 202 to the intermediate integrated circuit package 218 through the intermediate package carrier 220 .
- the stacked integrated circuit package system 100 can provide a stacked integrated circuit package system with reduced profile.
- the stacked integrated circuit package system 100 includes the base intra-stack interconnect 222 , such as a solder ball, formed over the base interposer 208 and disposed in the cavity 206 . This configuration can provide the functionality of an interconnected system with a reduced system height.
- the intermediate integrated circuit package 218 includes a first intermediate integrated circuit device 224 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the intermediate integrated circuit package 218 may be or may include a Known Good Package (“KGP”) that has been functionally tested.
- KGP Known Good Package
- the intermediate integrated circuit package 218 can include additional integrated circuit devices flip chips, wire bonded chips, or packaged integrated circuits.
- a top integrated circuit package 226 is mounted over the intermediate integrated circuit package 218 .
- the top integrated circuit package 226 includes a top package carrier 228 such as a laminated substrate or an interposer.
- the top package carrier 228 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- an intermediate intra-stack interconnect 230 such as a solder ball, forms an intermediate electrical interconnection between the intermediate integrated circuit package 218 and the top integrated circuit package 226 .
- Other examples of the intermediate intra-stack interconnect 230 include wire-bond wires, column grid arrays, pin interconnects, post interconnects, interconnects formed using folded printed circuit boards (PCBs) or combinations thereof.
- the top integrated circuit package 226 includes a first top integrated circuit device 232 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the top integrated circuit package 226 may be or may include a Known Good Package (“KGP”) that has been functionally tested.
- KGP Known Good Package
- the top integrated circuit package 226 can include additional integrated circuit devices flip chips, wire bonded chips, or packaged integrated circuits.
- the intermediate integrated circuit package 218 and the top integrated circuit package 226 can include multichip packages, flip chip packages, lead frame base packages, board-on-chip (BOC) packages, system-on-a-package (SIP) packages, package-in-a-package (PiP) packages and any combination thereof.
- the intermediate integrated circuit package 218 and the top integrated circuit package 226 can be assembled together before mounting the intermediate integrated circuit package 218 over the base integrated circuit package 202 .
- an assembly including the intermediate integrated circuit package 218 and the top integrated circuit package 226 may be tested before mounting the intermediate integrated circuit package 218 over the base integrated circuit package 202 .
- the intermediate integrated circuit package 218 and the top integrated circuit package 226 may be pre-assembled and tested to produce a Known Good Package (“KGP”) including at least two integrated circuit devices (the first intermediate integrated circuit device 224 and the first top integrated circuit device 232 ). This feature can further reduce manufacturing cost and increase reliability.
- KGP Known Good Package
- the stacked integrated circuit package system 100 is shown with the base integrated circuit package 202 , the intermediate integrated circuit package 218 , and the top integrated circuit package 226 of the same lateral dimensions.
- the base integrated circuit package 202 , the intermediate integrated circuit package 218 , and the top integrated circuit package 226 may have different relative lateral dimensions.
- the base intra-stack interconnect 222 and the intermediate intra-stack interconnect 230 are both illustrated as solder balls.
- the type of interconnect used for the base intra-stack interconnect 222 can be different from the type of interconnect used for the intermediate intra-stack interconnect 230 .
- FIG. 3 therein is shown a cross-sectional view of a stacked integrated circuit package system 300 exemplified by the top view of FIG. 1 in a second embodiment of the present invention.
- the cross-sectional view depicts a base integrated circuit package 302 having a base encapsulation 304 , such as a cover including an epoxy molding compound, with a cavity 306 therein.
- a base interposer 308 such as a laminated substrate, is exposed by the cavity 306 .
- the base integrated circuit package 302 includes a base package carrier 310 .
- the cavity 306 is below the base package carrier 310 .
- the base integrated circuit package 302 includes a first base integrated circuit device 312 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the first base integrated circuit device 312 can be over the base interposer 308 .
- the base integrated circuit package 302 can include additional integrated circuit devices such one or more flip chips, wire bonded chips, or packaged integrated circuits.
- a second base integrated circuit device 314 can be under the base package carrier 310 .
- the base integrated circuit package 302 in the stacked integrated circuit package system 300 has the base package carrier 310 over the base interposer 308 ; this configuration may be referred to as an “upside down” or “inverted” package-on-package (POP) system.
- POP package-on-package
- an external interconnect 316 can attach to the stacked integrated circuit package system 300 for connection to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.
- the external interconnect 316 is below the base package carrier 310 and is attached below and to the base interposer 308 .
- the base interposer 308 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- the stacked integrated circuit package system 300 provides a stacked integrated circuit package system with reduced profile.
- the stacked integrated circuit package system 300 includes the external interconnect 316 , such as a solder ball, formed under the base interposer 308 and disposed in the cavity 306 . This configuration can provide the functionality of an externally interconnectable system with a reduced system height.
- the intermediate integrated circuit package 318 is mounted over the base package carrier 310 .
- the intermediate integrated circuit package 318 includes an intermediate package carrier 320 such as a laminated substrate or interposer.
- a base intra-stack interconnect 322 such as a solder ball, forms a base electrical interconnection between the base integrated circuit package 302 and the intermediate integrated circuit package 318 .
- the intermediate package carrier 320 and the base package carrier 310 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- Other examples of the base intra-stack interconnect 322 include column grid arrays, pin interconnects, post interconnects, interconnects formed using folded printed circuit boards (PCBs) or combinations thereof.
- the base intra-stack interconnect 322 is mounted over and to the base package carrier 310 .
- the base intra-stack interconnect 322 couples to the intermediate integrated circuit package 318 through the intermediate package carrier 320 .
- the intermediate integrated circuit package 318 includes a first intermediate integrated circuit device 324 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the intermediate integrated circuit package 318 may be or may include a Known Good Package (“KGP”) that has been functionally tested.
- KGP Known Good Package
- the intermediate integrated circuit package 318 can include additional integrated circuit devices such as flip chips, wire bonded chips, or packaged integrated circuits.
- a second intermediate integrated circuit device 334 can be over the intermediate package carrier 320 .
- a top integrated circuit package 326 is mounted over the intermediate integrated circuit package 318 .
- the top integrated circuit package 326 includes a top package carrier 328 such as a laminated substrate or interposer.
- the top package carrier 328 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- an intermediate intra-stack interconnect 330 such as a wire, wire-bond wire or wire-bond ribbon, forms an intermediate electrical interconnection between the intermediate integrated circuit package 318 and the top integrated circuit package 326 .
- Other examples of the intermediate intra-stack interconnect 330 include solder balls, column grid arrays, pin interconnects, post interconnects, interconnects formed using folded printed circuit boards (PCBs) or combinations thereof.
- the top integrated circuit package 326 includes a first top integrated circuit device 332 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the top integrated circuit package 326 may be or may include a Known Good Package (“KGP”) that has been functionally tested.
- KGP Known Good Package
- the top integrated circuit package 326 can include additional integrated circuit devices flip chips, wire bonded chips, or packaged integrated circuits.
- a combination package encapsulation 336 such as a cover including epoxy molding compound, has been formed over the intermediate integrated circuit package 318 and the top integrated circuit package 326 .
- the combination package encapsulation 336 is optional.
- the combination package encapsulation 336 completely encapsulates both the intermediate integrated circuit package 318 and the top integrated circuit package 326 .
- the combination package encapsulation 336 can leave portions of the intermediate integrated circuit package 318 or the top integrated circuit package 326 exposed.
- the intermediate integrated circuit package 318 and the top integrated circuit package 326 can include multichip packages, flip chip packages, lead frame base packages, board-on-chip (BOC) packages, system-on-a-package (SIP) packages, package-in-a-package (PiP) packages and any combination thereof.
- the intermediate integrated circuit package 318 and the top integrated circuit package 326 can be assembled together before mounting the intermediate integrated circuit package 318 over the base integrated circuit package 302 .
- an assembly including the intermediate integrated circuit package 318 and the top integrated circuit package 326 may be tested before mounting the intermediate integrated circuit package 318 over the base integrated circuit package 302 .
- the intermediate integrated circuit package 318 and the top integrated circuit package 326 may be pre-assembled and tested to produce a Known Good Package (“KGP”) including at least two integrated circuit devices (the first intermediate integrated circuit device 324 and the first top integrated circuit device 332 ).
- KGP Known Good Package
- the combination package encapsulation 336 may be formed over an assembly including the intermediate integrated circuit package 318 and the top integrated circuit package 326 before mounting the intermediate integrated circuit package 318 over the base integrated circuit package 302 .
- the stacked integrated circuit package system 300 is shown with the base package carrier 310 and the intermediate package carrier 320 of the same dimensions. However, it is understood the base package carrier 310 and the intermediate package carrier 320 may have different dimensions.
- FIG. 4 therein is shown a top view of a stacked integrated circuit package system 400 in a third embodiment of the present invention.
- the top view depicts a base encapsulation 404 and a combination package encapsulation 436 , such as a cover including an epoxy molding compound.
- the combination package encapsulation 436 is optional.
- a top package carrier 428 such as a laminated substrate or interposer, is exposed.
- FIG. 5 therein is shown a cross-sectional view of the stacked integrated circuit package system 400 along line 5 - 5 of FIG. 4 .
- the cross-sectional view depicts a base integrated circuit package 502 and the base encapsulation 404 such as a cover including an epoxy molding compound, with a cavity 506 therein.
- the base integrated circuit package 502 includes a base package carrier 510 .
- the cavity 506 is above the base package carrier 510 .
- the base integrated circuit package 502 includes a first base integrated circuit device 512 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the first base integrated circuit device 512 can be under the base interposer 508 .
- the base integrated circuit package 502 can include additional integrated circuit devices such one or more flip chips, wire bonded chips, or packaged integrated circuits.
- a second base integrated circuit device 514 can be over the base package carrier 510 .
- an external interconnect 516 can attach to the stacked integrated circuit package system 400 for connection to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.
- the external interconnect 516 is attached below and to the base package carrier 510 .
- the base package carrier 510 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- the intermediate integrated circuit package 518 is mounted over the base interposer 508 .
- the intermediate integrated circuit package 518 includes an intermediate package carrier 520 such as a laminated substrate or interposer.
- the intermediate package carrier 520 and the base interposer 508 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- a base intra-stack interconnect 522 such as a solder ball, forms a base electrical interconnection between the base integrated circuit package 502 and the intermediate integrated circuit package 518 .
- Other examples of the base intra-stack interconnect include column grid arrays, pin interconnects, post interconnects, interconnects formed using folded printed circuit boards (PCBs) or combinations thereof.
- the base intra-stack interconnect 522 is mounted over the base interposer 508 .
- the base intra-stack interconnect 522 can couple to the intermediate integrated circuit package 518 through the intermediate package carrier 520 .
- the stacked integrated circuit package system 400 provides a stacked integrated circuit package system with reduced profile.
- the stacked integrated circuit package system 400 includes the base intra-stack interconnect 522 , such as a solder ball, formed over the base interposer 508 and disposed in the cavity 506 . This configuration can provide the functionality of an interconnected system with a reduced system height.
- the intermediate integrated circuit package 518 includes a first intermediate integrated circuit device 524 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the intermediate integrated circuit package 518 may be or may include a Known Good Package (“KGP”) that has been functionally tested.
- KGP Known Good Package
- the intermediate integrated circuit package 518 can include additional integrated circuit devices flip chips, wire bonded chips, or packaged integrated circuits.
- a top integrated circuit package 526 is mounted over the intermediate integrated circuit package 518 .
- the top integrated circuit package 526 includes the top package carrier 428 such as a laminated substrate or interposer.
- the top package carrier 428 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- an intermediate intra-stack interconnect 530 such as a wire, wire-bond wire or wire-bond ribbon, forms an intermediate electrical interconnection between the intermediate integrated circuit package 518 and the top integrated circuit package 526 .
- Other examples of the intermediate intra-stack interconnect 530 include solder balls, column grid arrays, pin interconnects, post interconnects, interconnects formed using folded printed circuit boards (PCBs) or combinations thereof.
- the top integrated circuit package 526 includes a first top integrated circuit device 532 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the top integrated circuit package 526 may be or may include a Known Good Package (“KGP”) that has been functionally tested.
- KGP Known Good Package
- the top integrated circuit package 526 can include additional integrated circuit devices flip chips, wire bonded chips, or packaged integrated circuits.
- the combination package encapsulation 436 such as a cover including epoxy molding compound, has been formed over the intermediate integrated circuit package 518 and the top integrated circuit package 526 .
- the combination package encapsulation 436 is optional.
- the combination package encapsulation 436 includes a top cavity 538 .
- the combination package encapsulation 436 encapsulates both the intermediate integrated circuit package 518 and the top integrated circuit package 526 , leaving the top package carrier 428 exposed.
- the combination package encapsulation 436 can fully encapsulate the intermediate integrated circuit package 518 and the top integrated circuit package 526 .
- the intermediate integrated circuit package 518 and the top integrated circuit package 526 can include multichip packages, flip chip packages, lead frame base packages, board-on-chip (BOC) packages, system-on-a-package (SIP) packages, package-in-a-package (PiP) packages and any combination thereof.
- the intermediate integrated circuit package 518 and the top integrated circuit package 526 can be assembled together before mounting the intermediate integrated circuit package 518 over the base integrated circuit package 502 .
- an assembly including the intermediate integrated circuit package 518 and the top integrated circuit package 526 may be tested before mounting the intermediate integrated circuit package 518 over the base integrated circuit package 502 .
- the intermediate integrated circuit package 518 and the top integrated circuit package 526 may be pre-assembled and tested to produce a Known Good Package (“KGP”) including at least two integrated circuit devices (the first intermediate integrated circuit device 524 and the first top integrated circuit device 532 ).
- KGP Known Good Package
- the combination package encapsulation 436 may be formed over an assembly including the intermediate integrated circuit package 518 and the top integrated circuit package 526 before mounting the intermediate integrated circuit package 518 over the base integrated circuit package 502 .
- FIG. 6 therein is shown a cross-sectional view of a stacked integrated circuit package system 600 exemplified by the top view of FIG. 1 in a fourth embodiment of the present invention.
- the cross-sectional view depicts a base integrated circuit package 602 having a base encapsulation 604 , such as a cover including an epoxy molding compound, with a cavity 606 therein.
- a base interposer 608 such as a laminated substrate, is exposed by the cavity 606 .
- the base integrated circuit package 602 includes a base package carrier 610 , such as a laminated substrate. In this example, the cavity 606 is above the base package carrier 610 .
- the base integrated circuit package 602 includes a first base integrated circuit device 612 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the first base integrated circuit device 612 can be mounted over the base package carrier 610 .
- the base integrated circuit package 602 can include additional integrated circuit devices such one or more flip chips, wire bonded chips, or packaged integrated circuits.
- an external interconnect 616 can attach to the stacked integrated circuit package system 600 for connection to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.
- the base package carrier 610 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- the external interconnect 616 is attached below and to the base package carrier 610 .
- the intermediate integrated circuit package 618 is mounted over the base interposer 608 .
- the intermediate integrated circuit package 618 includes an intermediate package carrier 620 such as a laminated substrate or interposer.
- the intermediate package carrier 620 and the base interposer 608 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- a base intra-stack interconnect 622 such as a solder ball, forms a base electrical interconnection between the base integrated circuit package 602 and the intermediate integrated circuit package 618 .
- Other examples of the base intra-stack interconnect 622 include column grid arrays, pin interconnects, post interconnects, interconnects formed using folded printed circuit boards (PCBs) or combinations thereof.
- the base intra-stack interconnect 622 is mounted over the base interposer 608 .
- the base intra-stack interconnect 622 couples the base integrated circuit package 602 to the intermediate integrated circuit package 618 through the intermediate package carrier
- the stacked integrated circuit package system 600 provides a stacked integrated circuit package system with reduced profile.
- the stacked integrated circuit package system 600 includes the base intra-stack interconnect 622 , such as a solder ball, formed over the base interposer 608 and disposed in the cavity 606 .
- This configuration can provide the functionality of an interconnected system with a reduced system height.
- the intermediate integrated circuit package 618 includes a first intermediate integrated circuit device 624 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the intermediate integrated circuit package 618 may be or may include a Known Good Package (“KGP”) that has been functionally tested.
- KGP Known Good Package
- the intermediate integrated circuit package 618 can include additional integrated circuit devices flip chips, wire bonded chips, or packaged integrated circuits.
- a top integrated circuit package 626 is mounted over the intermediate integrated circuit package 618 .
- the top integrated circuit package 626 includes a top package carrier 628 such as a laminated substrate or interposer.
- the top package carrier 628 may include other structures (not shown), such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof.
- an intermediate intra-stack interconnect 630 such as a solder ball, forms an intermediate electrical interconnection between the intermediate integrated circuit package 618 and the top integrated circuit package 626 .
- Other examples of the intermediate intra-stack interconnect 630 include wire-bond wires, column grid arrays, pin interconnects, post interconnects, interconnects formed using folded printed circuit boards (PCBs) or combinations thereof.
- the top integrated circuit package 626 includes a first top integrated circuit device 632 such as one or more flip chips, wire bonded chips, or packaged integrated circuits.
- the top integrated circuit package 626 may be a Known Good Package (“KGP”) that has been functionally tested.
- KGP Known Good Package
- the top integrated circuit package 626 can include additional integrated circuit devices flip chips, wire bonded chips, or packaged integrated circuits.
- a second top integrated circuit device 640 can be over the top package carrier 628 .
- a top package encapsulation 601 such as a cover including an epoxy molding compound, may be formed over the top integrated circuit package 626 .
- the intermediate integrated circuit package 618 and the top integrated circuit package 626 can include multichip packages, flip chip packages, lead frame base packages, board-on-chip (BOC) packages, system-on-a-package (SIP) packages, package-in-a-package (PiP) packages and any combination thereof.
- the intermediate integrated circuit package 618 and the top integrated circuit package 626 can be assembled together before mounting the intermediate integrated circuit package 618 over the base integrated circuit package 602 .
- an assembly including the intermediate integrated circuit package 618 and the top integrated circuit package 626 may be tested before mounting the intermediate integrated circuit package 618 over the base integrated circuit package 602 .
- the intermediate integrated circuit package 618 and the top integrated circuit package 626 may be pre-assembled and tested to produce a Known Good Package (“KGP”) including at least two integrated circuit devices (the first intermediate integrated circuit device 624 and the first top integrated circuit device 632 ).
- KGP Known Good Package
- the present invention provides a compact stacked integrated circuit package system.
- the present invention can provide improved yields due to the modular nature of the system.
- the base integrated circuit package, the intermediate integrated circuit package, and the top integrated circuit package may be independently tested or characterized before assembly in a stacked integrated circuit package system according to the current invention.
- the present invention provides a stacked integrated circuit package system with excellent thermal management properties.
- the gaps in the current invention such as the cavity can provide air flow channels for improved heat dissipation.
- the present invention can provide a system capable of complex internal interconnections.
- Some embodiments of the current invention include a base package carrier, a base interposer, an intermediate package carrier and a top package carrier including structures such as metal traces, metal layers, insulating layers, electrical vias, landing pads, or a combination thereof for providing complex interconnections.
- the present invention can enable the implementation of complex interconnected systems including three or more integrated circuit devices with a small footprint.
- the system 700 includes providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity in a block 702 ; mounting an intermediate integrated circuit package over the base interposer in a block 704 ; and mounting a top integrated circuit package over the intermediate integrated circuit package in a block 706 .
- Yet another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
- the integrated circuit package system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving yield, increasing reliability, and reducing cost of circuit system.
- the resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.
Abstract
Description
Claims (15)
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US12/782,992 US8067268B2 (en) | 2008-03-27 | 2010-05-19 | Stacked integrated circuit package system and method for manufacturing thereof |
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US20090243073A1 (en) | 2009-10-01 |
US7750454B2 (en) | 2010-07-06 |
US20100224979A1 (en) | 2010-09-09 |
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