|Publication number||US8076778 B2|
|Application number||US 12/570,941|
|Publication date||Dec 13, 2011|
|Filing date||Sep 30, 2009|
|Priority date||Sep 30, 2009|
|Also published as||CN102034740A, CN102034740B, US20110074030|
|Publication number||12570941, 570941, US 8076778 B2, US 8076778B2, US-B2-8076778, US8076778 B2, US8076778B2|
|Inventors||Kuo Liang Wei, Hsu Sheng Yu, Hong-Ji Lee|
|Original Assignee||Macronix International Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (23), Classifications (44), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Technical Field
The present invention relates to conductive lines of a semiconductor device, and more particularly, to a method for preventing damage to a conductive line during fabrication of a semiconductor device.
2. Related Art
As sizes of conductive lines of semiconductor devices are designed below sub-micron ranges, such as AlCu at about 0.1 μm, it is difficult to protect sidewalls of metal lines (ML) during fabrication processing. One solution includes using a heavy polymer gas flow during ML etch processing to protect the sidewall of the ML lines against damage. However, this solution results in producing ML lines having wider bottom portions and suffers from a tight overlay window of adjacent ML line formation. Conversely, in an attempt to relieve the overlay window problem, a light polymer gas flow is used to protect the sidewall of the ML lines against etching damage.
As shown in
Thus, a method is required that can prevent notch formation of conductive lines during etching processing, and provide adequate relief of the overlay window.
A method of fabricating conductive lines of a semiconductor device while preventing damage to the conductive lines is described here.
In one aspect, a method for fabricating a semiconductor device includes providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.
In another aspect, a method for fabricating a semiconductor device includes etching completely through an upper barrier layer and a conductive layer, without etching completely through a lower barrier layer disposed beneath the conductive layer, to form a plurality of conductive lines extending from the lower barrier layer, forming a liner layer to completely cover the conductive lines and to partially cover portions of the lower barrier layer disposed between the conductive lines, and etching completely through the lower barrier layer after the forming of the liner layer to form a plurality of lower barrier layers, wherein each of the plurality of lower barrier layers correspond to one of the plurality of conductive lines.
These and other features, aspects, and embodiments of the invention are described below in the section entitled “Detailed Description.”
Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:
As a result, the conductive lines 132 may be provided without having notches formed at the base region of the conductive lines 132. Accordingly, the conductive lines 132 may be provided having improved mechanical strength by preventing formation of notches during final etching of the lower TiN/Ti barrier layer 120, and the overlay window between adjacent ones of the plurality of conductive lines can be relieved.
While certain embodiments of the inventions have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the inventions should not be limited based on the described embodiments. Rather, the scope of the inventions described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5578166 *||May 24, 1995||Nov 26, 1996||Fujitsu Limited||Method of reactive ion etching of a thin copper film|
|US5779926 *||Feb 5, 1996||Jul 14, 1998||Applied Materials, Inc.||Plasma process for etching multicomponent alloys|
|US5976986 *||Aug 6, 1996||Nov 2, 1999||International Business Machines Corp.||Low pressure and low power C12 /HC1 process for sub-micron metal etching|
|US6054380 *||Dec 9, 1997||Apr 25, 2000||Applied Materials, Inc.||Method and apparatus for integrating low dielectric constant materials into a multilevel metallization and interconnect structure|
|US6103630 *||Feb 9, 1998||Aug 15, 2000||Taiwan Semiconductor Manufacturing Company||Adding SF6 gas to improve metal undercut for hardmask metal etching|
|US6156663 *||Sep 27, 1996||Dec 5, 2000||Hitachi, Ltd.||Method and apparatus for plasma processing|
|US6271119 *||Mar 11, 1999||Aug 7, 2001||Nec Corporation||Method for making semiconductor device|
|US6277745 *||Dec 28, 1998||Aug 21, 2001||Taiwan Semiconductor Manufacturing Company||Passivation method of post copper dry etching|
|US6307266 *||Jul 20, 2000||Oct 23, 2001||Winbond Electronics Corp.||Metal-line structure having a spacer structure covering the sidewalls thereof|
|US6387820 *||Sep 19, 2000||May 14, 2002||Advanced Micro Devices, Inc.||BC13/AR chemistry for metal overetching on a high density plasma etcher|
|US6440865 *||May 22, 2000||Aug 27, 2002||Winbond Electronics Corp.||Method of profile control in metal etching|
|US6566263 *||Aug 2, 2000||May 20, 2003||Taiwan Semiconductor Manufacturing Company||Method of forming an HDP CVD oxide layer over a metal line structure for high aspect ratio design rule|
|US6617689 *||Aug 31, 2000||Sep 9, 2003||Micron Technology, Inc.||Metal line and method of suppressing void formation therein|
|US6677647 *||Sep 15, 1998||Jan 13, 2004||Advanced Micro Devices, Inc.||Electromigration characteristics of patterned metal features in semiconductor devices|
|US6821900 *||Jan 9, 2001||Nov 23, 2004||Infineon Technologies Ag||Method for dry etching deep trenches in a substrate|
|US6960529 *||Feb 24, 2003||Nov 1, 2005||Ami Semiconductor, Inc.||Methods for sidewall protection of metal interconnect for unlanded vias using physical vapor deposition|
|US7078339 *||Dec 10, 2003||Jul 18, 2006||Hynix Semiconductor Inc.||Method of forming metal line layer in semiconductor device|
|US20020001945 *||Feb 28, 2001||Jan 3, 2002||Song Won-Sang||Method of manufacturing metal pattern of semiconductor device|
|US20020038911 *||Nov 8, 2001||Apr 4, 2002||Graas Carole D.||Surface modified interconnects|
|US20030036260 *||Apr 17, 2002||Feb 20, 2003||Makiko Nakamura||Method for manufacturing a semiconductor device|
|US20030116826 *||Dec 20, 2001||Jun 26, 2003||Chen-Chiu Hsue||Interconnect structure capped with a metallic barrier layer and method fabrication thereof|
|US20060214191 *||Mar 24, 2006||Sep 28, 2006||Kabushiki Kaisha Toshiba||Semiconductor device and method of manufacturing the same|
|US20080036026 *||Jul 10, 2007||Feb 14, 2008||Park Jeong S||Metal line of image sensor|
|U.S. Classification||257/750, 257/771, 216/100, 257/E23.161, 438/543, 257/E21.582, 257/762, 257/E21.017, 257/E23.155, 257/E23.151, 438/688, 216/67, 438/628, 257/E21.59, 257/635, 438/656, 438/618, 257/765, 216/102, 438/548, 438/625, 438/652, 257/E21.022, 257/E23.157, 438/622, 438/669, 257/E21.02, 257/758, 216/62, 257/E21.591, 216/72|
|International Classification||H01L23/48, H01L23/52, H01L23/40|
|Cooperative Classification||H01L21/32139, H01L2924/12044, H01L21/32136, H01L23/53223, H01L21/76852, H01L2924/0002|
|European Classification||H01L21/3213D, H01L21/768C3C2, H01L23/532M1A4, H01L21/3213C4B|
|Sep 30, 2009||AS||Assignment|
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WEI, KUO LIANG;YU, HSU SHENG;LEE, HONG-JI;REEL/FRAME:023308/0693
Effective date: 20090923
|Mar 11, 2015||FPAY||Fee payment|
Year of fee payment: 4