US 8088645 B2
A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semiconductor devices are die bonded to a direct bonded copper substrate which has a bottom surface exposed in the molded package. In one embodiment the module has 27 external connectors attached to one side of the PC board and arranged in the form of a ball grid array.
1. A method of forming an encapsulated semiconductor package comprising the steps of:
die bonding first semiconductor devices to die bond surfaces of a planar substrate respectively, the surfaces lying in a single plane and being disposed in regions;
attaching and electrically connecting the first semiconductor devices to selected traces respectively on a first side of a printed circuit (PC) board, the PC board having vias between the selected traces and traces on a second side of said PC board opposite to the first side;
attaching and electrically connecting second semiconductor devices to selected traces of the second side of the PC board respectively; and
attaching external pins to some of the traces on the second side of the PC board.
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This application is a divisional of U.S. patent application Ser. No. 12/028,051 filed Feb. 8, 2008, the specification of which is hereby incorporated by reference in its entirety.
This invention relates to power semiconductor packages with multiple semiconductor dice.
Generally smart power modules (SPM) include power devices such as IGBTs and IC control devices which are mounted on metallic leadframes. However such modules are subject to leadframe deformation and warpage due to large package size. Also the large number of bond wires increases the likelihood of a wire bond failure and also increases the likelihood of cracked die during the wire bonding operation.
As with all power devices, the dissipation of heat is a major factor in packaging such devices, particularly if there are multiple power devices in the same package which are susceptible to failure when heated above certain temperatures.
The invention comprises, in one form thereof, an encapsulated semiconductor package having a first plurality of conductive regions having die bond surfaces that lie in a single plane, a second plurality of semiconductor devices die bonded to the first plurality of die bond surfaces, a printed circuit (PC) board having a third plurality of traces on a first side thereof and a fourth plurality of traces on a second side thereof opposite to the first side, the second plurality of semiconductor devices attached to selected ones of the third plurality of traces, a third plurality of vias in the PC board connecting each of the third plurality of traces to selected ones of the fourth plurality of traces, a fifth plurality of semiconductor devices attached to selected ones of the fourth plurality of traces, and a sixth plurality of external pins attached to some of the fourth plurality of traces.
In another form, the invention includes a method of forming an encapsulated semiconductor package The method comprises the steps of die bonding a first plurality of semiconductor devices to surfaces of a second plurality of conductive regions, the surfaces lying in a single plane, attaching the first plurality of semiconductor devices to selected ones of a third plurality of traces on a first side of a printed circuit (PC) board, the PC board having vias between the third plurality of traces and a fourth plurality of traces on a second side of the PC board opposite to the first side, attaching a fifth plurality of semiconductor devices to selected ones of the fourth plurality of traces, and attaching a sixth plurality of external pins to selected ones of the fourth plurality of traces.
The aforementioned and other features, characteristics, advantages, and the invention in general will be better understood from the following more detailed description taken in conjunction with the accompanying drawings, in which:
It will be appreciated that for purposes of clarity and where deemed appropriate, reference numerals have been repeated in the figures to indicate corresponding features. Also, the relative size of various objects in the drawings has in some cases been distorted to more clearly show the invention.
Turning now to the drawings,
The control circuit 30 has, on the right side of
The ICs 56, 58, 60, and 62 receive power and control signals, and provide status output on the connections 78-116.
Reference numbers for the interconnections of selected devices and terminals are also shown in
Connection 130 from terminal P, 64, to the collectors of IGBTs 32, 34, and 36;
Connection 132 connecting the collectors of IGBTs 32, 34, and 36 together;
Connection 134 from terminal W, 66, to the emitter of IGBT 32;
Connection 136 from the emitter of IGBT 32 to the collector of IGBT 38;
Connection 138 from terminal V, 68, to the emitter of IGBT 34;
Connection 140 from the emitter of IGBT 34 to the collector of IGBT 40;
Connection 142 from terminal U, 70, to the emitter of IGBT 36;
Connection 144 from the emitter of IGBT 36 to the collector of IGBT 42;
Connection 146 from terminal NW, 72, to the emitter of IGBT 38;
Connection 148 from terminal NV, 74, to the emitter of IGBT 40;
Connection 150 from terminal NU, 76, to the emitter of IGBT 42;
The following table shows the corresponding semiconductor devices, external terminals and electrical interconnections in an embodiment of a 3D smart power module (SPM) 200 of the present invention shown in
Turning now to
The SPM 160 includes a double sided printed circuit board (PCB) 180 in one embodiment with a 13 conductive regions or traces on the bottom, with 35 top traces, and 13 vias connecting the 13 bottom traces with 13 selected top traces. Attached to the top traces of the PC board are three high voltage ICs 256, 258, and 260, a low voltage IC 262, a plurality of wire bonds 182, 27 ball grid array (BGA) pins 184, and 27 BGA solder balls 186. (In an alternative embodiment shown in
A first solder paste pattern 190 is used to die bond the six IGBTs 232-242, the six FRDs 244-254, and the four connecting pins 181, 183, 185, and 187 to the top layer 170 of the DBC 164. A second solder paste pattern 192 is used to attach the four connecting pins 181, 183, 185, and 187 to four of the bottom traces of the PC board 180. The IGBTs 232-242 and the FRDs 244-254 have solder bump contacts which are attached to the bottom traces of the PC board 180. The three high voltage ICs 256-260 and the low voltage IC 262 are die bonded to traces on the top of the PC board 180 with an epoxy pattern of die bonding material 194, and the 27 BGA pins 184 and the 27 BGA blocks 188 (Shown in
The DBC plate 164 with the patterned die bond area 172-178, as shown in
While the invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the scope of the invention.
Therefore, it is intended that the invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope and spirit of the appended claims.