|Publication number||US8094508 B2|
|Application number||US 12/509,739|
|Publication date||Jan 10, 2012|
|Filing date||Jul 27, 2009|
|Priority date||Apr 12, 2006|
|Also published as||US7567472, US20070266276, US20090290441|
|Publication number||12509739, 509739, US 8094508 B2, US 8094508B2, US-B2-8094508, US8094508 B2, US8094508B2|
|Inventors||Scott N. Gatzemeier, Joemar Sinipete, Nevil Gajera, Mark Hawes|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (9), Classifications (9), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of U.S. application Ser. No. 11/402,534, titled “MEMORY BLOCK TESTING,” filed Apr. 12, 2006 (allowed) now U.S. Pat. No. 7,567,472, which application is commonly assigned and incorporated herein by reference.
The present invention relates generally to memory devices and in particular the present invention relates to memory block testing.
Memory devices, such as NAND or NOR flash memory devices, dynamic random access memory devices (DRAMs), static random access memory device (SRAMs), or the like, are generally fabricated on semiconductor wafers. Each of these wafers typically contains a number of individual integrated circuit memory devices formed in rectangular areas known as dies. After fabrication, each die is separated, or diced, then packaged in a format suitable for the end user.
Before or after dicing and packaging, a manufacturer may test its integrated circuit devices as part of a quality program to improve end-use reliability. Such tests are generally performed on highly-specialized testing systems or tester hardware. Prior to dicing, tests may be performed by the testing system on each die of a semiconductor wafer in pattern. The tester hardware may test each die individually or it may test multiple dies concurrently. Subsequent to dicing, tests may be performed by the testing system on multiple packaged components in pattern. The tester hardware may test each component individually or it may test multiple components concurrently.
A typical NAND flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks, e.g., 2048 blocks. Each block includes a number of rows, e.g., 32 rows, and each row may include one or more pages, e.g., two pages. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate.
To guarantee the programming speed of a memory device to a customer, typical test methods usually involve determining a time it takes to program each page and comparing that time to a predetermined acceptable programming time for a page. For some conventional test methods, if the programming time for any one of the pages is longer than the predetermined acceptable programming time, the entire block is failed and is repaired. That is, an entire block may be failed and subsequently repaired for just one slow block. Such repairs increase manufacturing times that result in reduced yields. Moreover, the frequency of the repairs is highly dependent on variations in the fabrication process.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative test methods for determining programming speeds.
In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.
For one embodiment memory device 102 may be a NAND memory device or the like that includes an array of flash memory cells 104, e.g., floating-gate memory cells, an address decoder 106, row access circuitry 108, column access circuitry 110, Input/Output (I/O) circuitry 114, and an address buffer 116. Command execution logic 111 is provided to control the basic operations of the memory device 102 in response to control signals received via control signal connections 122. A state machine 113 may also be provided to control specific operations performed on the memory array and the memory cells. The command execution logic 111 and/or state machine 113 can be generally referred to as control circuitry 112 to control read, write, erase, and other memory operations. The memory device 102 receives control signals from the processor 120 over a control link 122. The memory cells are used to store data that are accessed via a data (DQ) link 124. Address signals are received via an address link 126 that are decoded at address decoder 106 to access the memory array 104. Address buffer circuit 116 latches the address signals. The memory cells are accessed in response to the control signals and the address signals. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of
For one embodiment, command execution logic 111 includes trim circuitry (not shown) that may include fusible elements, such as fuses and/or anti-fuses, and/or other non-volatile storage elements adapted to store control parameter values used by state machine 113 for controlling operations on memory blocks of memory array 104. Such control parameters may include, for example, parameters for adjusting the magnitude and duration of voltage pulses applied to the memory blocks, or portions thereof, for carrying out programming and erasing operations.
For another embodiment, processor 120 is adapted to perform methods in accordance with embodiments of the present invention in response to computer-readable instructions. These computer-readable instructions are stored on a computer-usable media and may be in the form of software, firmware, or hardware. In a hardware solution, the instructions are hard coded as part of processor 120, e.g., an application-specific integrated circuit (ASIC) chip, a field programmable gate array (FPGA), etc. In a software or firmware solution, the instructions are stored for retrieval by processor 120. Some additional examples of computer-usable media include static or dynamic random access memory (SRAM or DRAM), read-only memory (ROM), electrically-erasable programmable ROM (EEPROM or flash memory), magnetic media and optical media, whether permanent or removable.
Memory array 400 includes NAND strings 406 1 to 406 M. Each NAND string includes floating-gate transistors 408 1 to 408 N, each located at an intersection of a word line 402 and a local bit line 404. The floating-gate transistors 408 represent non-volatile memory cells for storage of data. The floating-gate transistors 408 of each NAND string 406 are connected in series, source to drain, between a source select line 414 and a drain select line 415. Source select line 414 includes a source select gate 410, e.g., a field-effect transistor (FET), at each intersection between a NAND string 406 and source select line 414, and drain select line 415 includes a drain select gate 412, e.g., a field-effect transistor (FET), at each intersection between a NAND string 406 and drain select line 415. In this way, the floating-gate transistors 408 of each NAND string 406 are connected between a source select gate 410 and a drain select gate 412.
A source of each source select gate 410 is connected to a common source line 416. The drain of each source select gate 410 is connected to the source of the first floating-gate transistor 408 of the corresponding NAND string 406. For example, the drain of source select gate 4101 is connected to the source of floating-gate transistor 408 1 of the corresponding NAND string 406 1. Each source select gate 410 includes a control gate 420.
The drain of each drain select gate 412 is connected to the local bit line 404 for the corresponding NAND string at a drain contact 428. For example, the drain of drain select gate 412 1 is connected to the local bit line 404 1 for the corresponding NAND string 406 1 at drain contact 428 1. The source of each drain select gate 412 is connected to the drain of the last floating-gate transistor 408 N of the corresponding NAND string 406. For example, the source of drain select gate 412 1 is connected to the drain of floating-gate transistor 408 N of the corresponding NAND string 406 1.
Typical construction of floating-gate transistors 408 includes a source 430 and a drain 432, a floating gate 434, and a control gate 436, as shown in
At block 510, each page of a memory block is programmed using one or more programming cycles that may include applying a programming voltage and subsequently performing a program verify to determine whether the page is programmed correctly. After programming the pages of the memory block, a programming time for each page is determined at block 520, and a total programming time for the memory block is determined at block 530. For one embodiment, the programming time for each page and the total programming time for the memory block each correspond to a number of programming cycles. If the total programming time (or total number of programming cycles) for the memory block is less that or equal to a first predetermined time (or number of programming cycles), the memory block is passed at block 540. If the total programming time for the memory block exceeds the first predetermined time (or number of programming cycles) or a programming time (or number of programming cycles) for any one of the pages exceeds a second predetermined time (or number of programming cycles), the memory block is failed at block 550.
For another embodiment, a time period
For some embodiments, processor 120 checks the logic level of status signals 610 after a first number R1 of programming pulses, e.g., about four pulses, to determine whether any of the pages are programmed. For example, pages 310 2, 310 4, 310 5, and 310 6 of
If a page is not programmed by the first number R1 of programming pulses, i.e., in a programming time of
If a page is not programmed by the second number R2 of programming pulses, i.e., in a programming time of
For another embodiment, if the number of pages programmed in a programming time of
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.
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|Cooperative Classification||G11C29/50, G11C29/34, G11C16/04, G11C29/50012|
|European Classification||G11C29/50, G11C29/34, G11C29/50C|
|Jun 24, 2015||FPAY||Fee payment|
Year of fee payment: 4
|May 12, 2016||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001
Effective date: 20160426
|Jun 2, 2016||AS||Assignment|
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426
|Jun 8, 2017||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001
Effective date: 20160426