|Publication number||US8095331 B2|
|Application number||US 12/324,212|
|Publication date||Jan 10, 2012|
|Filing date||Nov 26, 2008|
|Priority date||Nov 30, 2007|
|Also published as||US20090144675|
|Publication number||12324212, 324212, US 8095331 B2, US 8095331B2, US-B2-8095331, US8095331 B2, US8095331B2|
|Inventors||Christian Haufe, Ingo Kuehn, David Larsen|
|Original Assignee||Globalfoundries Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Non-Patent Citations (3), Referenced by (4), Classifications (8), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation-in-part of application Ser. No. 12/122,017, filed May 16, 2008 now abandoned.
1. Field of the Invention
The present disclosure generally relates to systems and techniques for testing semiconductor devices in the form of hardware and/or software representations, and, more particularly, to systems and techniques for testing complex integrated circuits that include a central processing unit (CPU) and embedded peripheral devices connected to the CPU by internal bus systems to define a system on chip (SoC).
2. Description of the Related Art
In manufacturing semiconductor devices including a relatively complex circuitry, the testing of the device may represent a part of the manufacturing process, which has been underestimated a long time in terms of cost and effort required to obtain reliable data with respect to proper functionality and reliability of the device. In this respect, the manufacturing of the complex semiconductor device is to be understood to include the design of the device on the basis of a functional description of the desired functional behavior of the device, the various stages of providing a preliminary representation of the device in the form of a software model or a hardware prototype and respective re-designed versions thereof after encountering failures during verification, as well as the actual implementation of the finally established design in the semiconductor material. Thus, one reason in failing to meet specifications of the integrated circuit with respect to functional behavior may reside in design errors that may be identified and remedied by circuit verification on the basis of software simulation and/or prototype testing prior to mass production of the integrated circuits under consideration. An improper functionality of the integrated circuit may further be caused by the manufacturing process itself when the completed circuitry does not correspond to the verified circuit design, owing to process fluctuations in one or more of the large number of process steps involved during the processing. Although measurement and test procedures are incorporated at many points in the manufacturing process, it is nevertheless extremely important to ascertain the correct functioning of the final semiconductor device, since, according to a common rule of thumb, the costs caused by defective chips increase with each assembly phase by approximately one order of magnitude. For example, the costs caused by a defective circuit board including a faulty chip are typically significantly higher than identifying a defective chip prior to shipping and assembling the circuit board. The same holds true for a system, when a failure thereof is caused by one or more defective circuit boards as a downtime of an industrial system may result in averaged costs of approximately several hundred dollars per minute compared to a price of a few dollars for an integrated circuit chip having caused the defect.
Hence, there is a vital interest in developing test procedures to identify as many defects as possible in completed integrated circuits while not unduly increasing the total manufacturing costs. In particular, with the demand for more features and lower costs of circuits, there is a tendency to integrate a plurality of different circuit portions into a single chip to provide a complete system on a chip (SoC). A semiconductor device comprising various functional blocks may typically include, in addition to one or more logic blocks, one or more embedded memory portions, such as are used as on-chip cache for CPUs or as buffers for data packets that are transferred between different clock domains, and other peripheral components, such as complex I/O devices, dedicated functional blocks for efficient data processing of a specific type and the like, wherein these peripheral blocks are operatively connected to the CPU of the system via appropriate bus systems.
As discussed above, economic constraints force semiconductor manufacturers to not only minimize the defect level of the total manufacturing process, but also to provide, in combination with a reduced defect level, a high fault coverage so as to reduce the delivery of defective chips at reasonable cost for appropriate test procedures and techniques. For moderately complex integrated circuits, it has become standard practice to develop the basic design of the circuit while taking into consideration a plurality of constraints posed by effective test procedures. Moreover, typically, additional hardware resources are provided in the chip that may enable the identification of faulty circuit components for a broad class of operating conditions, wherein the additional hardware resources in combination with design specifics of the basic circuit and sophisticated test procedures and test patterns substantially determine the fault coverage of the test procedure.
In many circuit designs, the functional logic portion is tested by so-called scan chains, which represent a chain of flip-flops connected to a specific area of the functional logic in such a way that the functional logic or a specific area thereof may be initialized with a desired state that has previously been entered into the scan chain. In this case, the state of the logic block may be verified on the basis of the state of individual logic gates, which may be considered as a verification of the operational behavior of the logic block at register transfer level. However, with the advance of the semiconductor technology having arrived at transistor dimensions as low as approximately 40 nm and less, highly complex CPU designs are available including millions of logic gates, which makes it increasingly difficult to verify the proper functionality of the CPU at the register transfer level. Moreover, due to the incorporation of complex peripheral blocks, as explained above, additional efforts are required for identifying design flaws at an early manufacturing state prior to actually implementing mass production techniques.
Hence, the changing focus in the electronic industry from frequency scaling to enhancement with respect to functionality may contribute significantly to the overall complexity of the corresponding verification of semiconductor devices, thereby generating an increased demand for verification techniques that enable the testing of circuit designs at higher levels of abstractions compared to the registered transfer level, previously explained. For example, the verification complexity for register-based logic circuits rises as the square of the increase in the number of registers and thus by doubling the complexity of circuit implementation, for instance by advancing from one technology node to a future node, a four-fold impact on verification may result. In order to enable an efficient modeling of highly complex circuit designs of embedded hardware/software systems for estimating functional characteristics and performance behavior prior to the actual implementation of these systems, a plurality of different system description languages, such as SystemC, SpecC, System Verilog and the like, have been developed. However, in addition to providing appropriate and powerful description languages for modeling complex circuit designs, the verification may be performed on different abstraction levels to provide the possibility of reducing verification costs and allowing identification of design flaws and associating the same with deficiencies in architectural aspects or implementation-specific aspects. The modeling of complex circuit designs on a higher abstraction level compared to the register transfer level may, for instance, be accomplished by a transaction-based modeling technique that is based on combining various communication events to so-called transactions, thereby achieving a significantly higher degree of abstraction compared to the register transfer level of usual signals. That is, a transaction may be understood as a complete communication event, for instance, the transmission of a date or of a complete block of data wherein a respective communication event is ideally represented by the exchange of a single message within the transaction-based simulation model. In this way, enhanced simulation performance may be obtained compared to event-controlled simulation of signal-based communication protocols. The abstraction obtained by the transaction-based modeling technique may be associated with a reduced accuracy with respect to the timing within the simulated circuit since the various different protocol phases, which may be required during a respective transaction, may not be resolved, wherein, even for commonly used communication media, such as interface buses, a reduced degree of accuracy may result. That is, the timing for completing transactions may be monitored with a different degree of accuracy, depending on the modeling strategy used. For instance, cycle approximate models typically implement respective transactions such that the simulated time interval of activity may be closely related to the respective time required in an actual hardware implementation. However, precise resolving of the progression of different transactions may not be monitored and also the total duration of a single transaction, that is, active phases plus interruptions, may not be determined from the model. On the other hand, the total communication traffic on a respective bus may be determined with a sufficient accuracy. Consequently, by using a transaction-based verification, the estimation and testing of certain circuit components may be accomplished on a higher level compared to the level of bus signal changes, thereby enhancing the overall verification efficiency. For instance, transactions may typically be generated randomly so as to increase test coverage, while also providing the possibility of introducing specific constraints in order to exclude useless operational scenarios in the circuit component under test.
Conventional verification approaches for complex systems containing a central processing unit (CPU) usually split verification into verification of the CPU core and verification of the embedded peripheral functional components. After the verification of these components, an additional step of system verification may be performed to estimate and verify the functional behavior of the system as a whole.
With reference to
In other cases, the monitor 165 may be omitted and the reference model 166 may be directly connected to the transaction generator 162. The transactions provided by the monitor 164, representing the response of the peripheral functional block with respect to the initial transactions obtained from the generator 162, are forwarded to a check module 167, which also receives the initial transactions via the monitor 165 or the transaction generator 162. Thus, a respective deviation of results from the reference model 166 and the peripheral functional block 102 may be estimated on transaction level in order to verify the operational behavior of the block 102. Moreover, a feedback may be implemented between the monitor 164 and the test case 161, for instance via an appropriate test coverage module 168, or any other appropriate functional module, which may therefore enable the test case 161 to adapt the stream of transactions produced by the generator 162 in response to the transactions obtained from the monitor 164. Thus, the stimulating transactions obtained from the generator 162 may be adapted “on the fly” with respect to the response of the peripheral functional block 102. It should be appreciated that, depending on the configuration of the peripheral block 102, a plurality of respective monitors and check modules may be provided so as to allow the evaluation of a plurality of individual components within the peripheral functional block 102. Thus, a high degree of test coverage may be obtained, for instance, on the basis of randomized yet constrained transaction streams, with a significantly reduced amount of verification time compared to a scenario operating on a less abstract level.
As previously indicated, the system 100 may be tested as a whole which may be accomplished by running a set of directed test scenarios from inside the simulated CPU 101 in order to address the embedded peripheral functional block 102, which, however, may result in a compromised functional coverage or reduced implementation of resources due to the very restrictive directed test scenarios. In other cases, the system 100 may be modified compared to the configuration as shown in
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the subject matter disclosed herein relates to techniques and systems for enhancing the efficiency of the verification process for semiconductor devices in a design state, which comprise a central processing unit (CPU), possibly in combination with embedded peripheral components. For this purpose, a transaction-based test environment may be provided in which transactions may be translated into machine code readable by the central processing unit. Thus, the CPU may be operated during verification in its native mode, thereby accessing the machine code obtained from the transactions generated in the test environment and thus enabling a transaction-based constraint-driven randomness during the verification procedure. Thus, by providing the transaction to machine code translator, the high level of abstraction of the transaction-based environment may be appropriately “lowered” in order to provide efficient verification of the CPU environment, while also maintaining the possibility of re-using the test environment for verification of embedded peripheral components using a transaction-based test strategy. Hence, enhanced test coverage and thus verification efficiency may be obtained for the central processing unit while, at the same time, providing the potential of re-usability of the transaction-based test environment for verification of a complex system by bypassing the transaction to machine code translator, if appropriate. In other aspects, the CPU may take part at the transaction-based functional verification of the embedded peripherals, thereby increasing the overall design test coverage by also verifying the CPU and the CPU interfaces as well as potential deadlocks/lifelocks.
One illustrative test environment disclosed herein is designed for verification of a design of the semiconductor device including a central processing unit and an interface system operatively connected to the central processing unit. The test environment comprises a transaction generator configured to generate a stream of transactions and a translator unit operatively connected to the transaction generator to receive the stream of transactions therefrom. The translator unit is configured to provide a machine code representation for each of the transactions in order to provide executable instructions for the central processing unit. The test environment further comprises a machine code interface configured to receive the machine code representations and to enable access to at least some of the machine code representations by the central processing unit. Additionally, the test environment comprises a transaction check unit configured to receive and verify a response transaction representing a response of the central processing unit.
One illustrative method disclosed herein relates to performing a transaction-based verification of a semiconductor device in a design state. The method comprises creating a first plurality of transactions representing communication events between a central processing unit and a peripheral functional block of the semiconductor device. The method further comprises generating machine code instructions from the first plurality of transactions, wherein the machine code instructions contain at least some instructions executable by the central processing unit. Moreover, the method comprises enabling access to the at least some executable instructions by the central processing unit and checking a response of at least one of the peripheral functional block and the central processing unit to obtain verification information, wherein the response is caused by executing the at least some instructions by the central processing unit.
A further illustrative method disclosed herein comprises configuring a transaction-based test environment to create a sequence of transactions that are appropriate for use in a semiconductor device to be tested, wherein the semiconductor device is in a design state and comprises at least a central processing unit. The method further comprises converting the sequence of transactions into machine code representations and operating the central processing unit on the basis of the machine code representations to verify a functional behavior of the semiconductor device.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Generally, the subject matter disclosed herein relates to test benches or test environments operating on transaction level, thereby providing enhanced verification efficiency with respect to time and fault coverage compared to low level verification techniques, while additionally providing the potential for lowering the level of abstraction in order to enable the testing or verification of a central processing unit (CPU). For this purpose, the higher level of abstraction of the transaction-based test environment may be used for creating appropriate test scenarios, such as constraint-driven transaction streams, wherein respective responses may also be estimated on the level of transactions, while this high level resource may be made available for microprocessor verification by providing a transaction to machine code translator. Consequently, the test benches and test strategies disclosed herein may enable the verification of central processing units with high test coverage and high efficiency while also enabling an efficient re-use of the transaction-based test environment, thereby significantly reducing the overall effort for verification of complex semiconductor devices including CPUs and embedded peripheral function components. That is, CPU-based designs may be verified with high test coverage, while other embedded components may also be tested on transaction level, and these test environments may also be re-used in a test scenario with respect to the system as a whole.
As previously explained, the semiconductor device 200, i.e., the respective representation thereof in the form of software and/or hardware, may typically be tested with respect to its functional behavior prior to actually fully implementing the circuit configuration in hardware by means of volume production techniques. For this purpose, the semiconductor device 200 may be connected to a test environment 260, which may also be referred to as test bench, at any appropriate stage of the design of the semiconductor device 200. The test environment 260 may be provided in the form of a transaction-based environment which, as previously described, may be operated at an abstract level for communicating with the device 200 in order to inject appropriate stimulators, which in turn may result in a response of the device 200 or certain components thereof that may be evaluated in order to verify the functional behavior of the device 200 or individual components thereof. The test environment 260 may comprise a transaction generator 262 that is configured to provide a sequence or stream of transactions, each of which may represent a communication event between the CPU 201 and any peripheral component connected thereto via the interface system 205. Furthermore, the test environment 260 may comprise a module 269 configured to receive transactions from the generator 262, translate the transaction into machine code instructions readable to the CPU 201 and enable access via a communication link 269V to the translated machine code instructions by the CPU 201. For this purpose, the module 269 may comprise a transaction to machine code translator 269A in communication with a machine code interface 269B, which may be configured to enable access to the machine code instructions by the CPU 201. The translator 269A may, for instance, comprise an appropriate conversion function, for instance, in the form of a table or any other appropriate means in which a transaction is correlated with a respective representation of machine code instructions, wherein, typically, a plurality of machine code instructions may relate to a single transaction, as is previously explained. In some illustrative embodiments, the translator 269A may further comprise a randomization generator which may assign a specific machine code representation to an incoming transaction if more than one machine code representation is associated with the incoming transaction. In other cases, a transaction associated with two or more machine code representations, i.e., with two or more sequences of machine code instructions, may be converted into a respective sequence of machine code instructions including the members of several different machine code sequences of these representations, or even including all of the individual machine code instructions associated with the transaction under consideration. It should be appreciated that any other translation mechanism may also be used for the translator 269A.
The test environment 260 may further comprise a check module 267 that is connected to a monitor module 264 which in turn may be connectable to the interface system 205 so as to receive signal waveforms and to convert the signals into transactions, which may be evaluated in the check module 267. For example, the transaction generator 262 and/or the module 269, i.e., the interface 269B, may be connected to a reference model, as previously explained with reference to
During operation of the transaction-based test environment 260, the device 200 is connected to the module 269 in the embodiment shown via the interface 269B and via the monitor 264, and the transaction generator 262 may provide an appropriate sequence of transactions, wherein the generation of the transactions may be controlled by a supervising control module, as will be described later on in more detail. Upon receiving the stream of transactions, the translator 269A may provide respective machine code instructions which are then supplied to the CPU via the interface 269B, wherein the CPU 201 may run in its native mode, thereby executing any executable instruction produced by the translator 269A. Based on the machine code instructions, the CPU 201 may address any peripheral components, such as the functional block 202, which may be sampled by the monitor 264, which provides respective translated response transactions to the check module 267.
With reference to
In other illustrative embodiments, the interface 263 may additionally be configured so as to enable the translation of bus signals into transactions that may be forwarded to the module 260A for further evaluation on transaction level. Furthermore, the environment 260 may comprise a monitor 265 that is configured to translate bus signals into transactions, which may also be forwarded to the module 260A for further evaluation. Thus, by means of the module 260A, the interface 263 and the monitor 265, a transaction-based verification of the peripheral block 202 may be accomplished in a similar manner as is described with reference to
Again referring to
In other aspects, a self-test mechanism may be incorporated into the test scenario and finally into the target platform. For instance, a flow may be established for identifying appropriate transactions and using the test environment to provide the transactions via the transaction generator and the machine code translator. Hence, a self-test code may be embedded into the generated machine code, possibly based on a reference model. This code is configured to detect errors in the design possibly based on manufacturing errors. The self-test machine instructions may be traced and stored in a low-level memory model of the test environment, which may also comprise a test bench for simulating the behavior of the destination platform of the design under consideration, for instance, a computer main board. The stored self-test code may be stored in real memory (RAM, ROM, etc.) of the destination platform to perform an on-board functional production test.
As a result, the present invention provides efficient verification techniques and respective test benches for performing transaction-based verification for individual blocks of a system while also enabling transaction-based verification on system level. For this purpose, a transaction-based test environment comprises a transaction to machine code translator, which may provide respective machine code instructions in a memory area that is accessible by the CPU under test. Hence, full constraint driven test strategies may be applied at block level and system level, while additional efforts for modifying the transaction-based test environment may be maintained at a low level.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
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|U.S. Classification||702/117, 716/106|
|International Classification||G01R31/00, G06F17/50|
|Cooperative Classification||G06F11/263, G06F11/2236|
|European Classification||G06F11/263, G06F11/22A12|
|Nov 26, 2008||AS||Assignment|
Owner name: ADVANCED MICRO DEVICES, INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HAUFE, CHRISTIAN;KUEHN, INGO;LARSEN, DAVID;REEL/FRAME:021896/0517
Effective date: 20081016
|Aug 18, 2009||AS||Assignment|
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: AFFIRMATION OF PATENT ASSIGNMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:023120/0426
Effective date: 20090630
Owner name: GLOBALFOUNDRIES INC.,CAYMAN ISLANDS
Free format text: AFFIRMATION OF PATENT ASSIGNMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:023120/0426
Effective date: 20090630
|Jun 24, 2015||FPAY||Fee payment|
Year of fee payment: 4