|Publication number||US8099648 B2|
|Application number||US 13/099,254|
|Publication date||Jan 17, 2012|
|Filing date||May 2, 2011|
|Priority date||Mar 9, 2006|
|Also published as||CN101035141A, CN101035141B, CN103401636A, EP1833188A2, EP1833188A3, EP1833188B1, US7694204, US7937644, US20070260965, US20100153805, US20110209027|
|Publication number||099254, 13099254, US 8099648 B2, US 8099648B2, US-B2-8099648, US8099648 B2, US8099648B2|
|Inventors||Brian K. Schmidt, Lawrence Llewelyn Butcher|
|Original Assignee||Silicon Image, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (25), Non-Patent Citations (10), Referenced by (2), Classifications (12), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of and claims priority to U.S. patent application Ser. No. 12/712,124, filed Feb. 24, 2010, now issued as U.S. Pat. No. 7,937,644 on May 3, 2011, entitled “Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits”, and U.S. patent application Ser. No. 11/372,866, filed Mar. 9, 2006, now issued as U.S. Pat. No. 7,694,204 on Apr. 6, 2010, entitled “Error Detection in Physical Interfaces for Point-to-Point Communications Between Integrated Circuits”, the entire contents of which are hereby incorporated by reference.
This invention relates generally to an apparatus and method for providing reliable data communications between electronic devices, and more particularly, to a physical interface configured to efficiently detect errors at the physical interface during point-to-point transmission of data bits over a physical medium between electronic devices. In one embodiment, the point-to-point transmission of data bits employs low-amplitude, high-frequency signaling along a serial data link.
Point-to-point communication between electronic devices, such as integrated circuits (“ICs”), is generally considered to be reliable, especially when a dedicated synchronous clock line is used to synchronize data transfers. In particular, many system designers expect communications between ICs to conform to a prevailing assumption that data bits exchanged between ICs are the same data bits. For example, most conventional processor ICs are designed to act upon data fetched from a memory IC regardless of whether either the address bits transmitted to the memory IC were correctly received, or the data received by the processor IC were the same as sent by the memory IC. But with traditional physical interfaces both transmitting data bits at faster data rates and at decreasing amplitudes (i.e., decreasing transmission power), the effects of background noise on the strength of the data signals causes the signal-to-noise ratios to decrease, which is indicative of an increase in errors that could thwart reliable point-to-point communications. Further, many system designers are implementing physical interfaces that serially transport data over a serial data link using asynchronous clocking techniques, whereby the clock is embedded in encoded serialized data. Examples of high-speed serial communications technologies having serial data links include Serial ATA (“SATA”)®, Transition Minimized Differential Signaling (“TMDS”), PCI Express, InfiniBand®, and the like. While conventional physical interfaces that provide for serial data communications reduce both noise and power, at least one drawback is that conventional serial data links are susceptible to data corruption during transit.
In the field of computer networking, the Open Systems Interconnect (“OSI”) model describes a common approach to detect and correct errors between two end stations (or computing devices). According to this approach, a data link layer calculates an error-detecting code (e.g., a cyclic redundancy code, “CRC”) based on a frame of transmitted bits. Then, it appends the error-detecting code as contiguous bits to the frame and then passes both the error-detecting code and the application data bits to a physical interface for line encoding (or coding). One example of line encoding translates 8 application data bits into 10 encoded bits. This type of line encoding technique is commonly known as 8B/10B. After line encoding is performed, the serial physical interface drives the encoded bits out over a communications medium to another serial physical interface, which recovers the clock and decodes the bits. The data link layer at the receiver then applies error detection and correction techniques using the contiguous bits of error-detecting code.
While functional, the data link layer performs these error detection and correction processes beyond the physical interface, thereby delaying error detection and/or resolution. Also, conventional physical interfaces are generally not well suited to facilitate error detection and correction in a standardized manner. For example, traditional physical interfaces are optimized to provide synchronous and parallel data communications between integrated circuits. As such, they can not readily be adapted to provide timely and reliable data transfers for asynchronous and serial data communications, such as over a serial data link. Further, conventional physical interfaces are not generally conducive to at least provide: (1) transparent error detection and recovery techniques that do not require an application to participate in specialized error handling techniques, and (2) efficient transmissions of error detection codes to increase the rate that those codes are transferred over the serial data link.
In view of the foregoing, it would be desirable to provide a physical interface, an apparatus and a method that minimize the above-mentioned drawbacks and provides for at least error detection and optional error recovery.
An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. According to various embodiments of the invention, a physical interface can facilitate communications over either serial or parallel data links, or it can be configured to use either an embedded asynchronous clock or an external synchronous clock.
In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode a subset of encoded data bits to yield decoded data bits. It also includes a physical interface (“PI”) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits. As such, the apparatus uses the physical interface error detection bit to determine whether the encoded data bits include at least one erroneous data bit as an error. In some embodiments, the apparatus includes an error detector configured to operate within a physical layer. In at least one embodiment, the apparatus efficiently transmits error detection codes within, for example, an NB/(N+1)B line coder. The encoded data bits can be substantially direct current (“DC”)-balanced. Further, the encoded data bits can be configured to shape the spectral properties of emitted radiations. Also, those encoded data bits can also include an embedded asynchronous clock that can be used to recover a clock at a receiving device. In some instances, the apparatus includes an error detector configured to operate within a physical layer to detect errors. The error detector performs error detection earlier than at a data link layer or at any upper layers of the Open Systems Interconnection (“OSI”) seven-layer reference model. In some cases, the physical interface error detection bit is a parity bit, while in other instances, the physical interface error detection bit is a portion of an error-detection code. For example, the error-detection code can be a cyclic redundancy check (“CRC”) checksum. The error detector in this case is configured to accumulate the physical interface error detection bit as well as other physical interface error detection bits from other subsets of the encoded data bits (i.e., other code words) to reconstruct the error-detection code. Note that the error detector can be configured to generate a CRC checksum from the physical interface error detection bit and the other physical interface error detection bits. Then, the error decoder can compare the CRC checksum against the error-detection code to determine whether an error has occurred.
In various embodiments, the physical interface error detection bit is received at the apparatus concurrent with the subset of the encoded data bits and each of the other physical interface error detection bits are also received at the apparatus concurrent with each of the other subsets of the encoded data bits, thereby decreasing the time the apparatus receives the error-detection code that otherwise is appended to follow the encoded data bits. In at least one embodiment, the apparatus also includes an error corrector configured to correct the error. The error corrector can be configured to either request a retransmission of the subset of the encoded data bits, or signal an application-specific module that an error has been detected so that the application-specific module can resolve the error. Or, the error corrector can take default measures, such as reinitializing one or more ICs. Note that one of the subsets of the encoded data bits can include N+m data bits, which can be decoded to obtain N application data bits as decoded data bits. Also note, that the apparatus can be configured to receive encoded data bits as N+2 data bits and to provide N application data bits as outputs. For example, when N is 8, the apparatus is configured as an 8B/10B decoder, it provides nine decoded data bits: eight application data bits and one physical interface error detection bit for error detection.
In another embodiment of the invention, an apparatus for generating error-detection codes in a physical interface for the transmission of data between integrated circuits (“ICs”) is disclosed. In one embodiment, the apparatus is configured to operate as or within a transmitting physical interface. The apparatus can include an N bit-to-N+2 (“N bit/N+2”) bit physical layer (“PHY”) encoder. This encoder is configured to insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and to encode the N+1 unencoded data bits to yield N+2 encoded data bits. The apparatus also includes an error-detection code generator configured to generate a number of bits constituting an error-detection code, which includes the physical interface error detection bit. N can represent any integer number of data bits. The apparatus, in some cases, can include a serializer configured to serialize the N+2 encoded data bits to form serial N+2 encoded data bits, thereby interleaving single error-detection data bits with the serial N+2 encoded data bits. In at least one embodiment, the apparatus includes storage to store a group of data bits that include the N data bits. The error-detection code generator is configured to examine the group of data bits to generate an error-detection code. In a specific embodiment, the apparatus includes a transmitter (“TX”) error corrector configured to retransmit one or more subsets of the group of data bits when the transmitter error corrector receives a request for retransmission.
In yet another embodiment of the invention, a physical interface is formed as an integrated circuit (“IC”) on a first substrate to detect transmission errors in data exchanged with a core IC formed on a second substrate. The core IC is another IC that contains logic for implementing an application-specific function, such as a storage function of a memory chip. The physical interface includes a plurality of input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the core IC. The physical interface also includes one or more error recovery modules coupled between the plurality of input ports and output ports. At least one of the error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports. The error recovery module optionally can include a physical layer (“PHY”) decoder configured to detect errors in the in-bound encoded data bits and to initiate an action to correct the errors.
In still yet another embodiment of the invention, a high-speed serial communications link between at least two integrated circuits (“ICs”) is disclosed. This link includes a physical medium for conveying data, a transmitter device coupled to a first end of the physical medium, and a receiver device coupled to a second end of the physical medium. It also includes an error detector configured to determine an error using the physical interface error detection bits. Note that the transmitter device includes an N bit/N+2 bit encoder that generates encoded data bits with physical interface error detection bits encoded therein, and the receiver device includes an N+2 bit/N bit decoder, which decodes the encoded data bits, and an error detector to determine an error using the physical interface error detection bit. Note that the transmitter and receiver devices can be one or more of any of the following: a transition-minimized differential signaling (“TMDS”) device, a high-definition multimedia interface (“HDMI”) device, a multi-Gigabit Ethernet device (e.g., a 10 Gbps Ethernet, or “10 GbE,” device), and/or a serial advanced technology attachment (“SATA”) device. Note, too, that the transmitter and receiver devices can implement Digital Visual Interface (“DVI”) and/or Low Voltage Differential Signaling (“LVDS”), as well as any other equivalent technologies.
The invention is more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which:
Like reference numerals refer to corresponding parts throughout the several views of the drawings. Note that most of the reference numerals include one or two left-most digits that generally identify the figure that first introduces that reference number.
Physical interface 102 also includes a transmitter (“TX”) error recovery module 104, whereas physical interface 122 also includes a receiver (“RX”) error recovery module 124. Both error recovery modules 104 and 124 operate to detect errors and to optionally correct those errors either in association or in conjunction with line encoding or decoding. While
In a specific embodiment, error recovery modules 104 and 124 facilitate early error detection shortly after data bits arrive at a receiver (e.g., an IC or electronic device) such that error detection can be performed, for example, any time before, during or after line decoding. As such, error detection within physical interface 124 can prevent device 121 from performing other downstream processes unnecessarily with incorrect or corrupted data bits until error detection and correction techniques can be applied. Advantageously, error recovery modules 104 and 124 can conserve computational resources that otherwise might process corrupt data bits, and can also expedite communications between devices 101 and 121 by reducing the time required to detect and/or correct errors, according to various embodiments of the invention. Various features of the invention can also decrease the time to detect an error. For example, error detection bits can be transported in an interleaved fashion with application data bits rather than at an end of a group of data bits being transmitted, as is customary. In at least one embodiment, line encoder 106 uses a NB/(N+2)B line encoding for encoding a data stream for a serial data link. Further, line encoder 106 can operate to embed physical interface (“PI”) error correction bits in that the encoded data stream without affecting the rate at which application data bits are communicated over physical medium 110. Advantageously, physical interfaces 102 and 122 can implement low-level error detection and/or correction—in whole or in part—at the physical layer (or “PHY”) without requiring devices 101 and 121 to resolve errors. As such, PI error correction information can be transmitted along with the application data bits so as to be transparent to the operation of devices 101 and 121. Of course, error detection and/or correction for devices 101 and 121 can be supplemented by other error recovery techniques at circuits and/or layers beyond physical interfaces 102 and 122. As such, the application data bits can include upper-layer (“UL”) error detection bits for upper-layer error recovery mechanisms. As error detection and/or correction are performed at physical layers, error detection can advantageously be performed more quickly than if performed beyond physical interfaces 102 and 122.
Regardless of which layer implements conventional error detection and correction, traditional upper-level error detection codes are generally transmitted in a fashion similar to the payload. But according to various embodiments of the invention, low-level error detection codes and payload can be line-decoded differently, such as in parallel. As used herein, the term payload generally refers to a collection of bits (i.e., application data bits) that represent program instructions and/or program data used by an application layer. Application data bits constitute application data, and therefore do not contain control codes for controlling data bit transfer. By contrast, error detection codes are control codes as they are used to control the reliability of data bit transmissions. So according to the various embodiments, portions of both application data bits and error detection bits are line-decoded (and line-encoded) at or nearly at the same time (especially if the portions of both application data bits and error detection bits are together encoded to form a code word). In one embodiment, line decoders operate to translate a code word to form decoded data bits, which can include both application data bits and physical interface (“PI”) error detection bits. Note that traditional upper-level error detection codes are transmitted in groups of contiguous bits (e.g., the bits of a CRC checksum for an Ethernet frame) and are usually passed through line decoders to upper-layers in a manner similar to application data bits. Consequently, conventional upper-level error detection techniques generally expend computational resources to line-decode control codes for error recovery at upper-layers, whereas in accordance with at least a specific embodiment of the invention, low-level error detection codes need not be communicated anywhere other than to the physical layer.
Physical interface 210 is a serial physical interface configured to serially receive N+m encoded bits into a line decoder-error detector (“LD/ED”) 214, which is configured to decode some or all of the N+m encoded bits to form N decoded application data bits. The value “m” represents the difference in the number of bits from the number of encoded data bits and the number of application data bits. For example, an 8B/10B line encoder has an m of 2, which is the difference. Line decoder-error detector 214 operates to line decode encoded bits and then detect an error, if one is detectable. If line decoder-error detector 214 detects an error, then it instructs an error corrector (“EC”) 216 to take appropriate error recovery measures. In one embodiment, error corrector 218 is configured to transmit an error indication signal 218 to an external IC or device to alert the external IC or device so it can resolve the error, such as by retransmitting the N+m encoded bits to physical interface 210. Advantageously, physical interfaces 210 and 230 provide error detection and correction for core circuit 204 without modifying core circuit 204, thereby conserving engineering resources required to integrate either error detection or correction into core 204. In another embodiment, error corrector 218 is configured to transmit an error indication signal 220 into core circuit 204 so that it can correct the error. In this case, core circuit 204 includes application-specific logic 244 to correct any detected errors. Advantageously, error handling by application-specific logic 244 in core circuit 204 (or elsewhere) therefore enables error detection and correction without requiring the transmitting IC or device (not shown) to help correct the error. This minimizes the number of signal conductors and/or pins needed by electronic device 200, especially if it is encapsulated in a semiconductor package. In still yet another embodiment, error corrector 216 of physical interface 210 can correct errors without sending either error indication signals 218 or 220. For example, the error corrector can implement forward error correction techniques, which automatically corrects errors.
Next, consider that the external IC, for example, is a DRAM controller (not shown) and core circuit 204 is a DRAM memory. Then, physical interface 230 can provide a chip-to-chip interface to exchange error-corrected addresses and data between the DRAM controller and the DRAM memory (i.e., core circuit 204) without one or more of them being modified (functionally or structurally) to implement error detection and correction. In some embodiments, physical interfaces 210 and 230 are formed on a first substrate, which contains an input-output (“I/O”) ring 202. Core circuit 204 is formed on a second substrate. If the first and second substrates are separate, then physical interfaces 210 and 230 can be packaged separately from core circuit 204. But if they are formed on the same substrate, then they can be formed as part of a system-on-chip (“SOC”) and can be encapsulated together by a single package. In alternative embodiments, physical interface 230 is a parallel physical interface configured to receive N+m encoded bits into RX error recovery module 232 and then decode some or all of the N+m encoded bits to form N decoded application data bits.
In a specific embodiment, PHY line decoder 302 decodes the N+m−1 encoded bits, which is a subset of the N+m bits, to yield N decoded application data bits and E error detection bits. Then, error detection bit extractor 312 extracts one or more physical interface error detection bits for low-level error detection purposes. For example, error detection bit extractor 312 can extract a single bit from the quantity of N+m (e.g., 10 bits) to yield N+m−1 bits (e.g., 9 bits) decoded bits, which include N decoded application data bits and E decoded error detection bits. As such, PHY line decoder 302 is configured to receive N+m bits, and to perform line decoding, which yields N application data bits and at least one error detection bit. Advantageously, PHY line decoder 302 can be implemented to supplement or replace a conventional 10B/8B decoder, which uses a commonly-used symbol size of 10 bits for the encoded bits, with the decoded application data bits having a bit size of 8 bits. In various embodiments of the invention, PHY line decoder 302 examines a 9th bit (i.e., one of the two bits of the difference between 10 encoded and 8 decoded application data bits) to detect errors. A suitable PHY line decoder 302 is an N+1 bit/N bit decoder as described in U.S. Pat. No. 6,747,580 titled “Method and Apparatus for Encoding or Decoding Data in accordance with an NB/(N+1)B Block Code and Method for Determining such a Block Code,” which is incorporated by reference in its entirety for all purposes. Note that while
After extraction, error detection bit extractor 312 then sends the physical interface (“PI”) error detection bit (“EDB”) 313 to error detector 314, which uses that bit to determine whether the N+m encoded data bits include one or more erroneous data bits. Error detector 314 is configured to detect errors in accordance with any number of error detection techniques and codes. In one embodiment, error detector 314 is configured as either an even or odd parity checker, with the physical interface error detection bit being a parity bit (i.e., either an even or odd parity bit). Advantageously, the physical interface error detection bits are received at PHY line decoder 302 concurrent with subsets of application data bits that undergo decoding. This can decrease the amount of time required for PHY line decoder 302 to receive the error-detection code in comparison to conventional error detection techniques that append an error detection code to the end of a group of encoded data bits, where the group can have a bit size much greater than N+m bits. In another embodiment, the physical interface error detection bit is a portion (e.g., one bit) of a CRC checksum. In this case, an error-detection code generator in a transmitting physical interface (not shown) is configured to generate the physical interface error detection bit as part of a CRC checksum. As is discussed below in
Once error detector 314 determines that an error has occurred during data bit transmission, then it signals to error corrector 316 that such an error has occurred. In some cases, error corrector 316 operates to request a retransmission of the decoded application data bits for which an error has been detected. Continuing with the previous example, if the 16-bit CRC checksum comparison indicates that an error exists in the 128 decoded application data bits, then error corrector 316 can request that the transmitting physical interface resend those 128 bits. In other cases, error corrector 316 can activate an application-specific circuit to perform user-defined error handling. In at least one instance, error corrector 316 can take some sort of default error-correcting action, such as reinitializing an associated IC, like a core circuit described above.
Transmitter physical interface 410 then sends the encoded bits via physical medium 420 to error bit extractor 422 of a receiving physical interface (“RX”) 440. Receiving physical interface (“RX”) 440 includes a PHY line decoder 428, an error bit extractor 422, error detection code reconstructor 426, an error detector 430, a comparator 434, and a buffer 431, which can maintain the decoded application data bits pending confirmation that no errors are detected. PHY line decoder 428 decodes the 10 encoded data bits into 9 decoded bits, which includes 8 decoded application data bits and 1 decoded error detection bit (“EDB”) 424. In various embodiments, PHY line decoder 428 includes clock data recovery circuits (not shown) to recover the embedded clock transmitted over physical medium 420 with the encoded application data bits. Error bit extractor 422 extracts error-detection bit 424 from the 9 decoded bits and provide it to error detection code reconstructor 426, which accumulates the error detection bit with other physical interface error detection bits. Next, error detection code reconstructor 426 reconstructs the error detection code, which was originally generated by error detection code generator 416. Next, error detector 430 generates a CRC checksum 432 based on a group of N decoded application data bits in buffer 431. Then, comparator 434 can operate to compare whether CRC checksum 432 matches error detection code 426. If it does, then there is no error; if it does not, then there is an error.
The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the invention. In fact, this description should not be read to limit any feature or aspect of the invention to any embodiment; rather features and aspects of one embodiment may readily be interchanged with other embodiments. For example, although the above descriptions of the various embodiments relate to physical layer line decoders, the discussion is applicable to physical layer line encoders and all types of communications links, as well as many types of communications protocols, such as Gigabit Ethernet, HDMI, TMDS, DVI and SATA. Also, the various embodiments are applicable to point-to-point communications between electronic devices as well as broadcasting from one to many. While some of the above discussions relate to serial data communication, the various embodiments of the invention can apply to parallel data communications as well.
Thus, the foregoing descriptions of specific embodiments of the invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed; obviously, many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications; they thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. Notably, not every benefit described herein need be realized by each embodiment of the invention; rather any specific embodiment can provide one or more of the advantages discussed above. It is intended that the following claims and their equivalents define the scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5923680||Jun 5, 1997||Jul 13, 1999||Northern Telecom Limited||Error correction in a digital transmission system|
|US5974544 *||Oct 1, 1996||Oct 26, 1999||Dell Usa, L.P.||Method and controller for defect tracking in a redundant array|
|US6292517 *||Sep 15, 1998||Sep 18, 2001||Tut Systems, Inc.||Method and apparatus for detecting a data signal on a carrier medium|
|US6324669 *||Nov 17, 1998||Nov 27, 2001||Seagate Technology Llc||Method and apparatus for using CRC for data integrity in on-chip memory|
|US6421803||Oct 4, 1999||Jul 16, 2002||Telefonaktiebolaget L M Ericsson (Publ)||System and method for implementing hybrid automatic repeat request using parity check combining|
|US6594262||Aug 19, 1998||Jul 15, 2003||Electronics And Telecommunications Research Institute||Apparatus and method for protecting ATM header from the burst error|
|US6662332||Nov 1, 2000||Dec 9, 2003||3Com Corporation||Interleaver for burst error correction|
|US6735217 *||Sep 15, 1998||May 11, 2004||Tut Systems, Inc.||Method and apparatus for detecting collisions on a network using multi-cycle waveform pulses|
|US6747580||Jun 12, 2003||Jun 8, 2004||Silicon Image, Inc.||Method and apparatus for encoding or decoding data in accordance with an NB/(N+1)B block code, and method for determining such a block code|
|US7010607 *||Sep 14, 2000||Mar 7, 2006||Hewlett-Packard Development Company, L.P.||Method for training a communication link between ports to correct for errors|
|US7111220||Mar 1, 2002||Sep 19, 2006||Xilinx, Inc.||Network physical layer with embedded multi-standard CRC generator|
|US7248587 *||Apr 11, 2005||Jul 24, 2007||Azul Systems, Inc.||Error recovery of variable-length packets without sequence numbers or special symbols used for synchronizing transmit retry-buffer pointer|
|US7280293 *||Jul 18, 2005||Oct 9, 2007||International Business Machines Corporation||Multi-level mapping of tape error recoveries|
|US7343540||Apr 25, 2002||Mar 11, 2008||Pmc - Sierra Israel Ltd.||Forward error correction coding in ethernet networks|
|US7430261||Jul 7, 2003||Sep 30, 2008||Robert Bosch Gmbh||Method and bit stream decoding unit using majority voting|
|US7499500||Mar 18, 2004||Mar 3, 2009||Sony United Kingdom Limited||Data communication system, method and apparatus for communicating a data signal formed of successive data elements|
|US7519084 *||Oct 8, 2004||Apr 14, 2009||Mitsubishi Denki Kabushiki Kaisha||Error control mechanism for a segment based link layer in a digital network|
|US20030070132||Dec 27, 2001||Apr 10, 2003||Christopher Pasqualino||Flexible video encoding scheme supporting audio and auxiliary information|
|US20030185251||Mar 17, 2003||Oct 2, 2003||Nec Corporation||Multiplex transmission system capable of using ordinary network packets to transmit a plurality of 8B/10B bit streams|
|US20030237041||Jan 22, 2003||Dec 25, 2003||Cole Robert M.||System and method for transferring data on a data link|
|US20050005189||Apr 25, 2002||Jan 6, 2005||Lior Khermosh||Forward error correction coding in ethernet networks|
|US20060041820||Feb 9, 2005||Feb 23, 2006||Ling Hang||Method and apparatus for receiving a control channel in a wireless communication system|
|US20070157060||Jan 4, 2006||Jul 5, 2007||Ganga Ilango S||Techniques to perform forward error correction for an electrical backplane|
|CN2662571Y||Aug 22, 2002||Dec 8, 2004||交互数字技术公司||Single-Carrier Frequency-Domain Equalization (SC-FDE) subscriber equipment with automatic physical layer request retransmission mechanism|
|EP1351462A1||Mar 25, 2003||Oct 8, 2003||MystiCom, Ltd.||Error Correcting 8B/10B Transmission System|
|1||Extended European Search Report for European Patent Application No. 07250987.0, Mailed Jun. 6, 2011, 7 pages.|
|2||Letter from Foreign Associate reporting Office Action for Taiwan Patent Application No. 096107301 mailed Oct. 1, 2010, 2 pages.|
|3||Non-Final Office Action for U.S. Appl. No. 11/372,866 mailed Apr. 30, 2009, 8 pages.|
|4||Notice of Allowance for U.S. Appl. No. 11/372,866 mailed Nov. 18, 2009, 13 pages.|
|5||Notice of Allowance for U.S. Appl. No. 12/712,124 mailed Sep. 13, 2010, 8 pages.|
|6||Office Action for Chinese Patent Application No. 200710087760.0 mailed Jan. 12, 2011, 19 pages.|
|7||Partial European Search Report for European Patent Application No. 07250987.0 mailed Feb. 17, 2011, 5 pages.|
|8||Restriction Requirement for U.S. Appl. No. 11/372,866 mailed Feb. 24, 2009, 12 pages.|
|9||Supplemental Notice of Allowance for U.S. Appl. No. 12/712,124 mailed Mar. 17, 2011, 6 pages.|
|10||USPTO, Non-final Office Action for U.S. Appl. No. 12/712,124 mailed Jun. 2, 2010, 8 pages.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8416717 *||Jul 29, 2010||Apr 9, 2013||Stmicroelectronics S.R.L.||Signals communication apparatus|
|US20110026544 *||Jul 29, 2010||Feb 3, 2011||Stmicroelectronics S.R.L.||Signals communication apparatus|
|U.S. Classification||714/758, 714/781, 714/799|
|Cooperative Classification||H04L2001/0092, H04L25/4908, H04L1/0061, H04L1/0045|
|European Classification||H04L1/00B7E, H04L1/08, H04L1/00B5, H04L25/49L1|
|Mar 19, 2015||AS||Assignment|
Owner name: JEFFERIES FINANCE LLC, NEW YORK
Free format text: SECURITY INTEREST;ASSIGNORS:LATTICE SEMICONDUCTOR CORPORATION;SIBEAM, INC.;SILICON IMAGE, INC.;AND OTHERS;REEL/FRAME:035226/0147
Effective date: 20150310
|Jul 17, 2015||FPAY||Fee payment|
Year of fee payment: 4
|Aug 21, 2015||AS||Assignment|
Owner name: LATTICE SEMICONDUCTOR CORPORATION, OREGON
Free format text: MERGER;ASSIGNOR:SILICON IMAGE, INC.;REEL/FRAME:036419/0792
Effective date: 20150513