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Publication numberUS8114765 B2
Publication typeGrant
Application numberUS 12/754,602
Publication dateFeb 14, 2012
Filing dateApr 5, 2010
Priority dateDec 31, 2008
Also published asUS8372740, US8658526, US20100193916, US20120135603, US20130183829
Publication number12754602, 754602, US 8114765 B2, US 8114765B2, US-B2-8114765, US8114765 B2, US8114765B2
InventorsHuiwen Xu, Yung-Tin Chen, Steven J. Radigan
Original AssigneeSandisk 3D Llc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods for increased array feature density
US 8114765 B2
Abstract
The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.
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Claims(21)
What is claimed is:
1. A method of making a semiconductor device, comprising:
patterning a first feature array on a substrate, wherein the first feature array comprises a plurality of completely distinct features;
depositing a first layer on the first feature array;
removing a portion of the first layer to form sidewall spacers and spacer regions;
filling the spacer regions with a selective material to form filler features; and
removing the sidewall spacers to form a second feature array having features and filler features.
2. A method as recited in claim 1, wherein the features and filler features of the second feature array define the second feature array as having at least twice the density of first feature array.
3. A method as recited in claim 1, wherein the first feature array comprises at least one pillar structure.
4. A method as recited in claim 1, wherein the second feature array comprises a two-dimensional structure.
5. A method as recited in claim 1, wherein the second feature array comprises a three-dimensional structure.
6. A method as recited in claim 1, wherein the substrate comprises a material selected from the group consisting of metal, a dielectric material, and silicon.
7. A method as recited in claim 1, wherein the second feature array is patterned using a surface activation technique.
8. A method as recited in claim 1, wherein the second feature array is patterned using plasma enhanced chemical vapor deposition (PECVD).
9. A method as recited in claim 1, wherein the selective material is applied using a directional gap fill technique.
10. A method as recited in claim 1, wherein the second feature array comprises a carbon material.
11. A method as recited in claim 1, wherein the first layer comprises a nitride material.
12. A method as recited in claim 1, wherein the first removing step is accomplished by etching.
13. A method as recited in claim 1, wherein an optional carrier gas can be applied to the spacer and spacer regions prior to applying the selective material.
14. A method as recited in claim 13, wherein the optional carrier gas is selected from the group consisting of He, Ar, H2, Kr, Xe, and N2.
15. A method as recited in claim 1, wherein an optional etchant gas can be applied to the spacer and spacer regions prior to applying the selective material.
16. A method as recited in claim 15, wherein the optional etchant gas comprises a gas selected from the group consisting of H2, F, Cl, and Br.
17. A method as recited in claim 1, wherein the selective material comprises a carbon material of the form CxHy, wherein x is an odd or even number greater than 1, and y is 2x.
18. A method as recited in claim 1, wherein the selective material comprises a material selected from the group consisting of carbon, tungsten, and silicon, and their associated isotopes.
19. A method for increasing array density of features having sidewall spacers and spacer regions, comprising:
filling the spacer regions of the feature array with a selective material to form filler features, wherein the feature array comprises a plurality of completely distinct features; and
removing the sidewall spacers of the feature array to form filler features in the spacer regions and increase the density of the feature array.
20. A method for increasing pattern array density of pillars having sidewall spacers and spacer regions, comprising:
filling the spacer regions of the array pattern with a selective material, wherein the array pattern comprises a plurality of completely distinct pillars; and
removing the sidewall spacers of the array pattern pillars to form additional pillars in the spacer regions and increase the density of the pattern array.
21. A semiconductor device produced by a method for increasing pattern array density of pillars having sidewall spacers and spacer regions, comprising:
filling the spacer regions of the array pattern with a selective material, wherein the array pattern comprises a plurality of completely distinct pillars; and
removing the sidewall spacers of the array pattern pillars to form additional pillars in the spacer regions and increase the density of the pattern array of the semiconductor device.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of non-provisional U.S. patent application Ser. No. 12/318,609, entitled “Resist Feature and Removable Spacer Pitch Doubling Patterning Method for Pillar Structures”, filed Dec. 31, 2008. This application also claims priority to U.S. Provisional Patent Application Ser. No. 61/260,813, entitled “Methods and Apparatus to Increase Pattern Density by 2× Using Gapfill of PECVD C,” filed Nov. 12, 2009. Both of these applications are hereby incorporated by reference in their entirety. All literature and similar materials cited in this application, including but not limited to, patents, patent applications, articles, books, treatises, and internet web pages, regardless of the format of such literature and similar materials, are expressly incorporated by reference in their entirety for any purpose.

BACKGROUND

Various semiconductor materials are used to create memory circuits, electronic devices, and systems. Semiconductor materials are particularly effective since they can be designed, fabricated, and manipulated on small scale. Semiconductor memory circuits are components in these devices which store both data and instructions. Therefore, efforts have focused primarily on trying to maximize the density or efficiency of semiconductor memory circuits while lowering their cost.

A number of tools and techniques are now available for fabricating memory circuits and their associated parts. However, as the dimensions are diminished, so are the tools and methods to make and fabricate these devices. Fabricating devices smaller than 80 nm requires complicated processes and tools. It is desirable, therefore, to simplify memory devices and methods while at the same time maximizing their feature array density. One such process that attempts to accomplish this objective is the technique of double exposure/double patterning. Another process can be the use of sidewall spacers formed on a template pattern which is then removed. The sidewall spacers are then used as a mask during etching of the underlying film or films.

The above mentioned methods have the effect of dividing the photolithography-produced pitch by two. This provides certain benefits in slightly improving feature array density. However, these techniques have limited applicability and effectiveness for higher order arrays such as two or three-dimensional feature arrays. Further, the above mentioned techniques suffer from the limitation that numerous steps are required to build the memory circuits or devices. In addition, in many cases the required tools and techniques limit the overall materials that can be employed for these feature arrays.

For these reasons, what is needed is a novel method that utilizes semiconductor materials and can improve overall feature array density and quality used for memory circuits and devices. Further these methods and devices must be simple to implement and design and not require complicated processes or tools.

SUMMARY

The embodiments generally relate to methods of making semiconductor devices, and more particularly, to memory circuits, devices and methods for making semiconductor pillar structures and increasing array feature pattern density using selective gap fill. The technique has application to a variety of materials and can be applied to making monolithic two and three-dimensional memory arrays.

The embodiments also provide methods for increasing array density of features having sidewall spacers and spacer regions, comprising filling the spacer regions of the feature array with a selective material to form filler features, and removing the sidewall spacers of the feature array to form filler features in the spacer regions and increase the density of the feature array.

The embodiments also provide methods of making semiconductor devices, comprising patterning a first feature array on a substrate, depositing a first layer on the first feature array, removing a portion of the first layer to form sidewall spacers and spacer regions, filling the spacer regions with a selective material to form filler features, removing a portion of the second layer covering the spacers regions, and removing the sidewall spacers to form a second feature array having features and filler features.

The embodiments also provide semiconductor devices produced by a method for increasing pattern array density of pillars having sidewall spacers and spacer regions, comprising, filling the spacer regions of the array pattern with a selective material, and removing the sidewall spacers of the array pattern pillars to form additional pillars in the spacer regions and increase the density of the pattern array of the semiconductor device.

These and other features of the present teachings are set forth herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The skilled artisan will understand that the drawings, described below, are for illustration purposes only. The drawings are not intended to limit the scope of the present teachings in any way.

FIG. 1 is a perspective view of a nonvolatile memory cell.

FIG. 2 is a perspective view of an array of memory cells of FIG. 1.

FIGS. 3 a through 3 d are cross-sectional side views illustrating steps in the process of forming conductive rails by a subtractive method.

FIGS. 4 a through 4 d are cross-sectional side views illustrating steps in the process of forming conductive rails by a Damascene method.

FIG. 5 is a cross-sectional side view of the device layers prior to the formation of the pillar structures.

FIGS. 6 through 10 are cross-sectional side views (Figures with subpart a) and top views (Figures with subpart b) of process steps of making a device array according to some embodiments of the teachings.

FIG. 11A shows a cross-sectional view of a first process step of making a device according to some embodiments of the present teachings.

FIG. 11B shows a top view of the process step shown in FIG. 11A.

FIG. 12A shows a cross-sectional view of a second process step of making a device according to some embodiments of the present teachings.

FIG. 12B shows a top view of the second process step shown in FIG. 12A.

FIG. 13A shows a cross-sectional view of a third process step of making a device according to some embodiments of the present teachings.

FIG. 13B shows a top view of the third process step shown in FIG. 13A.

FIG. 14A shows a cross-sectional view of a fourth process step of making a device according to some embodiments of the present teachings.

FIG. 14 B shows a top view of the fourth process step shown in FIG. 14A.

FIG. 15A shows a cross-sectional view of a fifth process step of making a device according to some embodiments of the present teachings.

FIG. 15B shows a top view of the fifth process step shown in FIG. 15A.

FIG. 16A shows a cross-sectional view of a sixth process step of making a device according to some embodiments of the present teachings.

FIG. 16B shows a top view of the sixth process step shown in FIG. 16A.

DESCRIPTION OF VARIOUS EMBODIMENTS

For the purpose of interpreting this specification, the following definitions will apply and whenever appropriate, terms used in the singular will also include the plural and vice versa. In the event that any definition set forth below conflicts with the usage of that word in any other document, including any document incorporated herein by reference, the definition set forth below shall always control for purposes of interpreting this specification and its associated claims unless a contrary meaning is clearly intended (for example in the document where the term is originally used). The use of “or” means “and/or” unless stated otherwise. The use of “a” herein means “one or more” unless stated otherwise or where the use of “one or more” is clearly inappropriate. The use of “comprise,” “comprises,” “comprising,” “include,” “includes,” and “including” are interchangeable and not intended to be limiting. Furthermore, where the description of one or more embodiments uses the term “comprising,” those skilled in the art would understand that, in some specific instances, the embodiment or embodiments can be alternatively described using the language “consisting essentially of” and/or “consisting of.”

In describing and claiming the embodiments, the following terminology will be used with the definitions set out below.

The term “selective material” refers to materials adapted to function as a hard mask material. For instance, carbon, silicon, amorphous silicon or carbon, and tungsten can be employed as hard mask materials. Other known or not known materials having similar functional properties can also be employed.

The term “surface activation technique” or “surface activate”, refers to any method or technique adapted to activate a surface for reaction. For instance, plasma enhanced chemical vapor deposition (PECVD) can be used to “surface activate” carbon surfaces by anisotropic bombardment. Other similar techniques and methods are also possible that produce similar surface activations. For instance, other methods that produce ionic surfaces can also be employed.

While the present teachings are described in conjunction with various embodiments, it is not intended that the present teachings be limited to such embodiments. On the contrary, the present teachings encompass various alternatives, modifications, and equivalents, as will be appreciated by those of skill in the art.

The present inventors realized that instead of using sidewall spacers as a mask for etching device layers, the sidewall spacers can instead be used as sacrificial spacers when forming the etching mask. Once the etching mask is formed, the sidewall spacers are removed and portions of the device layers located below the former sidewall spacer locations are removed to leave spaced apart devices, such as pillar shaped devices.

For example, one or more device layers are first formed over a substrate. Any suitable substrate can be used, such as a semiconductor wafer (including silicon or compound semiconductor wafers) or a metal, glass, ceramic or plastic substrate. The substrate can be covered by one or more insulating layers and/or one or more devices, such as driver circuits, can be formed on or in the substrate. The device layers can comprise semiconductor layers for semiconductor devices, electrically conductive layer or layers which form electrodes, and/or insulating layers for isolation of the semiconductor or conductive portions of the devices.

At least two spaced apart features are then formed over the device layers. A plurality (i.e., more than two) features are formed to form a large device array. The features can be formed directly on or above semiconductor, conductive and/or insulating device layers. The features can have any shape as long as these features can subsequently function as an etching mask for etching the underlying device layers.

For example, as will be described in more detail below, the features can have a cylindrical shape. However, other shapes, such as rectangular or triangular shape can also be used if rectangular or triangular devices are to be formed. The features can have any desired size, and have the same width as the desired width of the underlying devices. The features should have a sufficient height or thickness to act as an etching mask. The features comprise an imagable material, such as an imagable polymer material, including a photoresist material (including visible and UV imagable photoresist material), an electron beam imagable resist material or a nanoimprint lithography imagable resist material. Thus, by using an imagable material rather than a non-imagable material for the features, a separate etching step used to etch non-imagable features can be omitted. Optionally, a trimming step can be conducted to reduce the size of the spaced apart features. Any suitable trimming method, for example, dry etching, can be used for trimming the spaced apart features.

Sidewall spacers are then formed on the features. Sidewall spacers can be formed by conventional sidewall spacer formation methods, such as by depositing a film over the features and then anisotropically etching the film to leave sidewall spacers on the features. The spacers can be made of a conductive, insulating or semiconductor material different from that of the upper portions of the features. The sidewall spacer material can be selected i) such that it can be selectively anisotropically etched with dry etch chemistry compared to the material of the spaced apart features; and ii) such that it can be selectively removed (such as isotropically etched) compared to the material of the spaced apart features using a different dry or wet etch chemistry. For example, when the features comprise an imagable material, such as photoresist material, the spacers can be formed from silicon oxide or silicon nitride. Other material combinations can also be used.

Subsequently, the spaces between adjacent spacers located on adjacent features are filled with so-called filler features. The filler features can be formed by forming a filler film or layer over and between the features and the sidewall spacers. The filler film comprises a flowable material and/or can be deposited by liquid phase deposition, such as spin-on coating. For example, the filler film can comprise any suitable imagable or non-imagable polymer material that has a viscosity of about 1 to about 15 centipoise to render it flowable and can be deposited by liquid phase deposition. The flowable filler material fills the spaces between the spacers and exposes the upper portions of the spaced apart features and the spacers without the need to remove the upper portions of the flowable filler material. The resulting filler features have about the same height as the spaced apart features made of the imagable material. If a non-flowable material is used for the filler film, then an upper portion of the filler film can be removed by etching or polishing to expose upper portions of the sidewall spacers. The filler film material can comprise the same material as the imagable feature material (i.e., photoresist, e-beam resist or nanoimprint lithography resist) of the spaced apart features or a different material from the imagable material, but which has a similar etch characteristics or etch resistance to that of the imagable material with respect to the spacer material etching medium (i.e., which resists the etching gas or liquid which will be used to etch the spacers to about the same degree as the imagable material). The filler film material should be different from the material of the sidewall spacers so that the sidewall spacers can be selectively etched compared to the spaced apart imagable material features and the filler features.

After the filler features are formed, the sidewall spacers are selectively removed. The step of selectively removing comprises selectively etching the material of the sidewall spacers without substantially removing the original imagable spaced apart feature or filler feature material. The removal can be performed by selective wet etching for example. The removal of the spacers leaves the spaced apart features and the filler features spaced apart from each other.

The spaced apart features and filler features then function as etching mask during the etching of the underlying hard mask and/or device layers. The hard mask and/or device layers can be etched using isotropic or anisotropic etching using the spaced apart features and the filler features as a mask. Optionally, prior to the step of etching the hard mask and/or device layers, the filler features can be trimmed to reduce their sizes and/or to round their corners. Any suitable trimming method, for example, dry etching, can be used for trimming the filler features. In some embodiments, the spaced apart features can be trimmed during the step of trimming the filler features. The spaced apart features and/or filler features can be removed after etching the hard mask or device layers.

Any suitable devices can be formed. The devices can have a substantially cylindrical and/or substantially rectangular pillar shape, depending on the shape of the features and the filler features, as will be described in more detail below. Non-pillar shaped devices can also be formed. The devices can comprise diodes, transistors, resistors, anti fuse dielectrics, fuses, resistivity-switching materials, capacitors, etc. Logic, volatile memory or nonvolatile memory devices or arrays can be formed.

In a non-limiting embodiment, a plurality of pillar shaped devices which comprise a plurality of diode containing nonvolatile memory cells are formed. Referring to FIG. 1, U.S. Pat. No. 6,952,030, issued to Herner et al. and entitled “High-Density Three-Dimensional Memory Cell,” hereinafter the “'030 patent” and hereby incorporated by reference, discloses an exemplary nonvolatile memory cell which can be formed by the method of the embodiments of the present teachings.

The memory cell 20 includes a vertically oriented, cylindrical pillar shaped junction diode. The term junction diode is used herein to refer to a semiconductor device with the property of non-ohmic conduction, having two terminal electrodes, and made of semiconducting material which can be p-type at one electrode and n-type at the other. Examples include p-n diodes and n-p diodes, which have a p-type semiconductor material and an n-type semiconductor material in contact, such as Zener diodes, and p-i-n diodes, in which an intrinsic (undoped) semiconductor material can be interposed between the p-type semiconductor material and the n-type semiconductor material.

The diode 22 and an optional antifuse dielectric 24 are interposed between top 26 and bottom 28 conductors or electrodes. The vertically oriented junction diode 22 includes a heavily doped semiconductor region 30 of a first conductivity type (such as n-type), an intermediate region 32 which can be undoped semiconductor material or lightly doped semiconductor material (which will be referred to as an intrinsic region), and a heavily doped semiconductor region 34 of the second conductivity type (such as p-type) to form a p-i-n diode. If desired, the location of the p and n-type regions can be reversed. The semiconductor material of the junction diode 22 can be generally silicon, germanium, or an alloy of silicon and/or germanium. Other semiconductor materials can also be used. The junction diode 22 and the antifuse dielectric 24 are arranged in series between the bottom conductor 28 and the top conductor 26, which can be formed of a metal, such as tungsten and/or TiN. The antifuse dielectric 24 can be located above or below the diode 22.

The memory cell can comprise a one-time programmable (OTP) or re-writable nonvolatile memory cell. For example, each diode 22 can act as a steering element of a memory cell and another material or layer 24 which acts as a resistivity switching material (i.e., which stores the data) is provided in series with the diode between the conductors. Specifically, instead of the antifuse dielectric, the resistivity switching material 24 can comprise a fuse, polysilicon memory effect material, metal oxide (such as nickel oxide, perovskite materials, etc,), carbon nanotubes, phase change materials, switchable complex metal oxides, conductive bridge elements, or switchable polymers. The resistivity of the resistivity switching material 24 can be increased or decreased in response to a forward and/or reverse bias provided between the electrodes or conductors.

Briefly, the cell 20 operates as follows. In the initial state, very little current flows through the junction diode 22 when a read voltage is applied between the top conductor 26 and the bottom conductor 28 because the antifuse dielectric 24 impedes current flow. The application of a programming voltage between the top conductor 26 and bottom conductor 28 causes dielectric breakdown of the antifuse material, permanently forming a conductive path through the antifuse 24. If the diode semiconductor material is initially formed in a high resistivity state, then the semiconductor material of diode 22 can be altered as well, changing it to a lower-resistivity state. After programming, a higher read current flows between the top conductor 26 and the bottom conductor 28 upon application of a read voltage. In this way, a programmed cell can be distinguished from an unprogrammed cell.

In alternative embodiments, the antifuse dielectric 24 can be omitted. Instead, the polycrystalline semiconductor material of diode 22 can be formed in a relatively high-resistivity state, which also tends to impede current flow, as described in a U.S. patent application Ser. No. 10/955,549, “Nonvolatile Memory Cell Without a Dielectric Antifuse Having High- and Low-Impedance States,” filed by Herner et al. on Sep. 29, 2004 and hereinafter the “'549 application”; and U.S. patent application Ser. No. 11/148,530, “Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor Material,” filed by Herner et al. on Jun. 8, 2005 and hereinafter the “'530 application,” both hereby incorporated by reference. The application of a programming voltage lowers the resistivity state of the diode. Thus, the diode acts as a resistivity switching material in this embodiment.

Referring to FIG. 2, a portion of a first memory level 36 of memory cells 20 similar to the cell 20 of FIG. 1 is shown. Two, three, four, or more such memory levels, such as eight levels can be formed, stacked one atop the other, to form a monolithic three dimensional memory array, formed above a substrate such as a monocrystalline silicon wafer, and described in the '030 patent and the '549 and '530 applications. The diode pillars 22 have a pitch of less than 100 nm, such as pitch of 78 nm or less and a diameter of 100 nm or less, such as 50 nm or less, such as 32 nm for example.

The bottom electrodes or conductors 28 can be formed either by subtractive or by Damascene methods. In a subtractive method, a conductive layer or film can be patterned into spaced apart electrodes and the gaps between the electrodes are then filled with an insulating material. In a Damascene method, grooves are formed in an insulating material, a conductive layer or film can be formed in the grooves and over the insulating layer, and then the conductive layer or film can be planarized to leave spaced apart electrodes in the grooves.

FIGS. 3 a-3 d illustrate the subtractive method of forming rail-shaped electrodes or conductors 28. As shown in FIG. 3 a, one or more conductive layers 40, such as a W and/or a TiN layers are deposited over a substrate, and a layer of photoresist 42 is spun onto it. As shown in FIG. 3 b, the layer of photoresist 42 is then photolithographically patterned into the desired form. As shown in FIG. 3 c, an etch step removes portions of the conductive layer(s) 40 where they are not protected by etched photoresist layer 42. As shown in FIG. 3 d, after the etch, the photoresist layer 42 can be stripped, leaving conductor or electrode rails 40 behind. The gaps between the rails 40 are filled with an insulating material 44, such as silicon oxide, silicon nitride or other insulating materials. If desired, any overfill of the insulating material 44 can be removed, for example by chemical-mechanical polishing (CMP), to expose the upper surface of the rails 40 in the planarized surface of the insulating layer 44.

FIGS. 4 a to 4 d illustrate the Damascene method to form the electrode or conductor 28. First, a layer of photoresist 48 can be spun onto a deposited insulating layer 50, such as a silicon oxide layer. As shown in FIG. 4 b, the layer of photoresist 48 can be patterned. An etch step then forms grooves or trenches 52 in the insulating layer 50. In FIG. 4 c, after removal of the photoresist layer 48, one or more conductive layers 46, such as a W and/or TiN layers are deposited to fill the grooves or trenches 52. The one or more conductive layers 46 are planarized, for example by CMP or etchback, with the upper surface of the insulating layer to leave the rail shaped conductors in the grooves, as shown in FIG. 4 d.

FIG. 5 shows an initial stage of fabrication of a semiconductor device, such as a pillar shaped nonvolatile memory cell array 110, according to some embodiments of the teachings. The array 110 contains a plurality of bottom electrodes 114 formed by the subtractive or Damascene methods described above with respect to FIG. 3 or 4 respectively. The electrodes 114 correspond to the rail shaped conductors 28 shown in FIGS. 1 and 2. The electrodes 114 can comprise any suitable conductive material, such as tungsten, aluminum, their alloys, etc. The electrodes 114 are separated from each other by an insulating material 116, such as silicon oxide. An optional adhesion layer 118 can be formed above the electrodes 114. The adhesion layer can comprise titanium nitride or tungsten nitride. The optional antifuse dielectric layer 120 can be deposited over the adhesion layer 118. The antifuse dielectric layer 120 can comprise a thin silicon oxide or other insulating layer. Alternatively, another resistivity switching material described above can be substituted from the antifuse dielectric layer. Another optional adhesion layer 122, such a TiN layer, can be deposited over the antifuse dielectric layer 120. Therefore, the dielectric layer 120 can be sandwiched between two adhesion layers 118, 122.

One or more semiconductor layers 124, such as silicon or germanium or their alloys are formed over the adhesion layer 122. For example, the semiconductor layers 124 can comprise a lower n-type layer, a middle intrinsic layer and an upper p-type layer. The p-type layer can be formed by ion implantation of p-type dopants into the upper part of the intrinsic layer or by deposition of a p-type doped semiconductor layer on the intrinsic layer. An optional upper hard mask stack 126, can be formed over the semiconductor layers 124. The hard mask stack can comprise one or more layers selected from a Bottom Anti-Refection Coating (BARC) layer, a Dielectric Anti-Reflection Coating (DARC) layer (such as a silicon oxynitride layer), an organic hard mask layer, a conductive hard mask layer or layers, or an oxide hard mask layer. The organic hard mask layer can be an amorphous carbon advanced patterning film (APF). For example, the stack 126 can comprise a 10 to 20 nm, such as 15 nm TiN layer, a 25 to 75 nm, such as 50 nm W layer, a 100 to 300 nm, such as 200 nm APF layer, a 30 to 50 nm, such as a 40 nm SiON DARC layer, and a 15 to 40 nm, such as 25 nm BARC layer, from bottom to top. Referring to FIGS. 6 a and 6 b, a first step in the process of creating the pillar devices is shown. FIG. 6 a represents a side cross-sectional view of the device layers and FIG. 6 b represents a top view of the same after the first step. In the first step, a plurality of features 132 is formed over the hard mask stack 126 (or over the semiconductor layer 124 if stack 126 is omitted). The features are spaced apart from each other by spaces 134 (in the horizontal and vertical directions as shown in FIG. 6 b). The features 132 are formed by imaging the imagable material by photo, electron beam or nanoimprint lithography, followed by patterning the imaged material into the features 132. The features 132 can be 75 to 200 nm thick, such as 120 to 150 nm thick photoresist features, such as 193 nm radiation sensitive photoresist. The features 132 can optionally be trimmed after formation to reduce their size. If a BARC layer is present on top of the hard mask stack 126, then it can be patterned together with the features 132 or using features 132 as a mask such that the BARC layer portions are located only under the features 132.

The features 132 are arranged along a plurality of imaginary diagonal lines 136 in a rhombus or rotated square type pattern, as shown in FIG. 6 b. Only four of the plurality of diagonal lines 136 are shown in FIG. 6 b for clarity. As shown in FIG. 6 b, the features 132 have a substantially cylindrical shape (i.e., they have a circular or near circular (such as oval) cross section).

Alignment edge features 137 are provided adjacent to the device array boundary, as shown in FIG. 6 b. The alignment edge features can have a larger size than the plurality of spaced apart features 132 and/or they can have a different shape, such as an oval cross sectional shape. The alignment edge features will be used to simplify alignment in the cut mask step that will be described below.

FIGS. 7 a and 7 b show the next process step. In this step, silicon oxide spacers 138 are formed on each feature 132. It should be noted that if each feature 132 is cylindrical, then it technically has only one sidewall and only one ring or annulus shaped spacer 138 is formed around the sidewall of the feature 132. However, as used herein, the term “spacers” will denote the single annular spacer 138 as well as two or more spacers 138 formed on discrete sidewalls of a polygonal feature 132. The spacers 138 are formed by depositing a silicon oxide layer or film over and between the features 132 followed by anisotropic etching of the silicon oxide layer or film.

The oxide spacers 138 fill the spaces 134 around the features 132 primarily along the plurality of diagonal lines 136, leaving discrete spaces or interstices 140 between adjacent sidewall spacers 138. Due to the annular shape of the sidewall spacers 138, the interstices have a rectangular cross sectional shape with concave sidewalls, as shown in FIG. 7 b.

FIGS. 8 a and 8 b show the next two steps of the process. A filler film can be formed between and over the features 132 and spacers 138. The filler film can comprise an imagable material, for example, a photoresist material, an e-beam resist material, a nanoimprint resist material, or a non-imagable material. The filler film can be deposited by a liquid phase method, such as spin-on or spray coating, to expose the upper surfaces of the spacers 138. The deposition step leaves a plurality of imagable material filler features 142 between the sidewall spacers 138. Since the filler features 142 fill the interstices 140, the filler features 142 also have a rectangular or square cross sectional shape with concave sidewalls (i.e., a substantially rectangular or square shape). At this point in the fabrication of the device array, the spaces 134 are completely filled with either oxide spacers 138 or filler features 142.

If desired, an optional cut masking and etching step can be performed to remove the filler film or filler features 142 from the area outside of the device array. A photoresist layer can be formed over the plurality of filler features 142 and over the plurality of spaced apart features 132. The photoresist layer can be exposed such that the edges of the exposed areas intersect all of the edge features 137. Elongating or enlarging the edge features 137 thus allows for an easier alignment of this cut mask. The remaining filler film or filler features remaining in areas outside of the device array boundary that are not covered by the photoresist pattern are etched away. Alternatively, if the filler film comprises an imagable material, such as a photoresist material, the step of cut masking and etching step made be performed by simply imaging the imagable material (such as for example the exposing the photoresist filler film to radiation) in such a way that the edges of the exposed areas intersect all of the edge features 137. If desired, the cut masking and etching step can be performed after the step of removing the spacers 138.

FIGS. 9 a and 9 b show the next step in the process. In this step, the oxide spacers 138 are selectively etched away leaving the features 132 and filler features 142 spaced apart by spaces 145. The spacers 138 can be selectively etched by any selective wet or dry etch which can selectively etch silicon oxide over the spaced apart features 132 and over the material of filler features 142. For example, an HF isotropic wet etch can be used. The pitch between the features 132 and the filler features 142 has doubled compared to the pitch between the features 132 alone due to the removal of the oxide spacers. If desired, a portion of the hard mask stack 126 can also be etched during the spacer removal. For example, if a DARC layer is present in the stack, then first portions of the DARC layer located under the spacers can also be removed during the spacer removal process to leave second portions of the DARC layer below the imagable material features 132 and the filler features 142.

As shown in FIGS. 10 a and 10 b, at least one of the hard mask stack 126 and/or the device layers 118, 120, 122 and 124 are etched using the features 132 and the filler features 142 as a mask to form a plurality of pillar shaped devices 112.

For example, the features 132 and filler features 142 as well as any BARC layer material remaining under the features 132 and filler features 142 can be removed after patterning the DARC layer of the hard mask stack 126 using the features 132 and filler features 142 as a mask. The DARC layer can be patterned (i.e., etched) during the same step as the spacer 138 removal step. The patterned DARC layer can be trimmed after patterning to reduce the size of the remaining DARC layer patterns and to round the corners of the DARC layer patterns. It should be noted that the BARC and DARC layers can be etched together using the features 132 and the filler features 142 as a mask or the BARC layer can be etched prior to the step of forming the spacers 138, using the features 132 as a mask, while the DARC layer can be etched using the features 132 and the filler features 142 as a mask.

The patterned DARC layer can then be used as a mask to pattern the remaining layers of the hard mask stack 126, such as the APF, tungsten and TiN layers. The DARC layer can optionally be removed during and/or after patterning the remaining hard mask stack 126 layers. The remaining patterned hard mask stack 126 layers are then used as a mask to etch the device layers 118, 120, 122 and 124 to form a plurality of pillar shaped devices 112. For example, each of the devices comprises the p-i-n diode in series with an antifuse dielectric, as described with respect to FIG. 1. The pillar shaped devices 112 have a pitch which can be double that of what the pitch would have been had only the features 132 been used as mask.

The spaces between the pillar devices 112 are filled with a gap fill insulating material, such as silicon oxide, to isolate the devices 112 from each other. The gap fill insulating material can be planarized by CMP or etchback. The upper conductors or electrodes 26 can be formed over the devices 112 by the subtractive or the Damascene processes described above with respect to FIG. 3 or 4. The tungsten and TiN layers of the hard mask stack 126 can be retained in the final device as portions of the upper electrodes 26. The APF layer can be removed after patterning the device layers.

Formation of a first memory level has been described. Additional memory levels can be formed above this first memory level to form a monolithic three dimensional memory array. In some embodiments, conductors can be shared between memory levels; i.e. top conductor would serve as the bottom conductor of the next memory level. In other embodiments, an interlevel dielectric (not shown) can be formed above the first memory level, its surface planarized, and construction of a second memory level begins on this planarized interlevel dielectric, with no shared conductors.

A monolithic three dimensional memory array can be one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates. The layers forming one memory level are deposited or grown directly over the layers of an existing level or levels. In contrast, stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, U.S. Pat. No. 5,915,167, “Three dimensional structure memory.” The substrates can be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.

A monolithic three dimensional memory array formed above a substrate comprises at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or indeed any number of memory levels can be formed above the substrate in such a multilevel array.

Throughout this description, one layer has been described as being “above” or “below” another. It will be understood that these terms describe the position of layers and elements relative to the substrate upon which they are formed, in most embodiments a monocrystalline silicon wafer substrate; one feature can be above another when it is farther from the wafer substrate, and below another when it is closer. Though clearly the wafer, or the die, can be rotated in any direction, the relative orientation of features on the wafer or die will not change. In addition, the drawings are purposefully not shown to scale and are merely representative of layers and processed layers.

The embodiments also relate generally to methods of making semiconductor devices, and more particularly, to methods of making semiconductor pillar structures. Devices made from semiconductor materials are used to create memory circuits in electrical components and systems. Memory circuits are the backbone of such devices as data and instruction sets are stored therein. Maximizing the number of pillar structures per unit area on such circuits minimizes their cost and thus can be a primary motivation in designing of such circuits.

The present embodiments use various methods for increasing the density of memory arrays that can be used with various semiconductor devices. For instance, the feature density of memory arrays can be increased by forming pillars in the spaces between the original pillars where conventional memory arrays just deposit filler materials. By using the spaces between the original pillars, the new pillars can increase the density of the memory arrays and improve the memory circuits used in various semiconductor devices.

The present embodiments also realize that a single hard mask can be made from a single material to construct these memory circuits and semiconductor devices. This can be a much simpler and more efficient process than conventional methods. Conventional methods use a variety of materials, layers, and steps to make such a hard mask. In contrast, the present embodiments can employ a single material to form both the original pillars and fill the spacer regions. The pillars and filled spacer regions can then serve as a single hard mask. Once the hard mask is formed, the spacers can then be easily removed to expose the original pillars and filled spacer regions. The filled spacer regions can then be made into new pillars. The density of the memory array can then increased by having the original pillars combined with the new pillars formed from the filled spacer regions.

Referring now to FIGS. 11A and 11B, a first step in the process of creating the pillar devices is shown. FIG. 11A represents a side cross-sectional view of the device layers and FIG. 11B represents a top view of the same after the first step.

For example, one or more devices can be formed over one or more substrates 150 of the present embodiments. Any suitable substrate material can be used, such as a semiconductor wafer (including silicon or compound semiconductor wafers) or metal, silicon, a dielectric material, glass, ceramic or plastic. The substrates can then be covered by one or more other or additional layers. For instance, the substrate 150 can comprise one or more insulating layers or devices. The device layers can comprise semiconductor layers, semiconductor devices, electrically conductive layers, layers which form electrodes, and/or insulating layers for isolation of the semiconductor or conductive portions of the devices.

At least two spaced apart features 156 can then be formed in a patterned or non-patterned first feature array 154 over the substrate 150. The features can be formed directly or indirectly on or above the semiconductor, conductive and/or insulating or device layers. The features 156 can comprise any shape as long at the features can subsequently function as an etching mask for etching the underlying device layers. For example, as will be described in more detail below, the features 156 can be cylindrical in shape. However, other shapes such as rectangular, triangular, oblong, square, can also be employed with the present embodiments. The features 156 can have any desired size, width, and length. In some embodiments, the features 156 can have the same width as the underlying devices. The features 156 should have sufficient height and width to be capable as serving as a portion or as an entire etching hard mask. In certain other embodiments, the features 156 can comprise similar shapes, size, heights, widths and lengths. In still other embodiments, the features 156 can comprise different shapes, sizes, heights, widths, and lengths.

Referring now to FIGS. 12A and 12B, a second step in the process of creating the pillar devices is shown. FIG. 12A represents a side cross-sectional view of the device layers and FIG. 12B represents a top view of the same after the second step. Sidewall spacers 160 can then be formed on the features 156. Sidewall spacers 160 (see FIGS. 13A and 13B) can be formed by conventional sidewall spacer formation methods, such as by depositing a film or first layer 158 over the features 156 and then anisotropically etching the film to leave sidewall spacers 160 and sidewall spacer regions 164 on the features 156. The sidewall spacers 160 can comprise a conductive, insulating, or semiconductor material different from that of the upper portions of the features 156. In other embodiments the sidewall spacers 160 can comprise silicon, nitride, silicon nitride or other similar type materials that can generally be etched or removed or easily etched or removed relative to carbon materials.

Referring now to FIGS. 13A and 13B, a third step in the process of creating the pillar devices is shown. FIG. 13A represents a side cross-sectional view of the device layers and FIG. 13B represents a top view of the same after the third step. The sidewall spacer 160 material can be selected such that it can be selectively anisotropically etched with dry etch chemistry compared to material of the spaced apart features 156; and such that it can be selectively removed (such as isotropically etched) compared to the material of the spaced apart features 156 using a different dry or wet etch chemistry. For example, when the features comprise an imagable material, such as a photoresist material, the sidewall spacers 160 can comprise silicon oxide, silicon nitride, silicon, or nitride. Other material combinations can also be employed.

The sidewall spacer regions 164 can be in any shape, depth, width or design. In many cases, they will be defined by the sidewall spacers 160 and how they are oriented, shaped, designed, and positioned. These sidewall spacer regions 164 can be exposed to an optional etchant gas in an optional carrier gas. The optional etchant gas can comprise a gas or gas isotope selected from the group consisting of H2, F, Cl, and Br. The optional carrier gas can comprise a gas or gas isotope selected from the group consisting of He, Ar, H2, Kr, Xe, and N2. The optional etchant gas can be employed to prepare the spacer regions 164 for filling using a “selective material”. The etchant gas functions to limit the growth or deposition on the sidewall spacers 160, and fill the spacer regions 164. Other gases with similar functions can be employed with the present embodiments. The “selective material” that fills the spacer regions can then be used to later serve as filler features 190 (described in more detail below and shown in FIGS. 14A and 14B). The “selective material” can be used to directionally fill the spacer regions 164 or “gaps” in any desired direction. Generally, the directional fill can be from the bottom of the spacer region to the top of the spacer region 164. However, this is not required. In certain embodiment the filling of the spacer regions 164 can be described as “gap filling”.

Subsequently, as discussed, the spacer regions 164 located adjacent to sidewall spacers 160 can then be filled with a “selective material”. The “selective material” in some embodiments can comprise a carbon material of the form CxHy, wherein x can be an odd or even number greater than 1, and y can be 2x. In other embodiments, the “selective material” can comprise a material selected from the group consisting of carbon, tungsten, silicon, and their associated isotopes. Amorphous materials or mixtures of materials of carbon, tungsten, silicon, and their associated isotopes can be employed with the present embodiments. Other material or elements having similar properties to the above described materials or elements can also be employed with the present embodiments or teachings. Various processes can be used to construct the feature arrays. Table 1 shows an example of some parameters that can be employed when patterning features arrays with filler features 164 comprising a carbon material.

TABLE 1
Process Parameters for Feature Array
Patterning
PROCESS PARAMETER RANGE
TEMP (C.) 300-650 
Precursor CxHy x = 2-4; y = 2-10 (include all
the single, double and
triple bonded CxHy
species)
Inert carrier Gas/Precursor Ratio He, Ar, H2, Kr, Xe, N2 etc
Etchant Gas/precursor Ratio H2, F-containing gas
Carrier/Precursor Ratio 0.5:1-100:1 
Chamber Pressure (Torr) 1-10
1st RF Power Frequency (Mhz) 10-50 
2nd RF Power Frequency (Khz) 90-500
1st RF Power Density (W/in2) 1.0-30  
2nd RF Power Density to 1st RF  0-0.6
Power Density
Electrode Spacing (Mils) 200-1000

Example 1 Carbon Single Bond and Triple Bond Example

Some examples of the present teaching are provided on Table 1 above. The conditions for carbon to carbon single bonds (C—C) are described. In general the deposition rates for these types of materials are fairly slow. In contrast the carbon to carbon (C≡C) triple bond can be very reactive and fills the gaps and spacer regions very quickly and are more difficult to control.

Example 2 Carbon Double Bond Example

Carbon to carbon double bond (C═C) materials are both effective for growth and depositions and provide desirable material for directionally filling the spacer regions to form filler features. Examples of the conditions for deposition are provided in Table 1 above.

Referring now to FIGS. 14A and 14B, a fourth step in the process of creating the pillar devices is shown. FIG. 14A represents a side cross-sectional view of the device layers and FIG. 14B represents a top view of the same after the first step. The “selective material” can be used to fill the sidewall spacer regions 164 to form a second layer 170. The second layer 170 can be applied as a film over and between sidewall spacers 160 and sidewall spacer regions 164. The “selective material” in some embodiments can comprise the same material as the features 156 or material with similar etch characteristics as features 156. The “selective material” should be different from the material of the sidewall spacers 160 so that the sidewall spacers 160 can be selectively etched and removed later on to form the filler features 190.

Referring now to FIGS. 15A and 15B, a fifth step in the process of creating the pillar devices is shown. FIG. 15A represents a side cross-sectional view of the device layers and FIG. 15B represents a top view of the same after the fifth step. After the filler features 190 are formed, a portion of the second layer 170 covering the side wall spacers 160 can be removed. This can be accomplished using any technique known in the art. For instance, chemical mechanical polishing (CMP) is one technique that can be employed to expose the sidewall spacer top portion 180. Other techniques and methods known in the art can be employed. This technique then exposes the top portion of the features 156, sidewall spacers 160, and filler features 190 for further process steps.

Referring now to FIGS. 16A and 16B, a sixth step in the process of creating the pillar devices is shown. FIG. 16A represents a side cross-sectional view of the device layers and FIG. 16B represents a top view of the same after the sixth step. Next, the sidewall spacers 160 can be selectively removed to form open spacer regions 196 (see FIG. 16B). The step of selectively removing can be accomplished using selective etching. For instance, the material of the sidewall spacers 160 can be selectively etched or removed while the features 156 and filler features 190 act as a single hard mask. The hard mask and/or device layers can be etched using isotropic or anisotropic etching using the spaced apart features 156 and filler features 190 as the mask. Optionally, prior to the step of etching the hard mask and/or device layers, the filler features 190 can be reduced, trimmed, or size adjusted if desired. In certain embodiments when the features 156 and filler features 190 comprise a carbon material, the resulting hard mask can be uniform and produce high quality second feature arrays 200.

Other techniques known in the art are also possible to remove the sidewall spacers 160. The removal of the sidewall spacers 160 leaves the spaced apart features 156 and filler features 190 spaced apart from each other. A pattern or non-pattern second feature array 200 can then be formed that comprises features 156 and filler features 190. The second feature array 200 can comprise an array that has at least 2x the array density of the first feature array 154.

The pattern arrays can be designed in two-dimensional or three-dimensional devices. In other embodiments any suitable devices can be formed. For instance, the devices can have a substantially cylindrical and/or substantially rectangular pillar shape, depending on the shape of the features 156 and filler features 190. Non-pillar shaped devices can also be formed. The devices can comprise diodes, transistors, resistors, antifuse dielectrics, fuses, resistivity-switching materials, capacitors, etc. Logic, volatile memory or nonvolatile memory devices or arrays can also be formed. Further, a plurality of pillar shaped devices which comprise a plurality of diodes containing nonvolatile memory cells can be formed. The details regarding these devices are provide elsewhere (See U.S. Pat. No. 6,952,030, issued to Herner et al., and entitled “High density Three-dimensional Memory Cell,” hereinafter incorporated by reference. This patent describes memory cells which can be formed by the methods of the present embodiments).

Formation of a first memory level has been described. Additional memory levels can be formed above this first memory level to form a monolithic two or three-dimensional memory arrays. In some embodiments, conductors can be shared between memory levels; i.e., top conductor would serve as the bottom conductor of the next memory level. In other embodiments, an interlevel dielectric (not shown) can be formed above the first memory level, its surface planarized, and construction of a second memory level begins on this planarized interlevel dielectric, with no shared conductors.

A monolithic three-dimensional memory array can be one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates. The layers forming one memory level are deposited or grown directly over the layers of an existing level or levels. In contrast, stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, U.S. Pat. No. 5,915,167, “Three-dimensional Structure Memory”. The substrates can be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three-dimensional memory arrays.

A monolithic three-dimensional memory array formed above a substrate comprises at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight or indeed any number of memory levels can be formed above the substrate in such a multilevel array.

Other devices can be formed using the methods of the present teachings. For instance, a semiconductor device can be produced by a method for increasing pattern array density of pillars having sidewall spacers and spacer regions, comprising filling the spacer regions of the array pattern with a selective material, and removing the sidewall spacers of the array pattern pillars to form additional pillars in the spacer regions and increase the density of the pattern array of the semiconductor device.

The embodiments of the teachings have been described in an illustrative manner. It is to be understood that the terminology, which has been used, is intended to be in the nature of words of description rather than of limitation.

Many modifications and variations of the embodiments are possible in light of the above teachings. Therefore, within the scope of the appended claims, the embodiments can be practiced other than as specifically described.

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Classifications
U.S. Classification438/597, 438/587, 438/257, 438/262, 257/E21.038, 438/637, 438/397
International ClassificationH01L21/44
Cooperative ClassificationH01L27/101, H01L27/1021, H01L21/0338, H01L21/3088, H01L21/0337
European ClassificationH01L27/102D, H01L27/10C, H01L21/033F6, H01L21/033F4
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:XU, HUIWEN;CHEN, YUNG-TIN;RADIGAN, STEVEN J.;SIGNING DATES FROM 20100330 TO 20100401;REEL/FRAME:024193/0748