|Publication number||US8116161 B2|
|Application number||US 11/872,675|
|Publication date||Feb 14, 2012|
|Filing date||Oct 15, 2007|
|Priority date||Sep 8, 2005|
|Also published as||US7292490, US20080031069|
|Publication number||11872675, 872675, US 8116161 B2, US 8116161B2, US-B2-8116161, US8116161 B2, US8116161B2|
|Inventors||Lee-Lean Shu, Stephen Lee|
|Original Assignee||Gsi Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Classifications (11), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of application Ser. No. 11/223,194, filed Sep. 8, 2005, now U.S. Pat. No. 7,292,490 which is incorporated herein by reference in its entirety.
The present invention generally relates to semiconductor memory devices, such as dynamic random access memory (“DRAM”) devices. More particularly, the present invention relates to system and method for refreshing a DRAM device without interrupting or inhibiting read or write operations on the DRAM device.
2. Description of Related Information
Semiconductor memory devices are used to store electronic data. One type of semiconductor memory devices is a static random access memory device or an “SRAM” device, An SRAM device typically uses several transistors within each memory cell of the device to store electronic data.
Another type of semiconductor memory device is a dynamic random access memory device or a “DRAM” device. A DRAM device typically includes fewer transistors than an SRAM device, and one or more capacitors within each memory cell of die device to store electronic data. Because DRAM devices use capacitors for storage, DRAM devices require periodic refreshing in order to maintain stored data.
The present invention provides a system and method for refreshing a DRAM device, such as a device including 4T DRAM cells, in a manner that does not interrupt or inhibit read and write operations.
The present invention provides system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. According to one aspect of the present invention, the system includes refresh control circuitry that selectively generates requests to perform refresh operations; a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request, the refresh address corresponding to a word line of the DRAM array to be refreshed; and address control and switching circuitry coupled to the refresh control circuitry. The address control and switching circuitry selectively transmits read/write addresses and refresh addresses to the DRAM array, in order to perform refresh operations on the DRAM array without inhibiting read and write operations.
According to another aspect of the present invention, a method for refreshing a DRAM array is provided. The method includes generating refresh requests; generating a refresh address in response to a refresh request, the refresh address corresponding to a word line of the DRAM array to be refreshed; and selectively transmitting read/write addresses and refresh addresses to the DRAM array, in order to perform refresh operations on the DRAM array without inhibiting read and write operations.
These and other features, advantages, and objects of the invention will become apparent by reference to the following specification and drawings.
The present invention is now described in detail with reference to the drawings, which are provided as illustrative examples of the invention so as to enable those skilled in the art to practice the invention. Notably, the implementation of certain elements of the present invention may be accomplished using software, hardware, firmware or any combination thereof, as would be apparent to those of ordinary skill in the art, and the figures and examples below are not meant to limit the scope of the present invention. Moreover, where certain elements of the present invention can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present invention will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the invention.
System 100 may include word line address generating circuitry 104, address control logic 106, refresh address control circuit 108, refresh address counter 114 and dynamic address switching circuitry 112. Word line address generating circuitry 104, address control logic 106 and refresh address counter 114 are communicatively coupled to dynamic address switching circuitry 112. Refresh control circuit 108 is communicatively coupled to address control logic 106 and refresh address counter 114. Dynamic address switching circuitry 112 is coupled to a predecoder 116 and to a word line decoder 120, which is coupled to DRAM memory array 102. System 100 further includes column address generating circuitry 110, a predecoder 118, and a column decoder 122. Column address generating circuitry 110 is coupled to predecoder 118, which is coupled to column decoder 122. Column decoder 122 is coupled to memory array 102. Word line decoder 120 and column decoder 122 collectively provide address information to memory array 102 in a conventional manner.
The refresh circuitry of the present invention, which may include refresh control circuit 108 and refresh address counter 114, may act as an independent unit to DRAM array 102. In operation, refresh control circuit 108 selectively transmits refresh requests to address control logic 106 request refresh operations and to synchronize with the normal read and write operations of the DRAM array 102. System 100 executes a refresh operation by activating the word line that is decoded from the refresh address generation circuitry 108. All the cells that are connected to the activated word line are refreshed. The address control logic 106 may receive refresh requests from the refresh control circuit 108 and determine when to send a refresh address to memory array 102. The address control logic 106 causes dynamic address switching circuit 112 to selectively transmit the read/write addresses from word line address generating circuitry 104 and refresh addresses from refresh address counter 114.
In one embodiment, the address control logic 106 has three states: normal mode, refresh mode and power-down mode, which are based on the operations status of the DRAM array 102 and status of the refresh pulse. “Normal mode” is when the DRAM array 102 is in either read mode or write mode. When the address control logic 106 is in normal mode, it sends an external address to the word line decoder (e.g., via circuit 112). The column decoder 122 also receives an external address, which is used in conjunction with the word line decoder to select a particular DRAM cell in array 102. “Refresh mode” is when the DRAM array 102 is not in normal mode operation and a refresh pulse, which may be generated by refresh control circuit 108, is active. When the system is in refresh mode, address control logic 106 sends a refresh address from refresh address counter 114 to the word line decoder 120 (e.g., via circuit 112). The corresponding word line is then activated in memory array 102 to refresh all the cells connected to that word line. “Power down mode” is when the DRAM array 102 is in neither normal mode nor refresh mode. All three modes can occur in one cycle time in a synchronous memory device due to dynamic pulse design. But the modes will not occur simultaneously because normal mode takes precedence over refresh mode. Once normal mode operation is completed, the refresh mode can take place if there is refresh pulse present otherwise the address control logic would settle into power-down mode. It is possible for the system to go into normal mode when a refresh operation is still in progress. In this case, refresh mode operation will be terminated immediately and unconditionally.
In order to ensure a proper refresh completion, the width of a refresh pulse may be selected to be longer than the time it takes to complete the normal operation to ensure a proper refresh completion. In one embodiment, the refresh pulse is selected to be equal to or wider than the sum of normal operation time plus twice the time required for a word line refresh or the refresh word line pulse (e.g., refresh pulse≧active enable pulse width+2Śrefresh word line pulse width). One skilled in the art will appreciate that a pulse of this size will guarantee successful refresh under any situations. Once a refresh pulse is completed, the refresh operation is stopped until next refresh request.
The present invention can be applied to synchronous and asynchronous DRAM devices. Furthermore, the present invention can be applied to any type of DRAM cell array that requires refreshing. A DRAM device employing the hidden refresh strategy of the present invention can perform substantially the same as an SRAM device.
Address counter 204 may include one or more conventional counting devices such as a ring counter, shift-registers or the like. The refresh timer oscillator 202 controls the rate of refresh. Particularly, the refresh timer oscillator 202 generates a asynchronous refresh request pulse with which a refresh pulse is generated. The request pulse will cause address counter to count up or down to generate a new refresh address. In one embodiment, the refresh timer may control the rate of refresh by monitoring parameters of the DRAM device, such as cell leakage and temperature to adjust the refresh rate accordingly.
In operation, circuit 200 functions like an SRAM memory device. The control logic 224 determines when an active enable pulse is generated based on a read/write enable signal and a clock signal. In one embodiment, the control logic 224 combines external read or write enable signals with an external clock signal to generate a read or write active enable pulse using combinational logic circuitry and a one shot pulse generator. The control logic and pulse generator cooperate to generate only one active enable pulse per cycle. Control logic 224 will not generate an active enable pulse if there is no valid read or write enable signal. The read or write active enable pulse is used to generate the pulse word line for the read or write operation. The address enable pulse activates transistor 226, which transmits the active read/write address to the word line decoder. When the memory device is not performing a normal read/write operation, the SRAM idle pulse combined with the refresh word line pulse cause a refresh address to be transmitted to the word line decoder. The refresh pulse starts a new refresh cycle. The refresh pulse is then synchronized with normal operation to generate refresh enable pulses. In one embodiment, it is possible to utilize refresh enable pulses to do refresh operations. It is not desirable to turn on the refresh word line for the entire duration of the refresh enable pulse because it has an undesired effect of higher power consumption. In order to save power, refresh enable pulses generate refresh word line pulses through one-shot pulse generator 216. The control logic 224 will decide when the refresh address can be sent to the word line decoder, but it is the refresh word line pulse that determines how much time the word line will be active for a refresh. In one embodiment, the refresh word line pulse width is predetermined with worst-case conditions to ensure successful refresh. That is, the refresh pulse is selected to be equal to or wider than the sum of normal operation time plus twice the refresh word line pulse (e.g., refresh pulse≧active enable pulse width+2Śrefresh word line pulse width).
The exemplary timing diagrams of
In this embodiment, an address enable pulse is generated whenever a new address is detected by address transition detectors 324. The address enable pulse activates transistor 328, which transmits the active read/write address to the word line decoder. When the memory device is not performing a normal read/write operation, the SRAM idle pulse combined with the refresh word line pulse cause a refresh address to be transmitted to the word line decoder.
In operation, circuit 400 sets the refresh flag at the beginning of refresh operation and resets the flag when a refresh operation is completed.
The present invention may be described as a “hidden self-refresh” because it does not require clock or any other external signals to activate or deactivate the refresh of the DRAM device. The present invention refreshes the DRAM device without interrupting or inhibiting the normal operation of DRAM.
It should be understood that the inventions described herein are provided by way of example only and that numerous changes, alterations, modifications, and substitutions may be made without departing from the spirit and scope of the inventions as delineated within the following claims.
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|U.S. Classification||365/222, 365/230.06, 365/233.1, 365/230.02|
|Cooperative Classification||G11C11/40603, G11C11/40611, G11C11/406|
|European Classification||G11C11/406, G11C11/406E, G11C11/406A|