|Publication number||US8122276 B2|
|Application number||US 12/188,481|
|Publication date||Feb 21, 2012|
|Filing date||Aug 8, 2008|
|Priority date||Aug 10, 2007|
|Also published as||US20090044038|
|Publication number||12188481, 188481, US 8122276 B2, US 8122276B2, US-B2-8122276, US8122276 B2, US8122276B2|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (20), Classifications (12), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit under 35 U.S.C. §119(a) of a Korean patent application filed in the Korean Intellectual Property Office on Aug. 10, 2007 and assigned Serial No. 2007-80487, the entire disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to a dynamic clock control apparatus and method in a pipeline system. More particularly, the present invention relates to an apparatus and method for increasing system performance by controlling a clock signal of a pipeline structure.
2. Description of the Related Art
With reference to
To improve performance, most processors or digital blocks use a ‘pipeline structure’ as illustrated in
The synchronous digital system of the pipeline structure illustrated in
As illustrated in
One reason that causes the different processing times in the different stages is that a different function is performed in each stage. One of many techniques for minimizing the difference between processing times will be described below with reference to
In order to effectively apply the time borrowing technique, the estimation of the processing time of each stage must be accurate. This is also true for other techniques used to narrow a time difference between stages. However, since the techniques for reducing a time difference between stages are applied during a chip design, that is, before actual time differences can be measured on the fabricated chip, it is difficult to estimate the processing time accurately. Moreover, as a chip fabrication processes become highly divided, the impact of process tolerances increases rapidly. Also, an increased integration leads to more severe electrical coupling from a neighbor circuit. As a consequence, it is more difficult to determine the physical characteristics of a chip accurately during the chip design. Furthermore, post-fabrication revision regarding performance/power is not supported.
Accordingly, there exists a need for using the processing times of stages based on post-chip fabrication measurements rather than the less accurate estimates calculated during a chip design.
An aspect of the present invention is to address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an aspect of exemplary embodiments of the present invention is to provide a dynamic clock control apparatus and method in a pipeline system.
Another aspect of the present invention is to provide an apparatus and method for improving system performance or decreasing power by controlling the delay of a clock signal in a pipeline digital system.
A further aspect of the present invention is to provide an apparatus and method for enabling a system operation at a constant power supply voltage in a higher clock frequency or enabling a system operation at a lower power supply voltage in a constant clock frequency by delaying or advancing a clock signal input to each pipeline stage in a digital system using a plurality of pipelines.
In accordance with an aspect of the present invention, a pipeline system for dynamically controlling a clock signal is provided. The system includes a clock generator for outputting the clock signal at every predetermined period, a PDR added to each stage for outputting information about a processing speed of the each stage, and a CCU for controlling the delay of the clock signal by using the processing time of each stage received from the PDR and providing the clock signal with the controlled delay to a register between stages.
In accordance with another aspect of the present invention, a method for dynamically controlling a clock signal in a pipeline system is provided. The method includes determining a clock period of the pipeline system, determining a processing time of each stage included in the pipeline system, and controlling the delay of the clock signal input to a register between stages taking into account the processing time of each stage, if there is a stage with a processing time longer than the clock period.
Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the invention.
The above and other aspects, features and advantages of certain exemplary embodiments of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
Throughout the drawings, the same drawing reference numerals will be understood to refer to the same elements, features and structures.
The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. Also, descriptions of well-known functions and constructions are omitted for clarity and conciseness.
Exemplary embodiments of the present invention are intended to provide an apparatus and method for enabling a system operation at a constant power supply voltage in a higher clock frequency or enabling a system operation at a lower power supply voltage in a constant clock frequency by delaying or advancing a clock signal input to a pipeline stage in a digital system using a plurality of pipelines. With reference to
As illustrated in
The PDRs 422, 424, 426 and 428 are devices for outputting information about the processing speed of the combinational logic circuit of each stage. For example, they output information about the fastest path delay which corresponds to the fastest processing speed and the slowest slow path delay which corresponds to the slowest processing speed. The PDRs 422, 424, 426 and 428 will be described below in more detail with reference to
The CCUs 432, 434 and 436 are devices for controlling the delays of a clock signal input to registers between the combinational logic circuits 412, 414, 416 and 418. Each of the CCUs 432, 434 and 436 receives path signals of stages before and after a respective register from the PDRs of the stages and controls the output of a clock signal input to the respective register. The CCUs 432, 434 and 436 will be described below in more detail with reference to
While four stages are shown in
The clock delay controller 610 receives a fastest path delay signal and a slowest path delay signal from the previous stage (#N stage) and determines whether the previous stage is valid with respect to a clock signal. If the previous stage is not valid, the clock delay controller 610 increases the delay of the clock signal. The clock delay controller 610 also receives a fastest path delay signal and a slowest path delay signal from the following stage (#N+1 stage) and determines whether the following stage is valid with respect to the clock signal. If the following stage is not valid, the clock delay controller 610 advances the clock signal, thereby decreasing the delay of the clock signal. A detailed description will be made of the clock delay controller 610 with reference to
The programmable delay logic circuit 620 receives a clock signal (Source Clock) and delays the received clock signal by the adjusted time under the control of the clock delay controller 610. The programmable delay logic circuit 620 outputs the adjusted clock signal (#N+1 Stage Clock Signal) to its respective stage. A detailed description will be made of the programmable delay logic circuit 620 with reference to
The exclusive OR 712 receives the fastest and slowest path delay signals from the previous stage, performs an exclusive OR-operation on them, and provides the resulting exclusive OR value to the D-F/F 714. The exclusive OR value is ‘1’ if the previous stage is valid for a given clock period and ‘0’ if the previous stage is not valid for the given clock period. The D-F/F 714 provides the received information about validity to the delay counter 720, when a clock signal is generated.
The exclusive OR 716 receives the fastest and slowest path delay signals from the following stage, performs an exclusive OR-operation on them, and provides the resulting exclusive OR value to the D-F/F 718. The exclusive OR value is ‘1’ if the following stage is valid for a given clock period and ‘0’ if the following stage is not valid for the given clock period. The D-F/F 718 provides the received information about validity to the delay counter 720, when a clock signal is generated.
The delay counter 720 receives the validity information from the D-F/Fs 716 and 718 and increases a delay count if the previous stage is not valid and decreases the delay count if the following stage is not valid, thereby adjusting the delay of the clock signal input to a register.
A dynamic clock control method in a pipeline system according to an exemplary embodiment of the present invention will be described.
However, if it is determined that there is a stage with a clock timing error in step 904, the synchronous pipeline system adjusts the clock signal of the stage by delaying or advancing the clock signal with the error by a time period in step 906 and returns to step 902. The operation of adjusting the clock signal in step 906 will be explained below in more detail with reference to
If it is determined that the previous stage is valid in step 1002, the CCU determines whether the following stage (N+1th stage) is valid when receiving a clock signal in step 1006. If the following stage is not valid, the CCU decreases or reduces the delay of the clock signal by a time period in step 1008 and returns to step 1000. On the other hand, if the following stage is valid, the CCU maintains the clock signal in a current state in step 1010. Steps 1000 through 1010 are repeated until each CCU does not need to adjust the clock signal in the synchronous pipeline system.
Now an example of clock control in the exemplary 4-stage pipeline system illustrated in
In this case, the result from an exclusive-OR operation on the fastest and slowest path delay signals is a valid detection signal. When Clock2 is generated (positive edge), the valid detection signal is high, indicating always valid. Therefore, the current clock period is maintained because no clock delay is required.
It is noted from
As is apparent from the above description, exemplary embodiments of the present invention provide a dynamic clock control apparatus and method for a pipeline system including a clock generator for outputting a clock signal at every period, PDRs added to respective stages, for outputting information about the processing speed of each stage, and a CCU for controlling the delay of the clock signal received from the clock generator using the processing time of each stage, for input to a register between stages. Because the processing times of the stages are based on actual measurements, the present invention may increase performance and power efficiency.
While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims and their equivalents.
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|U.S. Classification||713/500, 713/322|
|Cooperative Classification||G06F1/08, G06F9/3861, Y02B60/1217, G06F1/3203, G06F9/3869|
|European Classification||G06F1/08, G06F1/32P, G06F9/38P2, G06F9/38H|
|Aug 8, 2008||AS||Assignment|
Owner name: SAMSUNG ELECTRONICS CO. LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, KANG-MIN;REEL/FRAME:021361/0798
Effective date: 20080808
|Aug 11, 2015||FPAY||Fee payment|
Year of fee payment: 4