|Publication number||US8130580 B1|
|Application number||US 12/876,064|
|Publication date||Mar 6, 2012|
|Filing date||Sep 3, 2010|
|Priority date||Sep 3, 2010|
|Also published as||US20120057422|
|Publication number||12876064, 876064, US 8130580 B1, US 8130580B1, US-B1-8130580, US8130580 B1, US8130580B1|
|Inventors||Sridhar Devulapalli, Albert S. Weiner|
|Original Assignee||Atmel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Classifications (8), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This subject matter is generally related to electronics, and more particularly to low power sense amplifiers for reading memory.
Low power devices like Radio Frequency Identification (RFID) tags need low read currents in their embedded non-volatile memory (NVM) to maximize reading distance from an RFID transmitter. One known approach to sensing the state of a NVM cell is to set up read conditions on the memory cell and compare a cell current to a reference current that is generated in a sense amplifier. There are several known circuit designs to produce the reference current. A drawback of these designs, however, is that direct current is consumed by each sense amplifier. The direct current consumption can be in the order of 10s of microamperes to 100s of microamperes per sense amplifier depending on the read speed desired. The direct current consumed is multiplied by the number of sense amplifiers in the circuit. This total current adversely affects the read range of the RFID tag. The direct current can be reduced somewhat by slowing the sense amplifier, but it cannot be reduced beyond a certain point because there is a maximum read time allowed in the system.
A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current.
The low power sense amplifier may include one or more of the following advantages: 1) reducing the average and instantaneous power requirements of the low power sense amplifier to approximately 1 microampere per sense amplifier or less, when operated at 500 KHz; 2) eliminating the need for a reference current; and 3) eliminating the need for direct current (dc) consumed in the low power sense amplifier when reading or not reading memory.
Pre-charge circuit 103 can include transistor 102 (e.g., a p-channel transistor) and optionally current limiting resistor 104. The gate terminal of transistor 102 is coupled to a read sense input (read_sense). The source terminal of transistor 102 is coupled to a reference voltage (vdd), and the drain terminal of transistor 102 is coupled to resistor 104. Alternatively, resistor 104 can be omitted and the drain terminal of transistor 102 can be coupled to the drain terminal of transistor 108 (e.g., p-channel transistor).
Sense capacitor circuit 105 can include sense capacitor 106 and transistor 108. The gate terminal of transistor 108 is coupled to delay path 109. The source terminal of transistor 108 is coupled to a first terminal of sense capacitor 106. A second terminal of sense capacitor 106 can be coupled to ground (gnd). The drain terminal of transistor 108 is coupled to the drain terminal of transistor 102 (or optionally resistor 104) and voltage detection circuit 107. The drain terminals of transistors 102, 108 are coupled to a memory output line (oline), which can be coupled to a memory cell through a y-decoding path (not shown).
Voltage detection circuit 107 can include Schmitt trigger 114 and series inverters 116, 118. The input of the Schmitt trigger 114 is coupled to the memory output line (oline). The output of the Schmitt trigger 114 is coupled to the input of inverter 116. The output of inverter 116 is coupled to the input of inverter 118. The output of inverter 118 is coupled to the gate terminal of transistor 112 (e.g., n-channel transistor).
Delay path 109 can include series inverters 110 a-110 c and transistor 112. The three series inverters can optionally be replaced with an odd number of inverters. The input of inverter 110 a is coupled to the gate terminal of transistor 108 and the gate terminal of transistor 112. The output of inverter 110 c is coupled to the source terminal of transistor 112. The drain terminal of transistor 112 is coupled to output latch 120.
Output latch circuit 120 can include inverter 122, NAND gate 126 and resistor 124. The input of inverter 122 is coupled to the drain of transistor 112 and a first terminal of resistor 124. The output of inverter 122 is coupled to a first input of NAND gate 126 and the input of inverter 128. A second terminal of resistor 124 is coupled to the output of NAND gate 126. A second input of NAND gate 126 is a sense amplifier reset input (sa_resetb). The output of inverter 128 is a data output line (dout). In some implementations, resistor 124 is optional and can be omitted. In such a configuration, the output of NAND gate 126 can be directly coupled to the input of inverter 122.
Having now described an exemplary implementation of low power sense amplifier 100.
When read_sense input is high during a sensing phase (e.g., during time t1-t3), the pre-charge path through transistor 102 is cut off. The memory output line (oline) is at the reference voltage (vdd) and its voltage might dip slightly due to charge sharing. The size of sense capacitor 106 can be selected to be significantly larger than the capacitance on the memory output line (oline) to avoid a large dip in voltage due to charge sharing. The voltage (ncap) stored on sense capacitor 106 starts discharging due to the memory cell current. The slope of the voltage on the memory output line (oline) depends on the memory cell current. Once the voltage on the memory output line (oline) voltage reaches a threshold voltage level of Schmitt trigger 114 (at time t2), the output terminal of Schmitt trigger 114 goes high, causing the output of inverter 116 to go low and the voltage on the gate terminal of transistor 108 to go high. The high voltage on the gate terminal of transistor 108 causes transistor 108 to be turned off due to the connection of the gate terminal of transistor 108 to the output of inverter 118. Sense capacitor 106 is disconnected from the memory output line (oline). At this time the memory output line (oline) may continue to discharge (e.g., discharge to ground) due to the memory cell current, as illustrated in
When the voltage on the gate terminal of transistor 108 is high, the gate terminal of transistor 112 is also high and transistor 112 is open. With transistor 112 open, inverters 110 a-110 c will invert and delay the voltage on the gate terminal of transistor 108. A low voltage on the source terminal of transistor 112 (output of inverter 110 c) overpowers output latch 120 at the output of inverter 122 and pulls the voltage at the input of inverter 122 low. The output of inverter 128 or data output line (dout) will go low as a result (at time t2).
While this document contains many specific implementation details, these should not be construed as limitations on the scope what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub combination or variation of a sub combination.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5696719 *||Aug 23, 1996||Dec 9, 1997||Lg Semicon Co., Ltd.||Sense amplified output control circuit|
|US6836426 *||Feb 26, 2004||Dec 28, 2004||Fujitsu Limited||Semiconductor memory device with proper sensing timing|
|US7333386 *||Feb 11, 2003||Feb 19, 2008||Stmicroelectronics S.A.||Extraction of a binary code based on physical parameters of an integrated circuit through programming resistors|
|US20100039851 *||Oct 21, 2009||Feb 18, 2010||Fujitsu Microelectronics Limited||Semiconductor memory|
|U.S. Classification||365/207, 365/205, 365/189.05, 365/185.25|
|Cooperative Classification||G11C7/065, G11C16/26|
|Sep 21, 2010||AS||Assignment|
Owner name: ATMEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DEVULAPALLI, SRIDHAR;WEINER, ALBERT S.;REEL/FRAME:025024/0660
Effective date: 20100903
|Jan 3, 2014||AS||Assignment|
Owner name: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRAT
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:ATMEL CORPORATION;REEL/FRAME:031912/0173
Effective date: 20131206
|Aug 19, 2015||FPAY||Fee payment|
Year of fee payment: 4
|Apr 7, 2016||AS||Assignment|
Owner name: ATMEL CORPORATION, CALIFORNIA
Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:038376/0001
Effective date: 20160404