|Publication number||US8143512 B2|
|Application number||US 12/383,532|
|Publication date||Mar 27, 2012|
|Priority date||Mar 26, 2008|
|Also published as||CA2718272A1, CN102037152A, EP2274456A1, US20090242029, WO2009120340A1|
|Publication number||12383532, 383532, US 8143512 B2, US 8143512B2, US-B2-8143512, US8143512 B2, US8143512B2|
|Inventors||Puthur D. Paulson, Charlie Hotz, Craig Leidholm, Damoder Reddy|
|Original Assignee||Solexant Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (23), Non-Patent Citations (12), Referenced by (5), Classifications (18), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority to U.S. Provisional Patent Application Ser. No. 61/070,903 filed Mar. 26, 2008 the contents of which is incorporated herein by reference.
Increasing oil prices have heightened the importance of developing cost effective renewable energy. Significant efforts are underway around the world to develop cost effective solar cells to harvest solar energy. In order for solar cells to be cost effective with traditional sources of energy solar cells must be manufactured at a cost well below $1/watt.
Current solar energy technologies can be broadly categorized as crystalline silicon and thin film technologies. Approximately 90% of the solar cells are made from silicon—single crystal silicon or polycrystalline silicon. Crystalline silicon (c-Si) has been used as the light-absorbing semiconductor in most solar cells, even though it is a relatively poor absorber of light and requires a considerable thickness (several hundred microns) of material. Nevertheless, it has proved convenient because it yields stable solar modules with good efficiencies (13-18%, half to two-thirds of the theoretical maximum) and uses process technology developed from the knowledge base of the microelectronics industry. Silicon solar cells are very expensive with manufacturing cost above $3.50/watt.
Second generation solar cell technology is based on thin films. Main thin film technologies are Amorphous Silicon, Copper Indium Gallium Selenide (CIGS), and Cadmium Telluride (CdTe).
Amorphous silicon (a-Si) was viewed as the “only” thin film PV material in the 1980s. But by the end of that decade, and in the early 1990s, it was written off by many observers for its low efficiencies and instability. However, amorphous silicon technology has made good progress toward developing a very sophisticated solution to these problems: multijunction configurations. Now, commercial, multijunction a-Si modules in the 7-9% efficiency range are being produced by several companies. A number of companies such as Kaneka, Sharp, Schott Solar, Ersol, etc., are manufacturing amorphous silicon solar cells on glass substrates by adopting commercially proven CVD process to deposit a-Si originally developed for flat panel display manufacturing. Equipment companies such as Applied Materials are offering turn-key systems to manufacture a-Si solar cells on glass substrates. The key obstacles to a-Si technology are low efficiencies, light-induced efficiency degradation (which requires more complicated cell designs such as multiple junctions), and process costs (fabrication methods are vacuum-based and fairly slow). United Solar has pioneered triple junction a-Si solar cells on flexible stainless steel substrates. However, a-Si solar cells are expensive to manufacture (>$2.5/watt).
Thin film solar cells made from Copper Indium Gallium Diselenide (CIGS) absorbers show promise in achieving high conversion efficiencies of 10-12%. The record high efficiency of CIGS solar cells (19.9% NREL) is by far the highest compared with those achieved by other thin film technologies. These record breaking small area devices have been fabricated using vacuum evaporation techniques which are capital intensive and quite costly. A number of companies (Honda, Showa Shell, Wurth Solar, Nanosolar, Miasole etc.) are developing CIGS solar cells on glass substrates and flexible substrates. However, it is very challenging to fabricate CIGS thin films of uniform composition on large area substrates. This limitation also affects the process yield, which are generally quite low. Because of these limitations, implementation of evaporation techniques has not been successful for large-scale, low-cost commercial production of CIGS solar cells. It is extremely unlikely that CIGS solar cells can be produced below $1/watt manufacturing cost.
CdTe thin film solar cells are very simple to make and have the potential to achieve lowest manufacturing cost compared to all other solar cell technologies. CdTe solar cells with 16.5% efficiency have been demonstrated by NREL. First Solar based in Arizona is producing CdTe solar cells on glass substrates at a manufacturing cost of $1.12/watt. First Solar expects to reduce the cost to below $1/watt by the end of 2009 when it ramps up its annual manufacturing capacity to 1 GW. Further reduction in manufacturing cost of CdTe solar cells is not readily achievable because of relatively slow piece by piece manufacturing process.
CdTe solar cells are made by depositing CdTe on 3 mm thick glass substrates and encapsulated with a second 3 mm cover glass. Hence they are produced by a slow piece by piece manufacturing process. Further reduction in manufacturing cost of CdTe solar cells to well below $1/watt is not readily achievable because of slow piece by piece manufacturing process. These CdTe solar cells are also very heavy and cannot be used for residential rooftop applications—one of the largest market segments of solar industry. Opportunity exists to innovate by developing CdTe solar cell on flexible substrate that can be manufactured by a continuous roll to roll process to significantly reduce manufacturing cost. Flexible solar cells will also be light weight making them suitable for residential roof top applications which are not accessible to CdTe on heavy glass substrates.
Superstrate solar cell configurations are known in the art and have a configuration comprising a substrate which is transparent and faces the sun to generate photovoltaic output. A transparent contact, commonly Indium doped tin oxide (ITO) or Fluorine doped tin oxide (FTO) film is deposited on the substrate followed by CdS window layer. In general the transparent conducting oxide (TCO) is a bilayer consisting of a 200-400 nm thick highly conducting layer with sheet resistance 5-10 Ω/cm3 and a 20-50 nm thick resistive layer with resistance 1-2 Ω-cm. A junction is formed by depositing a CdTe absorber layer using deposition techniques such as close spaced sublimation (CSS), sputtering, electrodeposition, screen printing & sintering or spray pyrolysis. The substrate temperature varies from one deposition technique to other; >600° C. for CSS and ˜100° C. for electrodeposition. CdCl2 treatments, generally at 400° C., are carried out on this device structure to improve the grain size and electronic properties. During the high temperature junction formation or the subsequent CdCl2 treatment significant CdTe—CdS inter-diffusion is observed, which enable the fabrication of high efficiency devices. CdCl2 treatment is followed by the contact treatments to form pseudo-ohmic contact to CdTe. Due to its high work function and it is not possible to dope CdTe>1016 cm3 and also there are no metals available that have a work function higher than CdTe, it is not possible to form ohmic contact to CdTe without the contact treatments. Contact treatments involves either etch treatments such as Br-Methanol or Nitric-Phosphoric acid (NP) or the deposition of interface layers such as Cu2Te, Sb2Te3, Bi2Te3, CuZnTe, HgCdTe that can be doped P+ to form pseudo ohmic or tunneling contacts. Metal electrodes are deposited on surface treated CdTe films using known techniques.
Substrate configuration solar cells are required when opaque substrates such as metal foil substrates are used for high volume production of CdTe/CdS devices. This change in the device configuration necessitates a substantial deviation from the conventional junction formation processing. Prior art substrate CdS/CdTe device performance is inferior to superstrate prior art devices. This is a result of the process advantages associated with the superstrate configuration such as enhanced CdS—CdTe inter-diffusion at higher CdTe processing temperature and the availability of post deposition CdTe surface for ohmic contact processing.
In one embodiment there is disclosed a photovoltaic device having a substrate configuration comprising a transparent or opaque substrate, a metal electrode layer, a TCO layer an absorber layer comprising a Group II-VI semiconductor compound, a window layer, and an interface layer between the absorber layer and the window layer. Preferably the absorber layer comprises CdTe and the window layer comprises CdS. Further, the absorber layer and/or the interface layer comprise a thin film, nanoparticles and/or nanoparticles that are sintered. In one embodiment the absorber layer and/or the interface layer comprises a plurality of grain sizes. In one embodiment the interface layer comprises a Cd rich CdTe1-x where 0<x<1 composition. In another embodiment the interface layer comprises a Tellurium rich Cd1-xTe composition where 0<x<1. In one embodiment a portion of said interface layer located next to the absorber layer comprises large grains sizes, and a portion of said interface layer located next to the window layer comprises small grain sizes. In one embodiment the large grain sizes are about 2.0 μm to about 6.0 μm and the small grain sizes are about 0.1 μm to about 1.0 μm. In another embodiment the large grain sizes are about 2.0 μm to about 3.0 μm, and the large grain sizes are about 0.2 μm to about 0.5 μm. In one embodiment the interface layer comprises a Group II-VI compound. In one embodiment the interface layer comprises at least three layers, where a first layer comprises a Group II-VI compound located next to the window layer, and a third layer comprises a Group II-VI compound located next to the absorber layer, and a second layer comprising a Group II-VIa 1-xVIb x compound, where 0<x<1 and a≠b located between the first and second layers. In one embodiment the interface layer comprises at least one layer comprising CdTe1-xSx where 0<x<1. In another embodiment said interface layer comprises at least three layers, the first layer comprises CdS, a third layer comprises CdTe, and at least one second layer comprising CdTe1-xSx where 0<x<1, said at least one second layer is positioned in between the first and third layers. In one embodiment a buried junction is located between the absorber layer and the window layer. In another embodiment of the present invention the interface layer is created by a surface treatment of the absorber layer where the surface treatment may comprise one or more of wet etching, dry etching, sputtering, reduction, electrochemical, heat treatments and ion milling.
Further disclosed herein is a process for making a photovoltaic device having a substrate configuration, comprising the steps of providing a substrate, forming an electrode, forming an absorber layer comprising a Group II-VI compound, forming a window layer, forming a TCO layer on the window layer, and forming an interface layer between the absorber layer and window layer. In one embodiment the absorber layer is subjected to at least one surface treatment to create the interface layer. In another embodiment the surface treatment is selected from the group consisting of wet etching, dry etching, sputtering, reduction, electrochemical, heat treatments and ion milling. In another embodiment the absorber layer comprises a Group II-VI compound, and the surface treatment creates Group VI vacancies in the absorber layer. The Group II-VI compound may be Cd compound and the Group VI vacancies may be Te. Further disclosed is forming an absorber layer and/or an interface layer comprising a plurality of grain sizes. In one embodiment the absorber layer and/or interface layer is deposited by an evaporation process, and the substrate temperature is varied during the evaporation process. In this embodiment the substrate temperature may be varied from 350° C. to 620° C. In another embodiment a first layer is deposited and sintered at a high temperature, preferably greater than 500° C. and a second layer is deposited and sintered at a low temperature, preferably less than 500° C. In another embodiment the absorber layer comprises a Cd rich CdTe composition and after a window layer comprising CdS is formed, and the device is sintered.
In one embodiment the interface layer comprises a Group II-VII1-xSx compound, where 0<x<1. In another embodiment the interface layer is deposited by an evaporation process wherein the substrate temperature is varied during the evaporation process. The invention also contemplates an interface layer comprising at least two layers where each of the at least two layers are formed by depositing a Group II-VI1-xSx compound, where 0<x<1, but x is different in at least two layers. During deposition the invention also contemplates mixing the deposition source fluxes. Mixing may occur by moving the sources, changing the source temperature, changing the gap and changing the heating element temperature.
Reference will now be made in detail to some specific embodiments of the invention including the best modes contemplated by the inventors for carrying out the invention. Examples of these specific embodiments are illustrated in the accompanying drawings. While the invention is described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural reference unless the context clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood to one of ordinary skill in the art to which this invention belongs.
“Interface layer” as used herein is meant to include a layer or plurality of layers between the absorber layer and the window layer. By definition an “interface layer” includes a single layer as well as a set of multiple layers which may be 1, 2, 3, 4, 5 or more layers. Each layer or layers may independently comprise a thin film, nanoparticles, sintered nanoparticles or a combination of one or more of the three. Also, the invention contemplates that a plurality of interface layers comprising films with the same and/or different grain sizes as well as layers comprising nanoparticles, sintered nanoparticles and or thin films of different chemical compositions.
As used herein the metal electrode is also referred top as a “back contact” or “electrode”.
By “photovoltaic device” as used herein it is meant a multilayered structure comprising the layers necessary where in a working environment with proper leads and connections is capable of converting light into electricity. In one embodiment the device contains at least the following layers in order: a substrate/electrode layer/absorber layer/interface layer/window layer and a TCO layer and this structure is known in the art as a “substrate configuration”. In a substrate configuration the substrate may be transparent or opaque. In a preferred embodiment the substrate comprises a metal and is opaque. The device may have any further structure necessary to practically utilize the device such as leads, connections, etc. The above preferred embodiments of the present invention do not limit the order of layers or deposition order of the photovoltaic device.
The absorber layer used in conjunction with solar cells of the present invention comprises Group II-VI semiconductor compound materials. The window layer used in conjunction with the instant invention preferably comprises n-type material. The window layer may comprise those materials known in the art such as CdS, CdSe, ZnS, ZnSe and oxysulfides.
By “grain size” it is meant grains having an average grain size diameter as measured by viewing a cross section of the layer with an electron micrograph (SEM or TEM). A number of grains, for example 30, are selected because their cross section represents the diameter of the grain and not a partial cross section, and the thicknesses of the selected grains are measured at their thickest point. An average thickness of the selected grains is calculated and this is the average grain size diameter.
By “small grain sizes” it is meant grain sizes having a diameter of between about 0.1 and 1.0 μm.
By “large grain sizes” it is meant grain sizes having a diameter of between about 2-6 μm.
By “plurality of grain sizes” it is meant particles having more than one grain size. In one embodiment the invention contemplates that a there be a population of small grain sizes and a population of large grain sizes.
By “surface treatment” it is meant to include the processes wet etching, dry etching, sputtering, reduction, electrochemical, heat treatments and ion milling. These examples are illustrative only and not exhaustive.
By “buried junction” it is meant a p-n junction located away from (i.e. not directly contacting) the interface of the window and absorber layers. The invention contemplates that a buried junction may extend into the absorber layer or into the interface layer.
By “forming a layer” it is meant those steps for depositing, etching, reacting scribing or otherwise creating or adding to a layer, or acting on a layer already present.
By “forming a buried junction in the absorber layer” it is meant those steps necessary to create a buried junction.
Nanoparticles or sintered nanoparticles useful in the present invention comprise compound semiconductors which include Group I-VI, II-VI, III-V and IV-VI compounds and Group IV semiconductors. This also includes I-III-VI compounds such as CIGS. CIGS is CuInxGa1-xSex where 0≦x<1 and included herein is the family of materials known in the art as CIGS including CIS, CISe, CIGSe, CIGSSe. Spherical nanoparticles used herein have a size between about 1-100 nm, preferably between about 2-20 nm. It is understood that the instant invention contemplates that “nanoparticles” as used herein is not limited to spherical or substantially spherical particles but includes various shaped nanostructures such as tetrapods, bentrod, nanowires, nanorods, particles, hollow particles, single materials, alloyed materials, homogeneous and heterogeneous materials. The size of the nanoparticles is variable but it is preferred that if the particle is an elongate structure, i.e. a nanorod, that the length of the nanorod have a maximum length of about 100 nm and have a maximum diameter of about 1-20 nm, preferably about 5 nm.
Nanoparticles or sintered nanoparticles according to the instant invention may have a core or core/shell or core/shell/shell, or core/shell/shell/shell construction. The core and/or the shell can be a semiconductor material including, but not limited to, those of the Group II-VI (ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, MgTe and the like) and III-V (GaN, GaP, GaAs, GaSb, InN, InP, InAs, InSb, AlAs, AlP, AlSb, AlS, and the like), Group IV-V compounds, and IV (Ge, Si) materials, and an alloy thereof, or a mixture thereof. Type II heterostructures (see S. Kim, B. Fisher, H. J. Eisler, M. Bawendi, Type-II quantum dots: CdTe/CdSe(core/shell) and CdSe/ZnTe(core/shell) heterostructures, J. Am. Chem. Soc. 125 (2003)11466-11467, the contents of which are incorporated herein by reference) and alloyed quantum dots (X. H. Zhong, Y. Y. Feng, W. Knoll, M. Y. Han, Alloyed ZnxCd1-xS nanocrystals with highly narrow luminescence spectral width, J. Am. Chem. Soc. 125 (2003) 13559-13563 and R. E. Bailey, S. M. Nie, Alloyed semiconductor quantum dots: tuning the optical properties without changing the particle size, J. Am. Chem. Soc. 125 (2003) 7100-7106, the contents of both are incorporated herein by reference) are considered suitable. The nanoparticles or sintered nanoparticles may have coatings or ligands attached thereto. Most of the materials listed above are quantum confined. But the invention does not require that the nanoparticles be quantum confined.
The invention contemplates that the nanoparticles used herein may be sintered or unsintered. In one embodiment of the present invention the nanoparticles are sintered or partially sintered during manufacturing and thus and the device comprises “sintered nanoparticles” or “nanoparticles that are sintered”. One of ordinary skill in the art will appreciate that the sintering process will alter the morphology, size and shape of the nanoparticles. Nanoparticle interface layers according to this invention can be thermally processed (in air, inert or reducing atmosphere or vacuum) to improve their electrical properties. Other sintering methods include laser, rapid thermal processing, flash annealing and similar techniques.
In one embodiment of the present invention there is disclosed an increased efficiency solar device obtained by controlling the grain size of the absorber and/or interface layer. The morphology and grain size of the interface and/or absorber layer significantly influences the diffusion of window layer materials into the absorber layer, for example CdS into CdTe. Group II-VI absorber material films possessing very large grains such as 2-6 μm or even a larger distribution of 5-6 μm gains exhibit minimal bulk diffusion of window materials into a Group II-VI absorber layer because the diffusion is predominantly one dimensional. This is undesirable. If the grains at the surface of the absorber layer or in an interface layer are smaller as contemplated in one embodiment of the present invention, for example 0.1 to 1.0 μm, the bulk diffusion is enhanced significantly because the increased grain boundary diffusion of the smaller grains allows a window layer compound, for example CdS to diffuse from all sides of the grains producing three dimensional diffusion. Three dimensional diffusion can also result in a CdTe—CdS buried junction around the grains increasing the junction area resulting in high efficiency devices.
In a preferred embodiment of the present invention an interface layer is located between the absorber layer and the window layer comprising an alloy of a Group II-VI compound and Sulfur. While not wishing to be bound by any particular theory or principle it is believed the interface layer reduces the interface states density resulting from a 10% lattice mismatch between a window layer material such as CdS and a Group II-VI absorber material like CdTe by grading the lattice constants and also allowing the formation of a buried homo-junction in the absorber layer. Inter-diffusion of CdS and CdTe is essential to buffer the close to 10% lattice mismatch between CdS and CdTe by the formation of a CdTe1-xSx alloy layer. This inter-diffusion also results in a buried electrical junction away from the CdS—CdTe metallurgical junction, which reduces the deleterious effects of interface states resulting from lattice mismatch. While not wishing to be bound by any particular theory this is probably because the formation of CdTe1-xSx is less efficient compared to significant amount of grain boundary diffusion and loss of S by sublimation.
A prior art solar device having a substrate device configuration is shown in
An embodiment of the present invention incorporating an interface layer between the absorber layer and the window layer is depicted in
In one embodiment of the present invention the CdTe absorber layer (or an interface layer material) grain size can be controlled by controlling the substrate temperature during the evaporation process. While not wishing to be bound by an exact temperature/grain profile, a 450° C. substrate temperature during close spaced sublimation may result in CdTe films having grains sizes about 0.20 μm to 2.0 μm. A 620° C. substrate temperature during close spaced sublimation of CdTe may result in CdTe films with grain size of about 2.0-6.0 μm. The invention contemplates a temperature range of between 300° C. to 620° C. The invention prefers large grain sizes to be between 2.0-3.0 μm. In another embodiment of the present invention a temperature profile comprising high and low substrate temperatures such as 620° C. followed by 450° C. can be used to create a graded layer of grain sizes with a size reduction towards the CdTe/window layer junction in a continuous deposition process.
In another embodiment of the present invention there is contemplated a two step sintering process employed to create similar grain morphology in either an absorber layer or an interface layer. A dispersion of nano or submicron size Group II-VI compound (preferably CdTe) particles are dispensed and sintered at a high temperature followed by another dispensing of the same Group II-VI dispersion that annealed at a lower temperature. In one non-limiting example the thickness of the grains in the first layer can be between 2-6 μm, preferably 2-3 μm, and the second layer can be 0.05 to 01.05 μm. The grain size distribution of particles in each layer is low and the invention contemplates that most layer will have a closes grain size distribution. The substrate temperature for the first layer can be 550° C. to 600° C. and the second layer can be 450° C. to 500° C.
The invention described herein contemplates three different processes to obtain the interface layer with lattice constants engineered to reduce the interface states. It is understood that these embodiments are illustrative but not exhaustive.
In one embodiment of the present invention a window layer comprising for example CdS with a thickness of about 0.1 to 0.15 μm is deposited on a CdTe film with a Cd rich surface or surface with small CdTe grains (after low temperature CdTe deposition). The films are then annealed at a temperature ranging from 400° C. to 550° C. for a 10 to 30 min duration. This temperature treatment can also be carried out in the presence of CdCl2 vapor from either a vapor source or CdCl2 applied directly on CdS surface using a saturated solution of CdCl2 in methanol. The effect of CdCl2 and temperature on CdS diffusion during device processing is known see “Study of in-situ CdCl 2 treatments on CSS deposited CdTe films and CdS/CdTe solar cells” P. D. Paulson and V. Dutta, Thin Solid films, 370, 2000, pp 299-306 the contents of which are incorporated herein by reference.
In another embodiment of the present invention an interface layer is created by depositing a Group II-VI absorber layer followed by the deposition of a Group II-VIa 1-xVIb x compound, a≠b, alloy with x varying from 0 to 1 forming a gradient of pure CdTe near the absorber layer and pure CdS near the window layer. This is particularly suitable for a continuous roll to roll fabrication of the device structure without a vacuum break. Thermal sources can be arranged in such a way that the flux changes from pure CdTe through CdTe deposition followed by interface layer where x varies from 0 to 1 followed by the deposition of pure CdS flux for the CdS film deposition. During this deposition, the substrate temperature is changed from 550° C.-650° C. for CdTe deposition to 250° C.-350° C. during interface layer deposition and finally to 200° C. to 300° C. for CdS deposition. Depending on the material, temperatures higher than 400° C. during or after the interface layer deposition could result in a segregation of secondary phases in the interface layer because of the miscibility gap in the CdS—CdTe phase diagram. The solubility of Sulfur in CdTe is only 5.8% see “Thin Film Cadmium Telluride—Cadmium Sulfide alloys and devices” D. G. Jensen, B. E. McCandless and R. W Birkmire, 25th IEEE Photovoltaic Specialist Conference, 1996, pp 773-776 the contents of which are incorporated herein by reference. Because of this reason the interface layer approach described in this invention is not suitable for a superstrate configuration, where the CdTe deposition temperature exceeds 450° C. temperature.
A low temperature deposition of a Group II-VIa 1-xVIb x compound, a≠b, where 0<x<1, for example CdTe1-xSx where 0<x<1, followed by the heat treatment at temperature >400° C. prior to CdS deposition can also be used to precipitate the CdS to the CdTe1-xSx grain boundary and forming three dimensional junction of CdTe94.6S5.8/CdS.
In a third embodiment multiple thin films comprising various stoichiometric amounts of a Group II-VIa 1-xVIb x compound, a≠b where 0<x<1, for example, CdTe1-xSx with x varying from 0 to 1 is dispensed using a dispersion of CdTe1-xSx nano or sub micron particle on surface treated CdTe film. The film stack is then heat treated at temperature 250° C. to 450° C. in an inert ambient. This temperature treatment can also be carried out in the presence of CdCl2 vapor from either a vapor source or CdCl2 applied directly on CdS surface using a saturated solution of CdCl2 in methanol.
In a preferred embodiment the interface layer comprises a stoichiometric gradient of CdTe1-xSx composition where 0≦x≦1 between CdTe and CdS.
In another alternative embodiment of the present invention there is contemplated various stoichiometric amounts of Group II-VIa 1-xVIb x compound where a≠b and 0<x<1, for example, CdTe1-xSex is dispensed using a dispersion of CdTe1-xSex nano or sub micron particle on a surface treated CdTe film. The film stack is then heat treated at temperature 250° C. to 450° C. in an inert ambient. This temperature treatment can also be carried out in the presence of CdCl2 vapor from either a vapor source or CdCl2 applied directly on CdS surface using a saturated solution of CdCl2 in methanol.
It is preferred that the CdTe surface undergo treatments prior to deposition of the CdS window layer as well as thermal treatment after the deposition of the CdS window layer. In one embodiment the treatment removes native oxides such as CdTeO3, or CdO from the CdTe surface. This treatment is particularly significant for a batch production process that involves a vacuum bake or exposure of the CdTe surface to an oxidizing gas ambient in the production process resulting in the formation of oxides. Wet as well as dry processes can be used for this process. A short wet etch in Br-methanol solution can be used to remove the surface oxides, see “The dynamics of Cadmium Telluride Etching” K. D. Dobson, P. D. Paulson, B. E. McCandless and R. W. Birkmire, Mat. Res. Soc. Symp. Proc. Vol. 763, 2003, pp B3.1.1-12 the contents of which are incorporated herein by reference. Sputtering, reduction in hydrogen plasma or heat treatments in Hydrogen or forming gas is particularly suitable for the dry process. Sputter process parameters such as process pressure, sputter power are tweaked to reduce the sputter damage on the CdTe surface. Previously sputter cleaning has been employed to clean the CdTe surface prior to contacting with metal electrode see “RF sputtering as a surface cleaning process for CdTe solar cells” V. Viswanathan, D. L. Morel and C. S. Ferekides, 31st IEEE Photovoltaic Specialist conference, 2005, pp 426-429 the contents of which are incorporated herein by reference. High process pressure such as 150 to 400 mTorr and low sputter power such as 30-100 watts inch is particularly suitable for the removal of oxides.
Another embodiment of the present invention envisions a surface treatment to remove the accumulation of deleterious trace elements on the absorber layer surface that diffused from the metal substrate as a result of the high temperature CdTe deposition. For example, Cu from a Cu doped ZnTe interface layer between the metal back contact and the absorber layer can diffuse through CdTe grain boundaries during CdTe deposition and create acceptor states in window layer and thereby compensate the n-type dopants. Previous studies show that Cu concentration higher than 1020/cm3 in CdS would severely affect the device results, see “Introduction of Cu in CdS and its effect on CdTe/CdS solar cells” K. Barri, M. Jayabal, H. Zhao, S. Asher, J. W. Pankow, M. R. Young and C. S. Ferekides, 31st IEEE Photovoltaic Specialist conference, 2005, pp 287-290, the contents of which are incorporated herein by reference. As a remedy preferential sputtering provides means to selectively sputter clean the trace elements. For example, Cu has higher sputter yield with respect to CdTe and hence traces of these elements can be preferentially sputtered. Selection of sputter power and the process pressure is very crucial for the selectively sputtering the trace elements without damaging the CdTe surface. For example a high sputter power density such as 100 to 200 watts/inch2 and low process pressure such as 1-2 mTorr would result in sputter damages on CdTe surface which results in heavily compensated surface regions with very low acceptor density. A preferred sputter clean process employs a low sputter power (1-2 watts/square inch) to reduce the sputter damage and higher process pressure (15-20 mTorr) to increase the scattering and thereby reduce the sputter damage and also increase the sputtering from grain boundaries. Adding forming gas in to the sputter gas aids in removing both oxides as well as the metal traces. Assuming that all the Cu traces has been diffused to the CdTe surface during and later removed by the sputter cleaning process, a high temperature annealing process can be used to anneal out all the sputter damage prior to the CdS deposition.
Another embodiment of the present invention contemplates a treatment to create Group VI vacancies in the absorber layer, for example Te vacancies in a CdTe absorber layer. This advantageously enhances sulfur diffusion to CdTe lattice. The surface treatment described here creates a Te depleted CdTe surface to enhance the formation of CdTe1-xSx alloy formation during subsequent CdS deposition. The invention contemplates that a wet as well as a dry process can be employed to create a Cd rich surface. For example selective electro chemical dissolution of Te by using suitable electropotential can be employed to create a Cd rich surface. This is possible because the standard electrode potential of Te (+0.55V) is more positive compared to Cd (−0.4V). Dry process has its own advantages and hence Ion milling which has been employed in the past on superstrate configuration device prior to contact application becomes an ideal candidate. Ion milling results shows that the resulting CdTe surface composition depends on the ion milling time and it has been employed to create Te rich surface see “Studies of ZnTe back contacts to CdS/CdTe solar cells” T. A. Gessert, P. Sheldon, X. Li, D. Dunlavy, D. Niles, 26th IEEE Photovoltaic Specialist conference, 1997, pp 419-422, the contents of which are incorporated herein by reference. In another embodiment of the present invention there is contemplated an interface layer comprising a Te rich CdTe composition that may be used advantageously to block Cu migration.
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|U.S. Classification||136/252, 136/260, 136/264|
|Cooperative Classification||Y02P70/521, C23C14/0629, C23C14/562, H01L31/073, Y02E10/543, C23C14/24, C23C14/54, H01L31/1836|
|European Classification||H01L31/18D3, C23C14/54, C23C14/06D2, H01L31/073, C23C14/24, C23C14/56B|
|Mar 24, 2009||AS||Assignment|
Owner name: SOLEXANT CORP., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PAULSON, PUTHER D.;HOTZ, CHARLIE;LEIDHOLM, CRAIG;AND OTHERS;REEL/FRAME:022495/0956
Effective date: 20090318
|Mar 18, 2014||AS||Assignment|
Owner name: SIVA POWER, INC., CALIFORNIA
Free format text: CHANGE OF NAME;ASSIGNOR:SOLEXANT CORP.;REEL/FRAME:032463/0703
Effective date: 20140207
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