|Publication number||US8149950 B2|
|Application number||US 11/961,969|
|Publication date||Apr 3, 2012|
|Filing date||Dec 20, 2007|
|Priority date||Dec 26, 2006|
|Also published as||CN102017553A, CN102017553B, CN104202279A, EP2106648A2, EP2106648A4, US8509347, US8737300, US8855234, US9137078, US9148324, US9246731, US9419837, US20080152037, US20120039254, US20120147993, US20130272202, US20130315291, US20140313884, US20150092830, US20160014782, US20160269210, US20170055198, WO2008078195A2, WO2008078195A3|
|Publication number||11961969, 961969, US 8149950 B2, US 8149950B2, US-B2-8149950, US8149950 B2, US8149950B2|
|Inventors||Wan Jong Kim, Kyoung Joon Cho, Jong Heon Kim, Shawn Patrick Stapleton|
|Original Assignee||Dali Systems Co. Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (88), Referenced by (22), Classifications (28), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/877,035, filed Dec. 26, 2006, and having the same inventors as the present case, and also claims the benefit of U.S. Provisional Application Ser. No. 61/012,416, filed Dec. 7, 2007, both of which are incorporated herein by reference.
The present invention generally relates to wideband communication systems using multiplexing modulation techniques. More specifically, the present invention relates to methods and systems for baseband predistortion linearization to compensate for nonlinearities and memory effects of multi-channel wideband wireless transmitters.
The linearity and efficiency of radio frequency (RF) power amplifiers (PAs) have been a critical design issue for non-constant envelope digital modulation schemes which have high peak-to-average-power ratios (PARs) as the importance of spectral efficiency in wireless communication systems increases. RF Pas have nonlinearities that generate amplitude modulation-amplitude modulation (AM-AM) and amplitude modulation-phase modulation (AM-PM) distortion at the output of the PA. These effects create spectral regrowth in the adjacent channels and in-band distortion which degrades the error vector magnitude (EVM).
The relationship between linearity and efficiency is a tradeoff since power efficiency is very low when the amplifier operates in its linear region and increases as the amplifier is driven into its compression region. In order to enhance linearity and efficiency at the same time, linearization techniques are typically applied to the RF PAs. Various linearization techniques have been proposed such as feedback, feedforward and predistortion.
One technique is baseband digital predistortion (PD) which typically uses a digital signal processor. Digital predistortion can achieve improved linearity and improved power efficiency with reduced system complexity when compared to the widely used conventional feedforward linearization technique. A software implementation provides the digital predistorter with re-configurability suitable for multi-standards environments. In addition, a PA using an efficiency enhancement technique such as a Doherty power amplifier (DPA) is able to achieve higher efficiencies than traditional PA designs at the expense of linearity. Therefore, combining digital predistortion with a PA using an efficiency enhancement technique has the potential to improve system linearity and overall efficiency.
However, most digital PDs presuppose that PAs have no memory or a weak memory. This is impractical in wideband applications where memory effects cause the output signal to be a function of current as well as past input signals. The sources of memory effects in PAs include self-heating of the active device (also referred to as long time constant or thermal memory effects) and frequency dependencies of the active device, related to the matching network or bias circuits (also referred to as short time constant or electrical memory effects). As signal bandwidth increases, memory effects of PAs become significant and limit the performance of memoryless digital PDs.
Various approaches have been suggested for overcoming memory effects in digital PDs. For the short-term memory effects, a Volterra filter structure was applied to compensate memory effects using an indirect learning algorithm, but the number of optimization coefficients is very large as the order increases. This complexity makes the Volterra filter based PD extremely difficult to implement in real hardware. A memory polynomial structure, which is a simplified version of the Volterra filter, has been proposed in order to reduce the number of coefficients, but even this simplified version still requires a large computational load. In addition, such a memory polynomial based PD suffers from a numerical instability when higher order polynomial terms are included because a matrix inversion is required for estimating the polynomial coefficients. An alternative, yet equally complex structure based on orthogonal polynomials has been utilized to alleviate the numerical instability associated with the traditional polynomials. To further reduce the complexity at the expense of the performance, the Hammerstein predistorter, which is a finite impulse response (FIR) filter or a linear time invariant (LTI) system followed by a memoryless polynomial PD, has been proposed. The Hammerstein predistorter assumed that the PA models used follow a Wiener model structure which is a memoryless nonlinearity followed by a finite impulse response (FIR) filter or a linear time invariant (LTI) system.
This implementation means that the Hammerstein structure can only compensate for memory effects coming from the RF frequency response. Therefore, if the RF frequency response is quite flat, the Hammerstein PD cannot correct for any other types of memory effects, such as bias-induced and thermal memory effects.
Most recently, a static lookup table (LUT) digital baseband PD cascaded with a sub-band filtering block has been used in order not to compensate for electrical memory effects, but to combat gain and phase variation due to temperature changes of the PA after an initial setting for the fixed LUT PD.
Hence, there has been a long-felt need for a baseband predistortion linearization method able to compensate for not only RF frequency response memory effects but also bias-induced or thermal memory effects in multi-channel wideband wireless transmitters.
Accordingly, the present invention substantially overcomes many of the foregoing limitations of the prior art, and provides a system and method of baseband predistortion linearization that compensates for nonlinearities as well as memory effects found in multi-channel wideband wireless transmitters. This result is achieved through the use of piecewise pre-equalized PD utilizing a lookup table. With this approach, the present invention is able to compensate for electrical and thermal memory effects while at the same time reducing the computational complexity and the numerical instability of the system as compared with prior art systems using a memory polynomial PD algorithm, while the present invention is comparable to a memory polynomial PD in terms of the resulting linearity in the performance of a multi-band PA.
Further objects and advantages of the invention can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings in which:
To overcome the computational complexity and numerical instability of the memory polynomial PD found in the prior art, The present invention, therefore, utilizes an adaptive LUT-based digital predistortion system with a LUT that has been pre-equalized to compensate for memory effects, so as to achieve less computational load than the prior art while also reducing the adjacent channel power ratio (ACPR) to substantially the same degree as the memory polynomial PD has achieved. The system provided by the present invention is therefore referred as a piecewise pre-equalized, lookup table based predistortion (PELPD) system hereafter.
Preferred and alternative embodiments of the PELPD system according to the present invention will now be described in detail with reference to the accompanying drawings.
where u(n) is the input signal 101 and the round function returns the nearest integer number which is the index (m) and N is the LUT 106 size.
The digital complex baseband input signal samples 101 are multiplied prior to pre-equalization 107 by complex coefficients 102 drawn from LUT entries as follows
where Fm(|u(n)|) is the complex coefficient 102 corresponding to an input signal 101 magnitude for compensating AM to AM and AM to PM distortions of the PA 110.
N by K−1 filter coefficients in the LUT of the piecewise pre-equalizer 107 are used to compensate for memory effects, where N is the depth of the LUT and the FIR filter has K taps. In some embodiments, the piecewise pre-equalizers 107 use a FIR filter rather than an infinite impulse response (IIR) filter because of stability issues, although a FIR filter is not necessarily required for all embodiments. The output 104 of the pre-equalizers can be described by
where Wk m(|u(n)|) is the k-th tap and m-th indexed coefficient corresponding to the magnitude of the input signal, u(n) 101. Also, Wk m(|u(n)|) is a function of |u(n)| and Fm 102 is a function of |u(n−k)|. For analysis purposes, the memoryless LUT 106 (Fm) structure can be replaced by a polynomial model as follows:
where 2p−1 is the polynomial order and b is a complex coefficient corresponding to the polynomial order. Moreover, it is noted that the tap coefficients and memoryless LUT coefficients (Fm) 102 depend on u(n) and u(n−k), respectively.
Therefore, each piece of the equalizer can be expressed using a polynomial equation by
where Wk m(|u(n)|) is the k-th tap coefficient with the m-th index being a function of |u(n)|. Without loss of generality, the piecewise pre-equalizers 107 can be defined similarly using a l-th order polynomial,
where wk,l is the k-th tap and l-th order coefficient.
After digital-to-analog converting 108 of z(n) 104, this signal is up-converted 109 to RF, amplified by the PA 110 generating distortions, attenuated 113, down-converted 114 to baseband, and then finally analog-to-digital converted 115 and applied to the delay 116 estimation algorithm 117. The feedback signal, that is, the output of the PA 110 with delay, y(n−Δ) 105 can be described by
where G(·) and Φ(·) is AM/AM and AM/PM distortions of the PA 110, respectively and Δ is the feedback loop delay. For estimating Δ, a correlation technique was applied as follows:
where d is the delay variable and N is the block size to correlate.
After delay 116 estimation, the memoryless LUT 106 coefficients can be estimated by the following equation which is the least mean square (LMS) algorithm with indirect learning.
F m(|u(n+1)|)=F m(|u(n)|)+μ·u(n)·e(n)
where n is the iteration number, μ is the stability factor and e(n) is x(n)−y(n)·Fm(|x(n)|).
It should be pointed out that addressing already generated can be reused for indexing y(n) 105 which is a distorted signal able to cause another error due to incorrect indexing. During this procedure, the samples, x(n) 103, should bypass by the piecewise pre-equalizers 107. After convergence of this indirect learning LMS algorithm, the equalizers 107 are activated. An indirect learning method with an LMS algorithm has also been utilized for adaptation of the piecewise filter coefficients. The input of the multiple equalizers 107 in the feedback path is written in vector format as
y FI(n)=[y F(n)y F(n−1) . . . y F(n−K+1)]
where yF(n) is the post LUT output, that is, y(n)·Fm(|y(n)|).
Therefore, the multiple FIR filter outputs, yFO(n), can be derived in vector format using the following equations.
y FO(n)=W m ·y FI(n)T
W m =[W 0 m W 1 m . . . W K-1 m]
where T is a transpose operator.
Adaptation of the tap coefficients of the pre-equalizers 107 can be obtained as follows:
W m(|u(n+1)|)=W m(|u(n)|)+μ·(y FI(n)T)*·E(n)
where E(n) is the error signal between z(n) and yFO(n), and μ is the step size (* represents the complex conjugate). The adaptation algorithm determines the values of the coefficients by comparing the feedback signal and a delayed version of the input signal.
Referring to the feedback path beginning at output 111, it will be appreciated that several alternatives exist for using such feedback to update the LUT values or polynomial coefficients. In some embodiments, the output of the PA is converted to baseband, and the resulting baseband signal is compared to the input signal. The resulting error is used to correct the LUT values and coefficients. In other embodiments, the output from the PA is spectrally monitored and the out of band distortion is monitored using a downconverter, bandpass filter and power detector. The power detector value is then used to adjust the LUT values or polynomial coefficients.
In order to examine the performance of the PELPD of the present invention, the behavioral modeling of a PA based on time domain measurement samples was first carried out. The behavioral model was based on the truncated Volterra model. A 300 W peak envelope power (PEP) Doherty PA using two 170 W push-pull type laterally diffused metal oxide semiconductors (LDMOS) at the final stage was designed. This Doherty PA operates at 2140 MHz band and has 61 dB of gain and 28% power added efficiency (PAE) at an average 30 W output power. To construct the PA model based on measurements of the actual PA, the test bench was utilized [K. Mekechuk, W. Kim, S. Stapleton, and J. Kim, “Linearinzing Power Amplifiers Using Digital Predistortion, EDA Tools and Test Hardware,” High Frequency Electronics, pp. 18-27, April 2004]. Based on the behavioral model, various types of PDs including a memoryless LUT PD, a Hammerstein PD, the PELPD of the present invention and a memory polynomial PD have been simulated and the adjacent channel power ratio (ACPR) performances are compared. The LUT size was fixed to 128 entries through all simulations, which is a compromise size considering quantization effects and memory size. Those skilled in the art will recognize that the amount of compensation for nonlinearities is related to the size of the LUT 106. Increases in LUT size, while yielding a more accurate representation of the nonlinearities, comes at the cost of more effort in the adaptation. Thus, selection of LUT size is a trade-off between accuracy and complexity.
As a test signal, a single downlink W-CDMA carrier with 64 dedicated physical channels (DPCH) of Test Mode based on 3rd Generation Partnership Project (3GPP) standard specifications, which has 3.84 Mchips/s and 9.8 dB of a crest factor. First, an eight tone signal with 500 kHz spacing which has 9.03 dB of PAR and 4 MHz bandwidth, which is comparable to a W-CDMA signal, was used for verifying the proposed method.
After verifying the ACPR performance of the PELPD of the present invention in the simulations based on the behavioral PA model, an experiment was performed using the actual Doherty PA in the test bench. The transmitter prototype consists of an ESG which has two digital to analog converters (DACs) and a RF up-converter, along with the PA. The receiver comprises an RF down-converter, a high speed analog to digital converter, and a digital down-converter. This receiver prototype can be constructed by a VSA. For a host DSP, a PC was used for delay compensation and the predistortion algorithm. As a test signal, two downlink W-CDMA carriers with 64 DPCH of Test Model 1 which has 3.84 Mchips/s and 9.8 dB of a crest factor was used as the input signal in the measurements in order to verify the compensation performance of the different PDs. All coefficients of PDs are identified by an indirect learning algorithm which is considered to be inverse modeling of the PA. During the verification process, a 256-entry LUT, 5 taps FIR filter for Hammerstein PD, the PELPD of the present invention (with 2 taps), and a 5th order-2 delay memory polynomial were used. The choice of the number of taps was optimized from several measurements.
The complexity of the PELPD method of the present invention and the memory polynomial method is also evaluated (neglecting LUT readings, writings, indexing, and calculation of the square root (SQRT) of the signal magnitude, because LUT indexing depends not only on the methods, but also on the variable, for example, magnitude, logarithm, power, and so on and the SQRT operation can be implemented in different ways). Therefore, the complexity is only estimated by counting the number of additions (subtractions) and multiplications per input sample. In order to consider a real hardware implementation, complex operations are converted into real operations and memory size is also considered. For example, one complex multiplication requires two real additions and four real multiplications. If N is the number of LUT entries, memory size required is 2N (I&Q LUTs).
In summary, the PELPD of the present invention, compared to the conventional Hammerstein approach, could reduce spectral regrowth more effectively and achieve a similar correction capability with the memory polynomial PD, but requires much less complexity.
Although the present invention has been described with reference to the preferred and alternative embodiments, it will be understood that the invention is not limited to the details described thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.
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|U.S. Classification||375/296, 375/233, 375/234, 379/340, 375/229, 379/398, 341/151|
|Cooperative Classification||H04B2001/0425, H04W72/0453, H04L27/2618, H04W24/04, H04L2025/03414, H04B1/0475, H04W40/00, H04W24/02, H03F3/24, H03F2201/3224, H04L25/03343, H03F2200/336, H04L27/362, H03F2200/57, H03F2201/3233, H03F1/3247|
|European Classification||H03F1/32P2, H03F3/24, H04L25/03B9, H04L27/36B|
|Feb 27, 2008||AS||Assignment|
Owner name: DALI SYSTEMS CO. LTD., CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, WAN JONG;KIM, JONG HEON;CHO, KYOUNG JOON;AND OTHERS;REEL/FRAME:020570/0944
Effective date: 20080124
|Sep 16, 2015||FPAY||Fee payment|
Year of fee payment: 4
|Sep 6, 2016||AS||Assignment|
Owner name: DALI WIRELESS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DALI SYSTEMS CO. LTD.;REEL/FRAME:039645/0347
Effective date: 20160906