|Publication number||US8154268 B2|
|Application number||US 12/324,368|
|Publication date||Apr 10, 2012|
|Filing date||Nov 26, 2008|
|Priority date||Dec 3, 2007|
|Also published as||EP2218163A1, US8344717, US20090140711, US20120126773, WO2009073573A1, WO2009073573A8|
|Publication number||12324368, 324368, US 8154268 B2, US 8154268B2, US-B2-8154268, US8154268 B2, US8154268B2|
|Inventors||Rhys S. A. Philbrick, Matthew B. Harris, Steven P. Laur|
|Original Assignee||Intersil Americas Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Referenced by (3), Classifications (9), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit of U.S. Provisional Application Ser. No. 60/991,847, filed on Dec. 3, 2007 and Ser. No. 61/021,178, filed on Jan. 15, 2008, which are herein incorporated by reference in their entireties for all intents and purposes.
The benefits, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings in which:
The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Many switching regulator or DC/DC converter configurations employ a feedback control loop for purposes of controlling at least one operating parameter of the regulator, such as output voltage, output current, maximum input or output current, etc. Current-mode regulator technologies are employed for their ease of implementation and their access to and control of the current signal. They often require a high-gain operational error amplifier to reduce output impedance necessitating a complex compensation network to stabilize the feedback loop and return performance to the system. This adds cost, difficulty, and size and can compromise performance. As further described herein, if the current signal is high-pass filtered, and if the system is referenced in a balanced manner, then the high-gain error amplifier may be replaced with a low-gain amplifier in which the regulator still maintains a low output impedance and accurate DC regulation performance. Replacing the high gain error amplifier with a low gain amplifier makes the regulator stable without any compensation. This makes the regulator cheaper, faster and less complex. The present invention is described in relation to current mode regulators, where it is understood that the present invention may be applied to other types of regulators.
One particular regulator is referred to as a synthetic ripple regulator which generates an artificial or synthesized ripple waveform that controls the switching operation of the regulator. The synthetic ripple regulator, however, typically uses a high gain amplifier in the control loop to compensate for DC voltage in the error signal. The high gain amplifier requires, in turn, a compensation circuit to avoid unwanted oscillations and to maintain control. The high gain amplifier and corresponding compensation circuit consumes valuable die space on the controller chip. Further, the compensation circuit causes phase delay and reduces transient response. Similar problems exist for other current mode controlled regulators and DC/DC converters.
The switch circuit 105, the output inductor L, the output capacitor CO, and an external resistor-capacitor (RC) compensation circuit 118 (among other supporting components) are generally external components relative to a regulator control integrated circuit (IC) 102. The phase node developing the phase voltage VPHASE is available to the regulator control IC 102 whereas the input voltage VIN is not (to avoid an additional pin on the regulator control IC 102). In the illustrated embodiment, the regulator control IC 102 includes a sample and hold (S&H) circuit 103 which samples the VPHASE voltage when the upper switch is turned on to effectively sample VIN. The output of the S&H circuit 103 provides a sampled version of VIN, shown as SVIN, which is provided to the positive voltage input of a transconductance (gm) amplifier 104 and to one input of a frequency control circuit 106. The negative voltage input of the transconductance amplifier 104 is coupled to ground. The transconductance amplifier 104 has a pair of outputs coupled between a supply voltage VDD and a first switched terminal of a switch SW1. The other switched terminal of the switch SW1 is coupled to a node 110. The transconductance amplifier 104 provides an output current proportional to the input voltage VIN to node 110 when the switch SW1 is closed. The switch SW1 receives the PWM signal at its control input and the switch SW1 is closed when the PWM signal is asserted to the first level (e.g., when the upper switch of the switch circuit 105 is on) and otherwise opened.
The output voltage VO is provided to the positive voltage input of another transconductance amplifier 108 having its negative voltage input coupled to ground. The current output terminals of the transconductance amplifier 108 are coupled between node 110 and ground. A ripple capacitor CR is coupled between node 110 and ground and a ripple resistor RR is coupled between node 110 and a node 112. A DC voltage source 113 provides a regulated constant voltage level REG to node 112. In one embodiment, CR has a capacitance of approximately 30 picofarads (pf). In one embodiment, REG is a constant voltage regulated at approximately 1.1 Volts (V). The resistance of the resistor RR may be within a suitable range but is generally a relative high value, such as 800 kilohms (kΩ) or the like as shown. The transconductance amplifier 108 draws a current based on the output voltage VO from node 110. The node 110 develops a ripple voltage VR and is coupled to the inverting (−) input of a comparator 114. The non-inverting (+) input of the comparator 114 is a node 209 developing a switched error voltage SERR, which is selectively coupled to either a window voltage VW or a compensation voltage VCOMP based on the state of a switch circuit SW2 controlled by the PWM signal. The switch circuit SW2 includes two switches SW2A and SW2B, where SW2A is closed when PWM is high and opened when PWM is low, and where SW2B is opened when PWM is high and closed when PWM is low. The output voltage VO, the PWM signal and SVIN (equivalent to VIN) are provided to respective inputs of the frequency control circuit 106, which has an output coupled to one end of a window resistor RW. The other end of the resistor RW is coupled to the output of an error amplifier (EA) 116 developing the compensation voltage VCOMP. The frequency control circuit 106 develops a window current IW at its output, which is provided through the resistor RW to develop the window voltage VW relative to VCOMP. An internal reference voltage VREF is provided to the non-inverting input of the EA 116. An output voltage sense signal VOSENSE is provided to one end of the external compensation circuit 118, having its other end coupled to an input pin (shown as a feedback pin FB) of the regulator control IC 102 receiving VOSENSE. VOSENSE is either the output voltage VO or a sensed and divided version thereof, such as provided by a resistive voltage divider or the like (not shown). The FB input pin is internally provided to the inverting input of the EA 116 and to one end of an internal capacitor ICAP. The other end of ICAP is coupled to the output of the EA 116.
In operation, the transconductance amplifier 108 draws current based on the output voltage VO from node 110 to continually discharge the ripple capacitor CR. When the switch SW1 is closed upon assertion of the PWM signal, a current based on the input voltage VIN provided through the switch SW1 by the transconductance amplifier 104 to charge the capacitor CR. Since VIN is greater than VO, when the switch SW1 is closed and the capacitor CR is charged by a collective current based on a difference between the voltages VIN and VO, or VIN−VO. When the switch SW1 is opened (when PWM is not asserted) the capacitor CR is discharged based on VO. As understood by those skilled in the art, the voltage VO is continually applied to one end of the output inductor L. The other end of the output inductor L is switched between the input voltage VIN and ground, causing a ripple current to flow through the output inductor L based on VIN and VO. In this manner, the voltage VR is a ripple voltage representing the ripple current through output inductor L. The EA 116 develops the VCOMP signal as a compensation voltage indicative of the relative error of VO. In particular, the voltage on FB is compared to the reference voltage VREF which represents the target voltage level of VO. When PWM is asserted to the first level (e.g., low), the voltage of VR rises at a constant rate (based on charge voltage VIN−VO) and the switch SW2 selects VW (e.g., SW2B is closed). When the voltage of VR rises above the voltage of VW, the comparator 114 switches PWM to the second level (e.g., high) causing the switch SW2 to switch to VCOMP (e.g., SW2A is opened) and causing the switch SW1 to open so that VR decreases at a constant rate. In this manner, the comparator 114 operates as a hysteretic comparator which compares the synthetic ripple voltage VR within a window voltage between VCOMP and VW. The frequency control circuit 106 adjusts the window current IW to adjust the window voltage VW relative to VCOMP to maintain a relatively constant switching frequency of the synthetic ripple regulator 100.
It is desired that the output of the regulator have a relatively low impedance. The error signal VCOMP has a significant level of DC and is developed in an unbalanced feedback loop. Note, for example, that the window voltage VW is developed on top of the VCOMP voltage and is compared with VR emulating inductor current. In view of these factors, the control loop requires the EA 116 to have relatively high gain. The high gain of the EA 116 requires the external compensation circuit 118 to stabilize the loop to maintain loop control. The high gain of EA 116 and the corresponding need for the compensation circuit 118 consumes valuable die space on the regulator control IC 102. Further, the compensation circuit 118 causes significant phase delay and reduces transient response. In this manner, the regulator control IC 102 is not as responsive to changes of VO or VIN or changes of other operating parameters.
The transconductance amplifier 216 provides an error current IERR to an error node 204 through a pair of current outputs coupled between VDD and node 204. An error resistor RERR is coupled between node 204 and the node 112 developing the regulated voltage REG. In one embodiment, REG is approximately 1.1V and RERR is approximately 30 kΩ. In one embodiment, the transconductance (gm) of the transconductance amplifier 216 and the resistance of RERR is such that gm*RERR=40 (in which an asterisk “*” denotes multiplication). The window resistor RW is replaced with a pair of window resistors RW/2, each having one end coupled to the error node 204. In one embodiment, each of the window resistors RW/2 have a resistance of approximately 110 kΩ. The other end of one window resistor RW/2 is coupled to a node 208, which is further coupled to the positive output of the frequency control circuit 206 providing the IW+ current. The other end of the other window resistor RW/2 is coupled to a node 210, which is further coupled to the negative output of the frequency control circuit 206 providing the IW− current. A pair of window capacitors CW1 and CW2 are provided in which CW1 is coupled between nodes 208 and 204 and CW2 is coupled between nodes 210 and 204. In one embodiment the window capacitors CW1 and CW2 are relatively small-valued capacitors having approximately equal capacitance of approximately 2 pf. Node 208 develops a window voltage VW and node 210 develops a compensation voltage VCOMP. The switch SW2 selects between nodes 208 and 210 for selectively providing either one of VW or VCOMP to the non-inverting input of the comparator 114 as controlled by the PWM signal. The resistors RW/2 and the capacitors CW1 and CW2 with center node 204 and nodes 208 and 210 on either side collectively forms a balanced hysteretic window circuit.
Operation of the regulator control IC 202 is similar to that of the regulator control IC 102 with significant modifications. First, the high gain EA 116 is replaced by the low gain transconductance amplifier 216 having its output resistor RERR tied off to the constant regulation voltage REG, which is the same voltage REG used to tie off the ripple resistor R. In one embodiment, REG is approximately 1.1V. The transconductance amplifier 216 is a low gain amplifier eliminating the need for the compensation circuit 118. The resistance of the ripple resistor RRB is significantly reduced as compared to the resistance of the ripple resistor RR (e.g., 800 kΩ down to 100 kΩ in the illustrated embodiment). In this manner, the voltage VR no longer emulates the ripple current through the output inductor L. Instead, the emulated ripple voltage is provided through a high pass filter, which is made by making the modulator ripple time constant RRB*CR significantly higher than the time constant of the output inductor L, or L/RDCR (in which the forward slash “/” denotes division and in which RDCR is the DC resistance of the inductor L). In this manner, the ripple voltage is filtered to remove DC so that the inductor ripple current is viewed from the AC perspective. The hysteretic voltage window is centered at the output of the transconductance error amplifier 216 at node 204. The high pass filtering of the emulated ripple current signal and the centered voltage error signal provides a balanced configuration which eliminates the need for a high gain error amplifier. Elimination of the high gain amplifier eliminates the need for the feedback compensation circuit, which reduces the components and increases available space and speeds up the transient response of the regulator controller.
It is noted that the VR signal may saturate during load application transient as shown in
The concepts applied to the synthetic ripple regulator as described above are equally applicable to any internally compensated current-mode switching regulator or DC/DC converter.
In operation of the regulator 400, when the voltage of CS falls below VERR, the comparator CM2 sets the output of the SR latch 405 which pulls PWM high to initiate a power phase of the switch circuit 401. The voltage CS rises while PWM is high until it reaches VERR+VW at the top of the window voltage range, causing the comparator CM1 to reset the output of the SR latch 405. The PWM is then pulled low so that CS begins decreasing. The PWM signal at the output of the SR latch 409 toggles the state of the switch circuit 401 to continuously energize and de-energize the power stage in this manner. The error signal VERR is derived from the error amplifier 407 sensing the output voltage VO (directly or via VOSENSE) through the impedance network Z1 and connected using negative feedback the other feedback network Z2. The impedance networks Z1 and Z2 are often complex and difficult to tune, and they usually cannot be integrated onto an integrated circuit (IC) or chip. The error amplifier 407 is typically a high gain operational amplifier.
In operation of the regulator 500, when FCS falls below VERR by VW/2, the comparator CM2 sets the SR latch 411 to pull PWM high to initiate the power phase, and when FCS rises above VERR by VW/2, the comparator CM1 resets the SR latch 411 to pull PWM low for the remaining portion of the cycle. Thus, the output of the SR latch 411 energizes and de-energizes the power stage as described previously. The high pass filter 501 removes DC and attenuates low frequency of the CS signal and the voltage sources 503 and 505 reference FCS and VERR to the same DC level. In one embodiment, the error signal VERR is derived from a comparatively simple low-gain amplifier 507 and the external compensation circuit 405 is eliminated.
In an alternative embodiment, the high pass filter 501 is replaced with the appropriate higher-order filter for ripple cancellation and frequency tuning.
In operation of the regulator 1000, when PWM is low, SW2A is opened and SW2B is closed so that current device 1003 draws current IW from node 1002 to ground. The window current IW flows into node 1002 through RW which causes a negative window voltage (VW=−RW*IW) to develop across RW decreasing the voltage of node 1002 by VW relative to VERR. When CS falls to the lowered voltage level of node 1002, the comparator 801 switches state and pulls PWM high. When PWM is high, SW2A is closed and SW2B is opened so that current device 1005 sources current IW from VDD to node 1002. In this case, the window current IW flows through RW from node 1002 in the opposite direction which causes a positive window voltage (VW=RW*IW) to develop across RW thereby increasing the voltage of node 1002 by VW relative to VERR. When CS rises to the increased voltage level of node 1002, the comparator 801 switches state again and pulls PWM back low. Once again, the error amplifier 407 is a high gain amplifier and the compensation circuit 405 is needed for proper operation of the regulator 1000. Also, the compensation circuit 405 is externally provided (e.g., not integrated on the control IC or chip) since it must generally be tuned to ensure proper operation.
Operation of the regulator 1100 is similar to that of the regulator 1000. For the regulator 1100, node 903 is the current node developing VERR across the resistor RW relative to the REG voltage. VERR is increased by VW=IW*RW when SW2A is closed and decreased by VW when SW2A is closed forming a similar hysteretic window operation. The resistor RHP and the capacitor CHP collectively form a high pass RC filter for filtering the CS voltage to provide a filtered voltage FCS on node 907. The high pass filtering of CS to provide FCS and referencing FCS to a common DC level as VERR (via RW) enables a significant simplification of the error amplifier circuit. In this embodiment, the high gain error amplifier 407 is replaced with the error amplifier 901, which may be implemented as a low gain amplifier with little or no compensation. Thus, the compensation circuit 405 is eliminated and the entire circuit may be implemented on chip.
Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for providing out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the following claims.
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|U.S. Classification||323/286, 323/282, 323/285|
|International Classification||G05F1/565, G05F1/575|
|Cooperative Classification||H02M3/156, H02M3/158|
|European Classification||H02M3/156, H02M3/158|
|Nov 26, 2008||AS||Assignment|
Owner name: INTERSIL AMERICAS INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PHILBRICK, RHYS S. A.;HARRIS, MATTHEW B.;LAUR, STEVEN P.;REEL/FRAME:021897/0035
Effective date: 20081125
|May 4, 2010||AS||Assignment|
Owner name: MORGAN STANLEY & CO. INCORPORATED,NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNORS:INTERSIL CORPORATION;TECHWELL, INC.;INTERSIL COMMUNICATIONS, INC.;AND OTHERS;REEL/FRAME:024329/0411
Effective date: 20100427
Owner name: MORGAN STANLEY & CO. INCORPORATED, NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNORS:INTERSIL CORPORATION;TECHWELL, INC.;INTERSIL COMMUNICATIONS, INC.;AND OTHERS;REEL/FRAME:024329/0411
Effective date: 20100427
|Jun 10, 2014||AS||Assignment|
Owner name: INTERSIL AMERICAS LLC, CALIFORNIA
Free format text: CHANGE OF NAME;ASSIGNOR:INTERSIL AMERICAS INC.;REEL/FRAME:033119/0484
Effective date: 20111223
|Oct 12, 2015||FPAY||Fee payment|
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