US 8198633 B2
A gate electrode structure of a transistor may be formed so as to exhibit a high crystalline quality at the interface formed with a gate dielectric material, while upper portions of the gate electrode may have an inferior crystalline quality. In a later manufacturing stage after implementing one or more strain-inducing mechanisms, the gate electrode may be re-crystallized, thereby providing increased stress transfer efficiency, which in turn results in an enhanced transistor performance.
1. A method of forming a transistor, comprising:
forming a first gate electrode material on a gate dielectric material that is formed above a silicon-containing semiconductor layer, said first gate electrode material having a polycrystalline structure and comprising a plurality of first grains;
forming a second gate electrode material on said first gate electrode material, said second gate electrode material having a polycrystalline structure and comprising a plurality of second grains, wherein a grain size of at least some of said plurality of second grains is smaller than a grain size of said plurality of first grains;
forming a gate electrode from said first and second gate electrode materials;
providing at least one strain-inducing mechanism for said transistor; and
after providing said at least one strain-inducing mechanism, increasing said grain size of at least some of said plurality of second grains, wherein increasing said grain size comprises annealing said gate electrode.
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12. A method, comprising:
depositing a first polycrystalline semiconductor material comprising a plurality of first grains on a dielectric layer in a deposition ambient established on the basis of a predefined parameter setting, said dielectric layer being formed on a silicon-containing semiconductor layer;
changing said parameter setting;
depositing a further semiconductor material using said changed parameter setting, wherein depositing said further semiconductor material comprises forming at least a second polycrystalline semiconductor material comprising a plurality of second grains, wherein a grain size of at least some of said plurality of second grains is smaller than a grain size of said plurality of first grains;
forming a gate electrode from said polycrystalline semiconductor material and said further semiconductor material;
providing at least one strain-inducing mechanism so as to create strain in a portion of said silicon-containing semiconductor layer positioned below said gate electrode; and
annealing said gate electrode so as to increase said grain size of at least some of said plurality of second grains.
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20. A method, comprising:
forming a gate dielectric material above a silicon-containing semiconductor layer;
forming a first polycrystalline material above said gate dielectric material;
forming an amorphous material above said first polycrystalline material
forming a gate electrode from said first polycrystalline material and said amorphous material;
providing at least one strain-inducing mechanism so as to create strain in a portion of said silicon-containing semiconductor layer positioned below said gate electrode; and
after providing said at least one strain-inducing mechanism, annealing said gate electrode, wherein annealing said gate electrode comprises crystallizing said amorphous material.
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1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors having strained channel regions by using stress-inducing sources, such as stressed sidewall spacers of gate electrodes, embedded strain-inducing semiconductors alloys and the like, to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Generally, a plurality of process technologies are currently practiced to fabricate integrated circuits, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode located close to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region is a dominant factor determining the performance of MOS transistors.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith, such as reduced controllability of the channel, also referred to as short channel effects, and the like, that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For instance, the thickness of the gate insulation layer, typically an oxide-based dielectric, has to be reduced with reducing the gate length, wherein a reduced thickness may result in increased leakage currents, thereby posing limitations for oxide-based gate insulation layers at approximately 1-2 nm. Thus, the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques, for example, for compensating for short channel effects, with oxide-based gate dielectric scaling being pushed to the limits with respect to tolerable leakage currents. It has, therefore, been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential of achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the problems encountered with the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance, by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region along the channel length direction for a standard crystallographic orientation increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity. On the other hand, uniaxial compressive strain in the channel region for the same configuration as above may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
For this purpose, a plurality of mechanisms have been developed that may be appropriate for creating a desired high strain component in the channel region of transistor elements. For example, dielectric materials, such as silicon nitride, silicon dioxide and the like, may be deposited with a high internal stress level which may be taken advantage of to provide a specific type of strain in the adjacent channel region. Silicon nitride is a frequently used material for forming sidewall spacer elements on sidewalls of gate electrode structures and may be deposited with tensile or compressive stress, which may then be transferred into the channel region via the gate electrode structure. In other approaches, the isolation structures that usually delineate respective active regions of transistor elements may be provided in the form of shallow trench isolations in sophisticated applications, wherein silicon dioxide, silicon nitride and the like may be used as insulating fill materials, which may also be provided in the form of a compressively stressed material, thereby exerting the corresponding stress on the transistor active region, which may finally result in a corresponding strain component in the channel region. In still other approaches, a strain-inducing semiconductor material may be locally incorporated or embedded in the transistor active regions, for instance in the drain and source areas, thereby also creating a corresponding strain in the adjacent channel region.
Moreover, after completing the basic transistor structure, additional strain-inducing mechanisms may be applied, for instance, by providing highly stressed dielectric materials above the transistor structure, for instance in the form of an etch stop material that may typically be used during the patterning of an interlayer dielectric material that is provided for passivating the circuit elements and providing a platform for forming additional wiring levels of the semiconductor device. Thus, transistor performance may be efficiently enhanced on the basis of one or more of the above-identified strain-inducing mechanisms, wherein, however, the finally achieved gain in performance may be less than expected due to a significant “absorption” of stress, which may be caused by the presence of the gate electrode structure. That is, it is assumed that the material of the gate electrode may act as a significant barrier with respect to the stress transfer mechanism, for instance provided by stressed spacer elements, embedded strain-inducing semiconductor material, stress-inducing isolation structures and the like. Since even a moderate increase of transistor performance may be associated with significant efforts with respect to the adaptation or new development of complex manufacturing techniques, as previously described, it is highly desirable to more efficiently exploit any mechanism for enhancing transistor performance, such as any of the above-described strain-inducing mechanisms.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure relates to methods and semiconductor devices in which the deleterious influence of the gate electrode on the stress transfer efficiency may be reduced or may even be used as a strain-inducing source by modifying the structure of the gate electrode and thus the mechanical characteristics thereof in order to enable a more efficient stress transfer into the channel region and/or to additionally create strain in the gate electrode structure. For this purpose, the molecular structure, that is, the crystal quality of the semiconductor material, such as silicon material, silicon/germanium material and the like, may be changed during a high temperature anneal process after implementing one or more strain-inducing mechanisms, thereby enabling more efficient stress transfer into the channel region, which may thus contribute to an increase of transistor performance. In some illustrative aspects disclosed herein, a change of the crystal state of the gate electrode material may be accomplished in a portion of the gate electrode material only, so that a desired high quality interface between the gate electrode material and the gate dielectric layer may be maintained, while nevertheless providing a significant change of a crystalline state of the remaining gate electrode material, thereby enabling an efficient stress transfer during the anneal process. In still other illustrative aspects disclosed herein, a different material composition may be provided in a portion of the gate electrode material so that, in combination with the re-establishing of the crystalline status of the gate electrode material, also the difference in material composition may provide overall a highly efficient strain-inducing effect.
One illustrative method disclosed herein relates to the formation of a transistor element. The method comprises forming a first gate electrode material on a gate dielectric material that is formed above a silicon-containing semiconductor layer, wherein the first gate electrode material has a polycrystalline structure. The method further comprises forming a second gate electrode material on the first gate electrode material, wherein the second gate electrode material has an inferior crystalline quality compared to the first gate electrode material. Additionally, the gate electrode is formed from the first and second gate electrode materials and at least one strain-inducing mechanism is provided for the transistor. Additionally, the method comprises annealing the gate electrode to enhance the crystalline quality of the second gate electrode material.
A further illustrative method disclosed herein comprises depositing a polycrystalline semiconductor material on a dielectric layer in a deposition ambient established on the basis of a predefined parameter setting, wherein the dielectric layer is formed on a silicon-containing semiconductor layer. Moreover, the parameter setting is changed and a further semiconductor material of reduced crystalline quality is deposited on the basis of the changed parameter setting. Moreover, a gate electrode is formed from the polycrystalline semiconductor material and the further semiconductor material that has the reduced crystalline quality. Additionally, the method comprises providing at least one strain-inducing mechanism to create strain in a portion of the semiconductor layer positioned below the gate electrode. Finally, the gate electrode is annealed to enhance the reduced crystalline quality.
One illustrative semiconductor device disclosed herein comprises a polysilicon material formed on a gate dielectric layer of a gate electrode structure of a transistor, wherein the polysilicon material has a first stress level. Moreover, the semiconductor device comprises a silicon-containing semiconductor material formed on the polysilicon material and having a second stress level that differs from the first stress level. Additionally, a metal silicide material is formed on the silicon-containing semiconductor material. Additionally, a strain-inducing component is provided that induces a strain in a channel region of the transistor.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Generally, the present disclosure provides techniques and semiconductor devices in which the efficiency of strain-inducing mechanisms provided prior to the completion of the basic transistor structure may be increased by increasing the crystalline quality of a significant portion of the gate electrode material, which has been provided in an earlier manufacturing stage with inferior crystalline quality, after implementing respective strain-inducing mechanisms, thereby contributing to an overall enhanced strain in the channel region of the transistor. Without intending to restrict the present disclosure to the following explanation, it is assumed that the “re-crystallization” of a significant portion of the gate electrode material may result in a mechanical configuration of the gate electrode, which in turn is a more direct interaction of the strain-inducing mechanisms into the channel region, since, during the re-crystallization process, the barrier effects of the gate electrode may be reduced. On the other hand, in some illustrative embodiments disclosed herein, desired interface characteristics between the gate dielectric material and the gate electrode material, such as polysilicon, may be maintained by providing an initial portion of the gate electrode material with the desired crystalline quality, that is, in a polycrystalline state with moderately high grain sizes, while, after a specified layer thickness is achieved, the deposition parameters of the deposition ambient may be changed or a further deposition process may be performed to create a reduced grain size, i.e., an inferior crystalline quality, or even deposit a substantially amorphous gate electrode material, which may then be re-crystallized, i.e., the grain size may be increased, on the basis of anneal elevated temperatures. In some illustrative embodiments disclosed herein, the effect of mechanical modification may be even further enhanced and/or the electronic characteristics of a portion of the gate electrode material may be appropriately adapted by introducing other components, such as germanium, tin, carbon and the like, thereby enabling a high degree of flexibility in designing overall transistor characteristics.
The semiconductor device 100 as shown in
Thereafter, the first gate electrode material 104A may be deposited, according to one illustrative embodiment, as a polysilicon material using well-established low pressure chemical vapor deposition (CVD) techniques. Thus, the device 100 may be exposed to a deposition ambient 105 in which appropriate precursor gases may be supplied on the basis of well-established deposition recipes. During the deposition 105, elevated temperatures may be applied so that the substrate temperature of the device 100 and thus also the surface temperature of the device 100 may be at a specified temperature that provides a moderately high grain size of the gate electrode material 104A, such as a polysilicon material. It is well known that the crystalline quality of a polysilicon material may strongly depend, among other things, on the process temperature. For example, for otherwise given process parameters and for a given deposition surface, such as the gate dielectric material 103, the crystalline quality and thus the grain size may be controlled by the substrate temperature, which may be in the range of approximately 500-700° C. Consequently, during the deposition process 105, the first gate electrode material 104A may be provided in the form of a polycrystalline semiconductor material having a desired high crystalline quality in order to obtain desired interface characteristics with the gate dielectric material 103.
In some illustrative embodiments, during the deposition of the gate electrode materials 104B and/or 104C, other process parameters may be changed in order to influence the crystalline quality. For instance, the deposition pressure, the gas flow rates and the like may be changed. In some illustrative embodiments, in addition to changed process parameters for reducing the crystalline quality of the materials 104B, 104C, at any appropriate deposition phase, additional materials may be supplied to the deposition ambient, for instance in the form of germanium-containing precursors, tin-containing precursors, carbon-containing precursors and the like, in order to provide desired electronic characteristics and also “amplify” the effect of the mechanical modification upon re-crystallizing the materials 104B, 104C having the inferior crystalline quality. For instance, a silicon/germanium mixture may be deposited with a fraction of germanium of up to approximately 35 atomic percent, while, in other cases, tin may be incorporated, possibly in combination with germanium, in order to obtain a silicon/tin/germanium mixture, while, in other cases, carbon may be introduced with a fraction of up to several atomic percent.
Thereafter, the further processing may be continued on the basis of well-established process techniques.
The semiconductor device 100 as shown in
As previously indicated, in some illustrative embodiments, the mechanical modification may be increased by providing an appropriate material mixture, such as silicon/germanium, silicon/carbon and the like, which may further increase a corresponding discrepancy in mechanical characteristics, such as volume upon re-crystallizing the portion 104B. Furthermore, the overall electronic characteristics may be adjusted, for instance the overall conductivity may be increased by adding a germanium component in the material 104B.
Thereafter, further processing may be continued, for instance by depositing a strain-inducing dielectric material, such as a silicon nitride material, a nitrogen-containing silicon carbide material and the like, followed by the deposition of an appropriate interlayer dielectric material, such as silicon dioxide and the like.
As a result, the present disclosure provides semiconductor devices and techniques for forming the same in which the stress transfer efficiency of one or more strain-inducing mechanisms, which may be provided prior to completing the basic transistor configuration, may be enhanced by a mechanical modification of the gate electrode. For this purpose, the gate electrode material may be provided with different crystalline qualities so as to maintain desired interface characteristics in combination with a desired gate dielectric material, while on the other hand providing a significant change of the crystalline structure upon annealing the gate electrode structure after patterning the same and after implementing one or more strain-inducing mechanisms. Consequently, overall transistor performance may be increased while not unduly contributing to overall process complexity since, in some illustrative embodiments, a corresponding modification of the mechanical characteristics of the gate electrode may be accomplished without any additional process steps.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.