|Publication number||US8198673 B2|
|Application number||US 13/080,702|
|Publication date||Jun 12, 2012|
|Filing date||Apr 6, 2011|
|Priority date||Nov 9, 2009|
|Also published as||CN102893380A, DE112010004330B4, DE112010004330T5, US7989297, US20110108918, US20110180872, WO2011056336A2, WO2011056336A3|
|Publication number||080702, 13080702, US 8198673 B2, US 8198673B2, US-B2-8198673, US8198673 B2, US8198673B2|
|Inventors||Haizhou Yin, Xinhui Wang, Kevin K. Chan, Zhibin Ren|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Classifications (14), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional application of U.S. patent application Ser. No. 12/614,699, filed Nov. 9, 2009, the content of which is incorporated herein by reference in its entirety.
The present invention relates generally to the field of semiconductor device manufacturing, and in particular relates to method of manufacturing field-effect-transistors through asymmetric epitaxial growth.
With shrinking dimensions of various integrated circuit components, transistors such as field-effect transistors (FETs) have experienced, over time, dramatic improvement in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Nevertheless, performance improvement brought up by this type of “classic” scaling, in device dimensions, has recently met obstacles and in some cases even been challenged, when the scaling goes beyond a certain point, by the increase in leakage current and variability that are inevitably associated with this continued reduction in device dimensions.
In general, power consumption and performance of integrated circuits stem from and depend upon capacitance, resistance, and leakage current of components, such as electrical junctions, wires, property of dielectric material, etc., that the integrated circuits may contain. In the case of a field-effect-transistor, it has been discovered that capacitance in the drain side and resistance in the source side, in particular, contribute largely to the overall performance of the FET, and reductions in capacitance in the drain side and resistance in the source side may help further improve performance of the FET.
Embodiments of the present invention provide a method of forming asymmetric field-effect-transistor. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure.
In one embodiment, performing epitaxial growth creates a source (or source extension) region in the second side of the gate structure and a drain (or drain extension) region in the first side of the gate structure, the source region formed by the epitaxial growth having a height higher than the drain region formed by the epitaxial growth. In one embodiment, the source region and the drain region cover at least a portion of sides of the spacers at the first and second sides of the gate structure.
According to one embodiment, the method further includes creating recesses in the first and second sides of the gate structure before performing the angled ion-implantation. In one aspect, the ion-implanted region is formed at a top surface of the recesses.
In another embodiment, performing epitaxial growth includes growing a drain region in the first side and a source region in the second side of the gate structure, the drain region having a height lower than that of the source region. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate, and the method further includes performing ion-implantation in the source region and the drain region, wherein the ion-implantation creates a PN-junction that extends downwardly and is in touch with an insulating layer inside the SOI substrate. In another embodiment, performing angled ion-implantation includes implanting ions of As or BF2 into the substrate in an area adjacent to the first side of the gate structure at substantially close to a surface of the substrate.
The invention will be understood and appreciated more fully from the following detailed description of the invention, taken in conjunction with the accompanying drawings of which:
It will be appreciated that for the purpose of simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, dimensions of some of the elements may be exaggerated relative to other elements for clarity purpose.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments of the invention. However, it is to be understood that embodiments of the invention may be practiced without these specific details.
In the interest of not obscuring presentation of essences and/or embodiments of the invention, in the following detailed description, some processing steps and/or operations that are known in the art may have been combined together for presentation and/or for illustration purpose and in some instances may have not been described in detail. In other instances, some processing steps and/or operations that are known in the art may not be described at all. In addition, some well-known device processing techniques may have not been described in detail and, in some instances, may be referred to other published articles, patents, and/or patent applications for reference in order not to obscure description of essences and/or embodiments of the invention. It is to be understood that the following descriptions have rather focused on distinctive features and/or elements of various embodiments of the invention.
Next, in order to form a field-effect-transistor 100 with asymmetric height-raised source/drain, the method may include forming a gate stack 120 on top of substrate 110 by applying one or more processes of front-end-of-line (FEOL) technologies. Gate stack 120 may include at least a gate dielectric layer, a gate conductor layer 121, and a hardmask layer 122. Hardmask layer 122, such as a silicon-nitride (SiN) hardmask, may be formed on top of gate conductor 121 to prevent, during a subsequent step of forming source/drain of FET 100, potential epitaxial growth of silicon on top of gate conductor 121 (which may be silicon as well). After forming gate stack 120, spacers 131 and 132 may be formed at the sidewalls of gate stack 120. Spacers 131 and 132 are formed to define regions, for example to the left and to the right of gate stack 120, where source and drain of FET 100 may be formed respectively, as being described below in more details.
Here, it is worth noting that a person skilled in the art will appreciate that embodiments of the present invention, as being described above and in more details hereafter, are not limited in the above aspect of forming asymmetric source/drain of a FET. Embodiments of the present invention may be similarly applied in other areas such as in forming asymmetric source/drain extensions, in addition to source/drain of a FET. For instance in the above example, when spacers 131 and 132 are formed as off-set spacers which has a substantially thin thickness, the below described process may be similarly applied in forming asymmetric source/drain extensions, in replacement of or in addition to asymmetric source/drain, of FET 100. However, hereinafter, in order not to obscure essence of the present invention, the below description will be focused mainly on forming asymmetric source/drain of a field-effect-transistor.
According to one embodiment, the implantation may be performed using type of ions, such as As and/or BF2, that may effectively suppress silicon epitaxial growth on top thereof. In addition, the implantation may be performed only shallowly around the top surface of silicon layer 113, by properly controlling the energy level of ions used in the implantation process, upon which epitaxial growth may be performed in a subsequent step.
Other components that may be part of FET 100 may be formed regularly using well-known processes of FEOL, either before or after the formation of asymmetric source/drain regions. Detailed description of their formation is therefore omitted hereinafter in order not to obscure the true essence of present invention.
Next, the method may include forming a gate stack 220 on top of SOI layer 212. Gate stack 220 may include a gate dielectric layer, a gate conductor layer 221 and a hardmask layer 222, for example a silicon-nitride (SiN) layer, on top thereof. SiN hardmask layer 222 may be formed to prevent epitaxial growth of silicon on top of gate conductor 221 in subsequent steps of epitaxially growing source and/or drain. Spacers 231 and 232 may next be formed adjacent to sidewalls of gate stack 220. Inside silicon layer 212, source/drain extensions 214 may be formed, which typically refer to doped regions of 214 underneath spacers 231 and 232 and close to gate stack 220.
According to one embodiment, because in the drain region 241 epitaxial growth is performed on top of ion-implanted region 216, the rate of growth of silicon-germanium on top of region 216 may be significantly suppressed to be slower than the epitaxial growth on the source region 242, creating a silicon-germanium layer 241 that has a height less than silicon-germanium layer 242 that is formed to the left side of gate stack 220. In one embodiment, silicon-germanium layer 241 is formed to overlap at least partially with drain extension region 214 underneath spacer 231.
While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the spirit of the invention.
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|U.S. Classification||257/327, 257/E21.561, 257/347|
|Cooperative Classification||H01L29/66659, H01L21/26586, H01L29/66628, H01L29/7835, H01L29/66636|
|European Classification||H01L29/78F3, H01L29/66M6T6F11H, H01L29/66M6T6F11E, H01L29/66M6T6F11D3, H01L21/265F|