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Publication numberUS8209490 B2
Publication typeGrant
Application numberUS 10/749,752
Publication dateJun 26, 2012
Filing dateDec 30, 2003
Priority dateDec 30, 2003
Fee statusPaid
Also published asCN1890646A, CN100585572C, US20050144390, WO2005066798A1
Publication number10749752, 749752, US 8209490 B2, US 8209490B2, US-B2-8209490, US8209490 B2, US8209490B2
InventorsMatthew Mattina, George Z. Chrysos
Original AssigneeIntel Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Protocol for maintaining cache coherency in a CMP
US 8209490 B2
Abstract
The present application is a protocol for maintaining cache coherency in a CMP. The CMP design contains multiple processor cores with each core having it own private cache. In addition, the CMP has a single on-ship shared cache. The processor cores and the shared cache may be connected together with a synchronous, unbuffered bidirectional ring interconnect. In the present protocol, a single INVALIDATEANDACKNOWLEDGE message is sent on the ring to invalidate a particular core and acknowledge a particular core.
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Claims(12)
1. A method for maintain cache coherency comprising:
receiving, with a shared cache, a write request referencing a block from a requesting processor core of the plurality of processor cores on a processor, wherein the plurality of processor cores each include a private cache, and wherein the plurality of cores and the shared cache are connected by a ring interconnect;
generating a single message, with the shared cache, in response to receiving the write request;
delivering an invalidation part of the single message to at least the second processor core;
delivering a write-acknowledgement part of the single message only to the requesting processor core;
invalidating the block in the private cache included in the second processor core in response to the second processor core receiving the invalidation part of the single message; and
write-acknowledging the write request for the requesting processor core in response to the requesting processor core receiving the write-acknowledgment part of the single message transmitted on the ring interconnect.
2. The method of claim 1, wherein the shared cache includes one or more banks, wherein the one or more cache banks is responsible for a subset of a physical address space of a computer system including the processor, and wherein the block is associated with a physical address of the physical address space of the computer system.
3. The method of claim 1 wherein the first message includes an InvalidateAndAcknowledge message , and wherein generating the InvalidateAndAcknowledge message, with the shared cache, is further in response to the block being present in the shared cache and the second processor core being a custodian for the block.
4. The method of claim 1 wherein the first message includes an InvalidateAllAndAcknowledge message, and wherein generating the InvalidateAllAndAcknowledge message, with the shared cache, is further in response to the block not being present in the shared cache and none of the plurality of processor cores being a custodian for the block.
5. The method of claim 1 wherein the plurality of processor cores writes data through to the shared cache.
6. The method of claim 1 wherein the plurality of processor cores each include a merge buffer, and wherein each of the merge buffers are to coalesce multiple stores to a same block.
7. The method of claim 6 wherein each private cache including in the plurality of cores are not to hold dirty data, and wherein each of the merger buffers are to hold the dirty data.
8. The method of claim 1, further comprising fetching, with the shared memory, a second block from a memory and generating, with the shared memory, a write acknowledge message to provide a write acknowledgement to the requesting processor core in response to receiving a second write request referencing the second block, the second block not being present in the shared cache and not being owned by any of the plurality of processor cores.
9. The method of claim 8 further comprising generating, with the shared cache, an evict message to evict a third block from an owning processor core of the plurality of processor cores and generating a second write acknowledge message to provide a second write acknowledgment to the requesting processor core in response to receiving a third write request referencing the third block, the third block being present in the shared cache and the owning processor core of the plurality of cores owns the third block.
10. The method of claim 1 wherein a bank of the shared cache is to be a home location for a non-overlapping portion of a physical address space associated with the block.
11. The method of claim 1 wherein the ring interconnect includes a synchronous, unbuffered, bidirectional, ring interconnect.
12. The method of claim 1 wherein the first message has a fixed deterministic latency around the ring interconnect.
Description
BACKGROUND INFORMATION

A cache coherent multiprocessor system contains two or more independent processor cores. These cores contain caches for replicating memory data close to where it will be consumed. A function of the cache coherent protocol is to keep these caches coherent, meaning, to ensure a consistent view of memory.

A cache coherent CMP is a special case of a cache coherent multiprocessor system. In a CMP, the independent processor cores are integrated onto a single piece of silicon. Currently, there is no protocol to ensure cache coherency in a CMP. Thus, a need exists for an on-chip cache coherence protocol maintaining coherency among the on-chip processor caches.

BRIEF DESCRIPTION OF THE DRAWINGS

Various features of the invention will be apparent from the following description of preferred embodiments as illustrated in the accompanying drawings, in which like reference numerals generally refer to the same parts throughout the drawings. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the inventions.

FIG. 1 is a block diagram of a CMP on a ring interconnect.

DETAILED DESCRIPTION

In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of the invention. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the invention may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

FIG. 1 illustrates a CMP design containing multiple processor cores P0, P2, P6, etc, with private caches on each core and a single on-chip shared cache 10. The shared cache 10 consists of multiple, independent cache banks (not shown). Each bank of the shared cache 10 is responsible for some subset of the physical address space of the system 5. That is, each shared cache bank is the “home” location for a non-overlapping portion of the physical address space. The processor cores P0, P2, etc and the shared cache 10 may be connected together with a synchronous, unbuffered bidirectional ring interconnect 15.

The CMP design of FIG. 1 contains core caches that are write-thru as opposed to write-back. Meaning that when the core writes data, rather than putting the written data into a cache on the core, the core just writes the data thru to the shared cache 10. When a core writes a piece of data, rather than storing the data in its private cache, the system 5 enables writing the data through to the shared cache 10. This is because of the bandwidth the ring interconnect 15 is able to support.

Typically, in cache coherent multiprocessor systems, a flow is needed to extract dirty data, also known as victim data, and then write the dirty data through. However, this is no longer necessary with the system 5 of FIG. 1. With this system 5, there is no need for error checking code on the private caches because the data is no longer dirty. There is another copy of the data in the shared cache 10. If the data gets corrupted, the system does not need to correct it because a backup copy exists in the shared cache 10.

Furthermore, in each core P0, P2, P6, etc, there is a coalescing write buffer or a merge buffer (not shown). Instead of the dirty data going into the private cache of a core, the dirty data may get put into this merge buffer, which is a much smaller structure. The merge buffer is continuously purging or emptying the writes back to the shared cache 10. So the system 5 does not necessarily write-thru immediately, but instead, the system 5 puts the dirty data into the merge buffer. The dirty data are put into the merge buffer and once the merge buffer is full, it pushes the writes into the shared cache 10 in a timely fashion. Since this is a CMP shared cache design, other processors on the ring 15 may request this data that was written by one of the cores and pushed out. So by pushing the data out to the shared cache 10 in a timely fashion, the data is being placed in a common place where other processor on the CMP can have access to the data.

In the system of FIG. 1, the caches are block based, and stores in the cores are subblock based. So when a store occurs, it is storing 1, 2, 4, 8, or 16 bytes of data. Advantageously, the merge buffer will coalesce multiple stores to the same block, but different bytes, before doing the write-thru, thus saving bandwidth.

As stated previously, FIG. 1 illustrates a non-blocking ring interconnect 15. There is no buffering in the ring 15, so transactions are always going around the ring 15. For example, if the system 5 is at processor P0 on the ring 15, and a message is being sent to processor P6 on the ring 15, there are five processors in between P0 and P6. The system 5 knows that if the message is sent during cycle X, the system 5 will get the message at X+5 cycles. This means that there is a fixed deterministic latency in this system 5 since the packet (message) never gets blocked in the ring 15.

The present coherence protocol is designed to maintain coherence only within a CMP. Assuming a standard invalidate-based protocol, with the usual 4-state MESI design for maintaining cache coherence between chips, in a shared cache the block can be in one of four states.

    • 1. Not present
      • b. Block X is not present in the shared cache (or in any of the core caches).
    • Present and owned by core C
      • c. Block X is in the shared cache and core C has exclusive write privileges for block X.
    • Present and not owned and custodian=C
      • d. Block X is in the shared cache and a single core has a copy
      • e. of block X.
    • Present and not owned and no custodian
      • f. Block X is in the shared cache but multiple cores have copies of block X.
      • g. Where:
    • X=the physical address of requested block
    • R=the core that requested the READ of block X
    • W=core that initiated a WRITE of block X
    • H=home shared cache bank for X
    • O=core that temporarily owns block X

The above protocol describes the fundamental operations initiated by the cores during READS (loads) and WRITES (stores). First a READ flow will be discussed and then a WRITE flow.

In a READ flow, when core R executes a load to address X and address X is not contained in the core cache, a READ message is sent to home shared cache bank H for address X. The home shared cache bank H can take three possible actions, depending on the state of block X as recorded by H.

Initially, if the state of X is not present, then in this case H does not have a copy of X in the shared cache. Thus, H sends a request to the memory buffer to fetch block X from memory. When H receives block X from memory, it will deliver the block to R, and H will record that R is the custodian, since R is the only core with a copy of block X.

Second, if the state of X is present, not owned, custodian=R, then in this instance, assume that H receives another READ request, but this time from R1. H does contain the requested block and no private cache has an exclusive copy of the block. H reads the block from the cache and delivers it to R1. H also marks the block as having no custodian since multiple cores (R and R1) now have copies of block X.

Finally, if the state of X is present and owned by core O, then in this case, H does contain the requested block, but core O contains an exclusive copy of the block. Thus H sends an EVICT message to core O. H then stalls the request to X and waits for a response from O. Once O receives the EVICT message, it sends the updated data for block X to H. Upon H receiving block X, it delivers block X to R.

In a WRITE flow, when core W executes a store to address X and address X is not present in the coalescing write buffer, a WRITE message is sent to home shared cache bank H for address X on the ring. The home shared cache bank H can take four possible actions, depending on the state of block X.

Initially, if the state of X is not present, then in this case, H does not have a copy of X in the shared cache. Thus H sends a request to the memory buffer to fetch block X from memory. When H receives block X from memory, it delivers a WRITE ACKNOWLEDGEMENT signal to core W, and records core W as the custodian of block X.

Secondly, if the state of X is present, not owned and custodian is R, then in this case, H does contain the requested block. H sends a merged INVALIDATEANDACKNOWLEDGE signal around the ring, using the properties of the ring. The INVALIDATE part is delivered only to core R, the custodian, invalidating the cached copy. The WRITEACKNOWLEDGEMENT part is delivered only to core W. This is advantageous because the shared cache is only sending one message to invalidate to core R and acknowledgement to core W. With the ring interconnect, there is no longer a need to send two separate messages. However, if the custodian is the same as the core that is initiating the WRITE, then no invalidate is sent. All other steps would remain the same. H then records W as the owner of block X and changes the custodian to W because no other core can now have a cached copy of X.

Next, if the state of X is present, not owned and no custodian, then in this instance, block X is present, but there is no custodian. This means that H does not know which cores have cached copies of X. Therefore, H sends a single INVALIDATEALLAND WRITEACKNOWLEDGE message around the ring. The INVALDIATE part is delivered to all cores, invalidating the cached copies. The WRITEACKNOWLEDGEMENT part is delivered only to core W, the processor that requested the write. H changes the custodian to W because no other core can now have a cached copy of X.

Finally, if the state of X is present, owned by core O, then in this case, H does contain the requested block, but core O contains an exclusive copy of the block. Thus, H sends an EVICT message to core O. Then H stalls the request to X and waits for a response from O. When O receives the EVICT message, it sends the updated data for block X to H. When H receives block X, it delivers a WRITE ACKNOWLEDGEMENT to core W, and records core W as the custodian of block X.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of the invention. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the invention may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US9244841 *Dec 31, 2012Jan 26, 2016Advanced Micro Devices, Inc.Merging eviction and fill buffers for cache line transactions
US20140189245 *Dec 31, 2012Jul 3, 2014Advanced Micro Devices, Inc.Merging eviction and fill buffers for cache line transactions
Classifications
U.S. Classification711/141, 711/130, 711/210, 711/121
International ClassificationG06F9/26, G06F9/34, G06F12/00, G06F13/28, G06F13/00, G06F12/08
Cooperative ClassificationG06F12/0811, G06F12/084, G06F12/0813, G06F12/0831
European ClassificationG06F12/08B4S, G06F12/08B4N, G06F12/08B4P4
Legal Events
DateCodeEventDescription
Jul 2, 2004ASAssignment
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MATTINA, MATTHEW;CHRYSOS, GEORGE Z.;REEL/FRAME:014814/0747;SIGNING DATES FROM 20040526 TO 20040626
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MATTINA, MATTHEW;CHRYSOS, GEORGE Z.;SIGNING DATES FROM 20040526 TO 20040626;REEL/FRAME:014814/0747
Dec 9, 2015FPAYFee payment
Year of fee payment: 4