|Publication number||US8212349 B2|
|Application number||US 12/649,092|
|Publication date||Jul 3, 2012|
|Filing date||Dec 29, 2009|
|Priority date||Dec 29, 2009|
|Also published as||US20110156238|
|Publication number||12649092, 649092, US 8212349 B2, US 8212349B2, US-B2-8212349, US8212349 B2, US8212349B2|
|Inventors||Hung-Hsin Hsu, Chin-Ming Hsu, Jui-Ching Hsu|
|Original Assignee||Powertech Technology Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Classifications (60), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a packaged semiconductor device, and more particularly to a semiconductor package including chip(s) using copper processes.
Semiconductor devices are always developing toward smaller feature sizes with higher densities of circuitry. When feature size is below 0.25 um, RC delay caused by the resistivity of metal traces and the parasitic capacitance of dielectric becomes the major key factor impacting the operation speed of semiconductor devices. Therefore, semiconductor industries have implemented copper traces in chips to replace the conventional Al/W or Al/Cu traces when feature sizes are below 0.13 um to increase the operation frequency of semiconductor devices so that copper processes have become the mainstream of multiple metal layers of high-end IC technology in the world. Since copper is an active metal, any copper ion from chips or substrates becomes the killing contaminant to the performance of Si materials and other dielectric materials. Once the semiconductor layers of Si chips are penetrated and contaminated by copper ions, the life cycles of minor carriers are shortened and the leakage current of devices increases. Furthermore, when copper ions penetrate into internal dielectric layer of IC chips, the breakdown electric fields are decreased with the increase of leakage current.
In the conventional chip packages, not only chips have copper circuitry but also substrates have many copper circuitry in different layers where normally a gold layer is disposed on the I/O pads of copper traces in substrates to prevent copper oxidation and to enhance electrical connections so that bonding wires can be used as electrical connection between chips and substrates. A barrier layer is formed between the gold layer and the copper circuitry to avoid inter-metallic diffusion between the gold layer and the copper layer. However, the barrier layer in substrate is only formed under I/O connecting pads and is very localized with a very thin thickness which can not effectively stop copper ions diffusing from the copper circuitry to the semiconductor layers of chips. Moreover, the copper ions of the chips also diffuse to the semiconductor layers leading to function failure of the chips, especially a lower chip disposed between an upper chip and the substrate which is more subject to function failure issues in the stacked package having chips using copper process.
The main purpose of the present invention is to provide a semiconductor package having chip using copper process to prevent copper ions (Cu ions) diffusing from copper circuitry of substrates to the active surfaces of chips to avoid function failure of chips.
The second purpose of the present invention is to provide a semiconductor package having chip using copper process to prevent copper ions diffusion and contamination of interposer chip in multi-chip stacked package to enhance product reliability.
According to the present invention, a semiconductor package having chip using copper process primarily comprises a substrate, a first chip using copper process, and a first electrical connecting component. The substrate has a core layer, a copper circuitry including at least a connecting pad, a patterned diffusion barrier on the copper circuitry, and a solder mask, wherein the copper circuitry is formed on the core layer and the patterned diffusion barrier has such a pattern identical to the copper circuitry that an upper surface of the copper circuitry is completely covered. The solder mask covers the patterned diffusion barrier and the core layer and has an opening to expose a portion of the patterned diffusion barrier on the connecting pad. The substrate further has a bonding layer formed on the portion of the patterned diffusion barrier inside the opening. The first chip is disposed on the substrate, and the first chip has a first copper pad. The first electrical connecting component connects the first copper pad to the bonding layer. The first chip described in the above semiconductor package is also revealed in the present invention.
A semiconductor package having chip using copper process and the chips according to the present invention has the following advantages and functions:
1. Through the identical patterns between the patterned diffusion barrier and the copper circuitry of the substrate as a technical mean, the patterned diffusion barrier can completely cover the upper surface of the copper circuitry to prevent copper ions diffusing from the copper circuitry of the substrate to the active surface or semiconductor layer of the chip to avoid function failure of chip using copper process, especially to avoid function failure of the chip stacked in the middle of an multi-chip stacked package.
2. Through the disposition the barrier layer completely covering the backside of the semiconductor layer of a chip using copper process as a technical mean, the diffusion and contamination of copper ions between stacked chips can effectively be avoided to enhance product reliability.
3. Through complete coverage of the patterned diffusion barrier on the upper surface of the copper circuitry as a technical mean, the patterned diffusion barrier can serve as an etching mask during the formation of copper circuitry so that the copper circuitry does not extend to the edges of the core layer, i.e., the conventional plating lines can be eliminated and the cut ends of the conventional plating lines exposed from the edges of the core layer can be avoided to prevent electrical static discharging.
With reference to the attached drawings, the present invention is described by means of the embodiment(s) below where the attached drawings are simplified for illustration purposes only to illustrate the structures or methods of the present invention by describing the relationships between the components and assembly in the present invention. Therefore, the components shown in the figures are not expressed with the actual numbers, actual shapes, actual dimensions, nor with the actual ratio. Some of the dimensions or dimension ratios have been enlarged or simplified to provide a better illustration. The actual numbers, actual shapes, or actual dimension ratios can be selectively designed and disposed and the detail component layouts may be more complicated.
According to the first embodiment of the present invention, a semiconductor package having chip using copper process is illustrated in
The substrate 110 has a core layer 111, a copper circuitry 113 including at least a connecting pad 112, a patterned diffusion barrier 114, and a solder mask 115. The substrate 110 is a chip carrier for electrical connections to the chip 120. The core layer 111 is the major structure of the substrate 110 made of glass fiber enforced resin which can be chosen from epoxy resin, PI (Polyimide), BT (Bismaleimide Trazine) resin, FR4 resin, etc.
The copper circuitry 113 is formed on the core layer 111 where the copper circuitry 113 further includes a plurality of conductive traces formed by etching a copper foil where the copper foil went through PCB manufacture processes of dry film coating, exposing, and developing to form the conductive traces with the connecting pad 112. In this embodiment, each conductive trace has a corresponding connecting pad 112 as shown in
As shown in
The solder mask 115 covers the patterned diffusion barrier 114 and the core layer 111. The solder mask 115 has an opening 116 to expose a portion of the patterned diffusion barrier 114 on the connecting pad 112. The substrate 110 further has a bonding layer 117 formed on the portion of the patterned diffusion barrier 114 inside the opening 116. The portion of the patterned diffusion barrier 114 is aligned with the connecting pad 112. Preferably, the bonding layer 117 can be gold to enhance reliable electrical connections between the substrate 110 and the first chip 120 during wire bonding processes.
To be more specific, as shown in
In detail, the solder masks 115 and 119 are individually disposed on the top and bottom surfaces of the substrate 110 to form a protection layer to protect the conductive traces from moisture and contaminant from the environment. The solder masks 115 and 119 are also known as solder resist composed by epoxy resin and photosensitive resin. The colors of the solder mask 115 and 119 are not limited to green which also can be black, red, blue, or other colors.
As shown in
As shown in
As shown in
As shown in
As shown from
Firstly, as shown in
According to the second embodiment of the present invention, another semiconductor package having chip using copper process is illustrate in
In the present embodiment, the first chip 120 further includes a first barrier layer 224 disposed between the first semiconductor layer 122 and the first adhesive layer 123 to completely cover the backside of the first semiconductor layer 122. The first adhesive layer 123 is attached to the first barrier layer 224. The second chip 140 using copper process further includes a second barrier layer 244 disposed between the second semiconductor layer 142 and the second adhesive layer 143 to completely cover the backside of the second semiconductor layer 142.
To be more specific, preferable, the materials of the first barrier layer 224 and the second barrier layer 244 are nickel (Ni) which can be formed by wafer-level sputtering, i.e., the back surface of the copper wafer is ground to an appropriate thickness, followed by sputtering the diffusion barriers 224 and 244 on the back surfaces of the copper wafer in wafer forms, and finally, the copper wafer is diced into a plurality of individual chips where the adhesive layers 123 and 143 can be formed before or after dicing. In the present embodiment, the second semiconductor layer 142 is a thinned chip through backside grinding. The second chip 140 using copper process may be smaller than the first chip 120. In other embodiments, the first chip 120 and the second chip 140 using copper process can be identical chips with the same dimensions, functions, and structures which can be fabricated in the same wafer.
Through the disposition and complete coverage of the patterned diffusion barrier 244 on the back surface of the second semiconductor layer 142 of the second chip 140 using copper process in a multi-chips stacked package, copper ions diffused from the first copper pad 121 and the copper circuitry 124 on the active surface of the first chip 120 can effectively be blocked by the second barrier layer 224 and the first barrier layer 224 (or the patterned diffusion barrier 114) and to be constrained within the first chip 120. The copper ions diffused from the second copper pad 141 and the copper circuitry 144 on the active surface of the second chip 140 using copper process can effectively be blocked by the second barrier layer 224 to be constrained within the second chip 140 using copper process. The copper ions diffused from the copper circuitry 113 of the substrate 110 can effectively be blocked within the substrate 110 by the patterned diffusion barrier 114. Therefore, copper ion contamination between stacked chips in a multi-chip stacked package can effectively be avoided to enhance product reliability.
The above description of embodiments of this invention is intended to be illustrative but not limited. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure which still will be covered by and within the scope of the present invention even with any modifications, equivalent variations, and adaptations.
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|U.S. Classification||257/692, 257/E23.072, 257/751, 257/E23.025|
|International Classification||H01L23/49, H01L23/498|
|Cooperative Classification||H01L24/73, H01L2224/48644, H01L2924/181, H01L2224/48844, H01L2924/00014, H01L2224/04042, H01L2224/48847, H01L2224/48647, H01L24/45, H01L2224/73265, H01L2224/45147, H01L2924/10253, H01L2224/83856, H01L2224/48227, H01L2224/83101, H01L2224/48145, H01L2924/14, H01L2924/01078, H01L2924/15311, H01L23/49866, H01L2224/32225, H01L2924/01033, H01L2924/01079, H01L2225/06506, H01L2224/484, H01L2924/01074, H01L2224/48228, H01L2224/32145, H01L24/27, H01L2224/0401, H01L2224/05647, H01L2924/01029, H01L24/05, H01L2224/85444, H01L24/29, H01L24/48, H01L2924/014, H01L25/0657, H01L2924/01005, H01L23/498, H01L2224/45144, H01L2924/01013, H01L2924/01014, H01L2924/10329, H01L2224/2919, H01L2924/01028, H01L2225/0651, H01L2224/274, H01L2924/01082|
|European Classification||H01L23/498M, H01L23/498, H01L24/48, H01L25/065S, H01L24/05|
|Dec 29, 2009||AS||Assignment|
Owner name: POWERTECH TECHNOLOGY INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSU, HUNG-HSIN;HSU, CHIN-MING;HSU, JUI-CHING;REEL/FRAME:023715/0018
Effective date: 20091215
|Jul 16, 2015||FPAY||Fee payment|
Year of fee payment: 4