US 8214788 B2 Abstract Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.
Claims(24) 1. One or more computer-readable storage media storing computer-executable instructions which when executed by a computer cause the computer to perform a method, the method comprising:
receiving semiconductor chip design information, the semiconductor chip design information comprising substrate profile information indicating electrical characteristics of a multi-layer substrate over or under which a circuit design is to be implemented;
computing parameters for an approximation of the multi-layer substrate's contribution to a Green's function at one or more frequencies of interest;
generating a representation of the multi-layer substrate's contribution to the Green's function using the computed parameters;
computing impedance values for signal-wire segments in the circuit design using the representation of the multi-layer substrate's contribution to the Green's function; and
outputting the impedance values.
2. The one or more computer-readable media of
3. The one or more computer-readable media of
4. The one or more computer-readable media of
5. The one or more computer-readable media of
6. The one or more computer-readable media of
7. The one or more computer-readable media of
8. The one or more computer-readable media of
receiving second circuit design information, the second circuit design information comprising information indicative of a second geometric layout of at least signal-wire segments and ground-wire segments in a second circuit design; and
reusing the parameters for the approximation of the multi-layer substrate's contribution to the Green's function to compute impedance values for the signal-wire segments in the second circuit design.
9. The one or more computer-readable media of
10. The one or more computer-readable media of
11. The one or more computer-readable media of
12. The one or more computer-readable media of
13. A method, comprising:
with a computer,
receiving semiconductor chip design information, the semiconductor chip design information comprising substrate profile information indicating electrical characteristics of a multi-layer substrate over or under which a circuit design is to be implemented;
computing parameters for an approximation of the multi-layer substrate's contribution to a Green's function at one or more frequencies of interest;
generating a representation of the multi-layer substrate's contribution to the Green's function using the computed parameters;
computing impedance values for signal-wire segments in the circuit design using the representation of the multi-layer substrate's contribution to the Green's function; and
outputting the impedance values.
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receiving second circuit design information, the second circuit design information comprising information indicative of a second geometric layout of at least signal-wire segments and ground-wire segments in a second circuit design; and
reusing the parameters for the approximation of the multi-layer substrate's contribution to the Green's function to compute impedance values for the signal-wire segments in the second circuit design.
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Description This application claims the benefit of U.S. Provisional Application No. 61/034,978 entitled “High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-Layer Conducting Substrate” filed Mar. 8, 2008, and U.S. Provisional Application No. 61/053,660 entitled “High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multi-Layer Conductive Substrate” and filed May 15, 2008, both of which are hereby incorporated herein by reference. This application pertains generally to the field of analyzing the electrical characteristics of circuit designs. For example, embodiments of the disclosed technology can be used to perform impedance extraction for circuit layouts (including layouts with intentional inductors) in the presence of a multi-layer substrate (e.g., as part of a physical verification process). As VLSI technology continues to scale, the number of wires in an integrated circuit, as well as the impact of the wires on circuit delay, noise, and power dissipation, increases rapidly. Hence, impedance extraction techniques that are computationally efficient as well as reasonably accurate are desired. However, interconnect impedance extraction presents a challenging task owing to the sheer size of the problem, both in terms of computation time and required memory. The complexity of the extraction problem is further compounded as lithography scaling enables faster transistors, driving maximum signal propagation frequencies on interconnects into the range of 20-100 GHz. In this frequency regime, it is desirable to analyze the effect on interconnect circuit parameters arising from the presence of complex substrate structures underneath or over the interconnect layers. The underlying physics includes, for example, transient currents in interconnects that are the sources of time-varying magnetic fields, which in turn induce currents in other interconnects as well as eddy currents in the lossy substrate. The presence of these eddy currents modifies the impedance matrix of the interconnects. At high frequencies, the effect of a low resistivity substrate on interconnect impedance can be a matter of significant concern. Often, a very high-resistivity (˜1000 Ω−cm) substrate is used (underlying a low-resistivity surface layer for active devices) in radio-frequency or mixed-signal ICs in order to substantially decrease the importance of substrate eddy currents. However, low-resistivity substrates continue to be used for latch-up avoidance. Hence, in order to efficiently and accurately compute the impact of the multi-layer substrate on interconnect impedance, it is desirable to use a parasitic extraction methodology that incorporates this effect. In general, conventional interconnect extraction tools are too expensive, in terms of computation time and/or memory, to handle this problem. For example, with the industry standard tool FastHenry, the substrate must be specified as an explicit conductive layer(s) demanding several thousand filaments at high frequencies. The resulting linear system is rapidly overwhelmed by the size requirements related to the partitioning of the substrate, even for single-layer substrate media. This constitutes orders of magnitude overhead in computation time and memory requirements, even for the simplest interconnect configurations. Accordingly, improved methods for performing interconnect impedance extraction in the presence of a multi-layer conductive substrate are desired. Disclosed below are representative embodiments of methods, apparatus, and systems for performing interconnect impedance extraction in the presence of a multi-layer conductive substrate. For example, embodiments of the disclosed technology comprise computationally efficient methods to accurately compute the frequency-dependent impedance of VLSI interconnects in the presence of multi-layer conductive substrates. The disclosed methods, apparatus, and systems should not be construed as limiting in any way. Instead, the present disclosure is directed toward all novel and nonobvious features and aspects of the various disclosed embodiments, alone and in various combinations and subcombinations with one another. The methods, apparatus, and systems are not limited to any specific aspect or feature or combination thereof, nor do the disclosed embodiments require that any one or more specific advantages be present or problems be solved. In one disclosed embodiment, semiconductor chip design information is received. The semiconductor chip design information comprises substrate profile information indicating electrical characteristics of a multi-layer substrate over or under which a circuit design is to be implemented. Parameters are computed for an approximation of the multi-layer substrate's contribution to a Green's function at one or more frequencies of interest. A representation is generated of the multi-layer substrate's contribution to the Green's function using the computed parameters. Impedance values are computed and output for signal-wire segments in the circuit design using the representation of the multi-layer substrate's contribution to the Green's function and using geometrical information about the circuit design (e.g., the impedance values can be stored as an impedance matrix in volatile or nonvolatile computer memory). In some implementations, the signal-wire segments in the circuit design can comprise signal-wire segments for an intentional inductor. Furthermore, in certain implementations, the parameters for the approximation of the multi-layer substrate's contribution to the Green's function can be computed for a plurality of frequencies of interest. The parameters of the approximation can be computed, for example, by fitting a non-linear least squares problem (e.g., using a variable projection technique). In some implementations, circuit design information is also received. The circuit design information can comprise information indicative of a geometric layout of at least signal-wire segments and ground-wire segments in the circuit design. In particular implementations, the circuit design can be a first circuit design, the circuit design information can be first circuit design information, and the geometric layout can be a first geometric layout. In such implementations, second circuit design information can be received, where the second circuit design information comprises information indicative of a second geometric layout of at least signal-wire segments and ground-wire segments in a second circuit design. In addition, the parameters for the approximation of the multi-layer substrate's contribution to the Green's function can be reused to compute impedance values for the signal-wire segments in the second circuit design. In certain implementations, the circuit design can be modified based at least in part on the computed impedance values. In some implementations, a netlist representative of electrical characteristics of the circuit design and comprising the impedance values can be generated. For example, the circuit design can include an intentional inductor, and the netlist can comprise information about a resistance part and a reactance part of the electrical characteristics exhibited by the intentional inductor. In some implementations, the impedance values comprise mutual impedance values and self impedance values. In another embodiment disclosed herein, semiconductor chip design information is received. The semiconductor chip design information comprises substrate profile information for a substrate over or under which a circuit design is to be implemented. A representation of electrical effects of the substrate at an operating frequency of interest is generated and stored. The representation of this embodiment represents the electrical effects of the substrate as a combined effect of a linear combination of complex exponentials. In particular implementations, the complex exponentials include unknown parameters, which can be computed using a non-linear least squares fitting technique. Further, the complex exponentials can correspond to images in a vector potential formulation caused by source magnetic dipoles. In some implementations, the substrate has multiple layers. In certain implementations, representations can be generated and stored for multiple other operating frequencies of interest. In further implementations, layout information indicative of at least signal-wire segments in a circuit design is received. In these implementations, impedance values for the signal-wire segments in the circuit design can be computed using the representation of the electrical effects of the substrate at the operating frequency of interest and stored. In another embodiment disclosed herein, layout information indicative of at least signal-wire segments in a circuit design is received. At least one signal-wire segment is identified as having a length that exceeds a transverse distance to a nearest neighboring return path by more than a threshold amount (e.g., 20 times). A first impedance extraction technique is performed for the at least one signal-wire segment identified. The first impedance extraction technique generates a first representation of impedance effects in the circuit design. A second impedance extraction technique is performed for other signal-wire segments in the circuit design. The second impedance extraction technique generates a second representation of the substrate effect on impedance in the circuit design. In this embodiment, the first impedance extraction technique and the second impedance extraction technique both account for electrical effects caused by a multi-layer substrate. Furthermore, the first impedance extraction technique is computationally more efficient but less accurate than the second impedance extraction technique. In certain implementations, the first representation is refined using the second representation to generate a complete representation of the impedance effects in the circuit design. The first impedance extraction technique performed in this embodiment can use an approximation of a two-dimensional Green's function and the second impedance extraction technique can use an approximation of a three-dimensional Green's function. Furthermore, in particular implementations, both the first impedance extraction technique and the second impedance extraction technique do not represent the multi-layer substrate as a plurality of filaments. In another disclosed embodiment, layout information indicative of at least signal-wire segments in a circuit design is received. Substrate profile information indicative of electrical characteristics of a substrate (e.g., a multi-layer substrate) over which the circuit design is to be implemented is also received. An impedance extraction technique is performed using the layout information and the substrate profile information. In this embodiment, the impedance extraction technique generates a plurality of impedance values for the signal-wire segments, but does not represent the substrate as a plurality of filaments during impedance extraction. A representation of electrical characteristics of the circuit design is generated. The representation can be, for example, a netlist that includes the impedance values. In certain implementations, the impedance extraction is performed using an approximation of a Green's function in the presence of the substrate. The Green's function can be due to a magnetic dipole. Furthermore, in some implementations, the impedance extraction can be performed using a representation of the substrate that comprises a superposition of complex exponentials. The representation of the electrical characteristics of the circuit design is a netlist that includes the impedance values. Embodiments of the disclosed methods can be performed by software stored on one or more tangible computer-readable media (e.g., one or more optical media discs, volatile memory components (such as DRAM or SRAM), or nonvolatile memory or storage components (such as hard drives)) and executed on a computer. Such software can comprise, for example, an electronic-design-automation (“EDA”) synthesis or verification tool. Such software can be executed on a single computer or on a networked computer (e.g., via the Internet, a wide-area network, a local-area network, a client-server network, or other such network). Additionally, any circuit description, design file, data structure, data file, intermediate result, or final result (e.g., a portion or all of a Spice or Spice-type netlist having impedance information) created or modified using any of the disclosed methods can be stored on a tangible computer-readable storage medium (e.g., one or more optical media discs, volatile memory or storage components (such as DRAM or SRAM), or nonvolatile memory or storage components (such as hard drives)). Furthermore, any of the software embodiments (comprising, for example, computer-executable instructions for causing a computer to perform any of the disclosed methods) or circuit descriptions, design files, data structures, data files, intermediate results, or final results created or modified by the disclosed methods can be transmitted, received, or accessed through a suitable communication means. The foregoing and other objects, features, and advantages of the invention will become more apparent from the following detailed description, which proceeds with reference to the accompanying figures. I. General Considerations Disclosed below are representative embodiments of methods, apparatus, and systems for extracting impedance in a circuit design. The disclosed methods, apparatus, and systems should not be construed as limiting in any way. Instead, the present disclosure is directed toward all novel and nonobvious features and aspects of the various disclosed embodiments, alone and in various combinations and subcombinations with one another. The methods, apparatus, and systems are not limited to any specific aspect or feature or combination thereof, nor do the disclosed embodiments require that any one or more specific advantages be present or problems be solved. More specifically, embodiments of computationally efficient methods to accurately compute the frequency-dependent impedance of VLSI interconnects in the presence of multi-layer conductive substrates are described. In certain embodiments, the resulting accuracy (e.g., errors less than 2%) and CPU time reduction (e.g., more than an order of magnitude) are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the short distances relevant to VLSI interconnects. These embodiments permit the evaluation of the self and mutual impedance of multiconductor current loops, including substrate effects, in terms of easily computable analytical expressions that involve their relative separations and the electromagnetic parameters of the multi-layer substrate. Although the operations of some of the disclosed methods are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed methods can be used in conjunction with other methods. Additionally, the description sometimes uses terms like “determine” and “generate” to describe the disclosed methods. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms may vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art. The disclosed technology can be used, for example, to analyze impedance effects on digital, analog, or mixed-signal integrated circuit designs before the circuits are physically implemented. The disclosed technology can be applied, for example, to any circuit design or situation where wire impedance effects may affect signal delay or signal integrity or power consumption. For instance, the disclosed embodiments can be used to analyze the high-frequency behavior of wires or interconnect in an integrated circuit design (e.g., an application-specific integrated circuit (“ASIC”), a programmable logic device (“PLDs”) such as a field programmable gate array (“FPGA”), a system-on-a-chip (“SoC”), or a microprocessor) or in the off-chip interconnect at the board or package level (e.g., multilayered packages or printed circuit boards). The disclosed technology can also be used for the analysis of intentional inductors or other passive devices (e.g., intentional inductor or passive devices in an integrated circuit design, off-chip circuitry, or at the package level). As more fully explained below, embodiments of the disclosed methods can be performed by software stored on one or more tangible computer-readable media (e.g., one or more optical media discs, volatile memory or storage components (such as DRAM or SRAM), or nonvolatile memory or storage components (such as hard drives)) and executed on a computer. Such software can comprise, for example, an electronic-design-automation (“EDA”) synthesis tool. Such software can be executed on a single computer or on a networked computer (e.g., via the Internet, a wide-area network, a local-area network, a client-server network, or other such network). The software embodiments disclosed herein can be described in the general context of computer-executable instructions, such as those included in program modules, which can be executed in a computing environment on a target real or virtual processor. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The functionality of the program modules may be combined or split between program modules as desired in various embodiments. Computer-executable instructions for program modules may be executed within a local or distributed computing environment. For clarity, only certain selected aspects of the software-based implementations are described. Other details that are well known in the art are omitted. For example, it should be understood that the disclosed technology is not limited to any specific computer language, program, or computer. Additionally, any circuit description, design file, data structure, data file, intermediate result, or final result (e.g., a portion or all of a Spice or Spice-like netlist or subcircuit representation comprising impedance information as a function of frequency, data indicative of parameters used with the Green's function approximations, a portion or all of a Green's function representation (such as a Green's function matrix), a portion or all of a impedance matrix, or a portion or all of circuit design information) created or modified using any of the disclosed methods can be stored on a tangible computer-readable storage medium (e.g., one or more optical media discs, volatile memory or storage components (such as DRAM or SRAM), or nonvolatile memory or storage components (such as hard drives)). Furthermore, any of the software embodiments (comprising, for example, computer-executable instructions for causing a computer to perform any of the disclosed methods) can be transmitted, received, or accessed through a suitable communication means. Similarly, any circuit description, design file, data structure, data file, intermediate result, or final result (e.g., a portion or all of a Spice or Spice-like netlist comprising impedance information, data indicative of parameters used with the Green's function approximations, a portion or all of a Green's function representation (such as a Green's function matrix), a portion or all of a impedance matrix, or a portion or all of circuit design information) created or modified using any of the disclosed methods can be transmitted, received, or accessed through a suitable communication means. Such suitable communication means include, for example, the Internet, the World Wide Web, an intranet, software applications, cable (including fiber optic cable), magnetic communications, electromagnetic communications (including RF, microwave, and infrared communications), electronic communications, or other such communication means. Such communication means can be, for example, part of a shared or private network. Moreover, any circuit description, design file, data structure, data file, intermediate result, or final result (e.g., a portion or all of a Spice or Spice-like netlist comprising impedance information, data indicative of parameters used with the Green's function approximations, a portion or all of a Green's function representation (such as a Green's function matrix), a portion or all of a impedance matrix, or a portion or all of circuit design information) produced by any of the disclosed methods can be displayed to a user using a suitable display device (e.g., a computer monitor or display). Such displaying can be performed as part of a computer-implemented method of performing any of the disclosed methods. The disclosed methods can be used at one or more stages of an overall synthesis scheme. For example, any of the inductance extraction methods disclosed can be used during physical synthesis (e.g., during the physical verification process) in order to evaluate and improve a circuit design. Circuits manufactured from such circuit designs are also considered to be within the scope of this disclosure. For example, after synthesis is performed using embodiments of the disclosed methods, the resulting circuit design can be fabricated into an integrated circuit using known microlithography techniques. The disclosed technology is particularly suitable for verifying the correctness of a circuit design. Certain embodiments of the disclosed methods are used to compute impedance effects in a computer simulation, physical verification tool, or other electronic design automation (“EDA”) environment wherein the impedance in a circuit representation is analyzed. For example, the disclosed methods typically use circuit design information (for example, a netlist, HDL description (such as a Verilog or VHDL description), GDSII description, Oasis description, or the like) stored on computer-readable storage media. For presentation purposes, however, the present disclosure sometimes refers to the circuit and its circuit components by their physical counterpart (for example, wires, conductors, paths, and other such terms). It should be understood, however, that any such reference not only includes the physical components but also representations of such circuit components as are used in simulation, physical verification, or other such EDA environments. With reference to The computing environment may have additional features. For example, the computing environment The storage The input device(s) The communication connection(s) The various impedance extraction methods disclosed herein can be described in the general context of computer-readable media. Computer-readable media are any available media that can be accessed within or by a computing environment. By way of example, and not limitation, with the computing environment II. Two-Dimensional Treatment of VLSI Interconnect Impedance Extraction in the Presence of Multi-Layer Conductive Substrate A. Introduction In this disclosure, embodiments for computing the frequency-dependent impedance of VLSI interconnects in the presence of multi-layer conductive substrates are described. The disclosed embodiments are accurate, yet computationally inexpensive compared to conventional methods. For VLSI interconnect impedance extraction, certain embodiments of the disclosed technology rely on a loop impedance formalism, which leads to the correct physical behavior of closed on-chip currents. In order to describe current loop interactions, and in certain embodiments of the disclosed technology, the Green's function for a magnetic dipole in the presence of a multi-layer substrate is computed. This computation is discussed in Section II.C. below. Further, this Green's function describes the two-dimensional problem in the quasi-static approximation. In certain embodiments, up to the maximum frequency of interest for VLSI technology (100 GHz), a quasi-static computation of the magnetic vector potential is justified since the minimum wavelength (>1.5 mm) is much larger than the relevant physical transverse dimensions of the interconnect geometry. However, the skin depth of the substrate layers is often of the same order as the wavelength. Hence, the quasi-static assumption used in this disclosure is validated by comparison with a full-wave field solver ( In brief, exemplary embodiments using analytical formulations to compute the loop impedance matrix for general VLSI interconnect configurations in the presence of a multilayer conductive substrate are described. Particular implementations of these embodiments are suitable for system level extraction of Manhattan interconnects. B. Background The two-dimensional quasi-static Green's function for an elementary excitation consisting of a single monopole current, in the presence of a stratified substrate, is discussed in A. Weisshaar et al., “Accurate closed-form expressions for the frequency-dependent line parameters of on-chip interconnects on lossy silicon substrate,” The function g 1. Computation of the Substrate Green's Function A straight-forward approach to evaluating the substrate Green's function is to use numerical integration techniques. However, this approach is computationally too expensive to handle complex VLSI interconnect configurations typically consisting of millions of wires. Alternative approaches to compute this Green's function, as discussed below, approximate the term g 2. Approximate Complex Image Method In this approach, g
Keeping only the first term in the series expansion, expression (3) becomes:
The expression in (7) is analytically integrable. The first exponential term arises from the source (line current) at the point (0, z′), while the second one represents the effect of an opposing current (negative sign) lying at the point
3. Rational Function Fit Method (RFFM) An alternative method for evaluating the substrate Green's function involves approximating it by a rational function, which can be integrated analytically. The rational function fit in the complex λ plane can be uniquely defined in terms of a set of K pole-residue pairs:
The pole-residue extraction demands a non-linear least-square fit for every point (x,z) in space and is computationally expensive. Achieving accuracy within 1-2% using this technique often requires a number of poles K of the order of 100 for each (x,z) point. The number of such points (x,z) must also be large. For these reasons, even though this methodology can be applied for parasitic extraction of interconnects, it is computationally expensive and memory intensive. 4. Discrete Complex Images Method (“DCIM”) The DCIM can be considered as an extension to the approximate complex image method, which approximates g C. Green's Function for a Magnetic Dipole in the Presence of a Conductive Substrate The magnetic monopole Green's function leads to a PEEC approach that has an unphysical long distance behavior with the inductance per unit length decaying logarithmically with wire separation, instead of the correct power law decay associated with closed current approaches. See, e.g., A. Ruehli, “Inductance calculations in a complex integrated circuit environment,” The end result is dense and non-diagonal-dominant impedance matrices. In this disclosure, embodiments of the disclosed technology involve computing physically measurable quantities (e.g., in terms of loop quantities) that result in sparse impedance matrices. One exemplary embodiment (referred to herein as the exemplary 2D impedance extraction embodiment) is based on a Green's function corresponding to a closed elementary loop: a magnetic dipole. The Green's function in this embodiment has the correct long distance behavior for the magnetic field and the correct low frequency behavior corresponding to magneto-quasi-static phenomena. It can be verified that it is the quasi-static limit of the Sommerfeld layered-media Green's function. The block diagrams Typical semi-conductor chip substrates have two or three layers with different resistivity values. Hence, the expressions presented so far encompass the relevant scenarios to characterize realistic process configurations. For substrates consisting of more than three layers, it is straightforward to find the extensions of Expressions (15) and (16). Next, an example of an accurate analytical approximation to the dipole Green's function in the presence of multi-layer substrates is described. The described example is not to be construed as limiting, however, as the resulting approximation can be varied from implementation to implementation without departing from the underlying principles of the disclosed technology. 1. Modified Discrete Complex Images Method In Expressions (13), (14), the term containing g
This alternative functional representation of g
Physically, the approximation (19) has a similar interpretation to that of the discrete complex images method. The kth term in the approximation constitutes an image of the dipole current source at a complex distance α From (19) it is clear that α The number of images, K, determines the computational expense in finding the set of images (α Inserting (19) into (13) and (14), the following analytical expressions can be obtained for the Green's functions: 2. Accuracy of the Modified Discrete Complex Images Method and Comparison with Other Methods Graphs The Monte-Carlo results for typical 2-layer and 3-layer substrates are shown in graphs Although several techniques have been proposed to implement DCIM to approximate the 3D substrate Green's function, it still remains a challenging task. To implement DCIM for the 2D quasi-static Green's function, the Variable Projections (VARPRO) method can be used, which can be used for exponential fitting problems. The sampling points in λ are user-defined, giving wide latitude for non-uniform sampling to account for the rapid variations in g In comparison with RFFM, one advantage of the exemplary 2D impedance extraction embodiment is in terms of computation cost. Computing the Green's function G(x,z,x′,z′) using RFFM involves evaluation of the pole-residue pairs in Expression (8) for each pair of points (x,z) and (x′,z′). Impedance extraction of a general interconnect configuration requires numerous computations of G, at coordinates that are not known a priori. In Table II, the computation time is shown for one element of the loop impedance matrix shown in Expression (33). Since the impedance matrix for a realistic interconnect configuration may require hundreds of such computations (the interconnect shown in Section II.E with 15 filaments per conductor requires 15
D. Interconnect Impedance Computation Using the Green's Function for a Magnetic Dipole In this section, computing interconnect impedances for a set of interacting conductors in the presence of a multi-layer conductive substrate is discussed. Because embodiments of the disclosed technology concern a two-dimensional scenario, the conductors are assumed to have a common length, L. The general impedance extraction problem is shown schematically in diagram 1. Magnetic Vector Potential Due to a Finite Size Conductor Loop The Green's functions in Expressions (20) and (21) give the magnetic vector potential at the point (x,z) due to a unitary magnetic dipole (p=1) located at (0, z′). In the general case, the vector potential at (x,z) due to a finite size magnetic dipole is obtained by integrating the Green's function times the source dipole moment density (P(x′,z′)) over the co-ordinates of the source:
It has been shown that when the separations between the source (x′,z′) and the destination (x,z) is larger than roughly 5 times the diameter of the source dipole (a in the wire configuration shown in schematic block diagram However, for impedance extraction, it is desirable to accurately compute the vector potential when separations are of the order of, or smaller than, the diameter of the source dipole. In this scenario, the dipole approximation is no longer valid and, in one exemplary embodiment, the source is replaced by a continuous distribution of magnetic dipoles along the line joining the two ends of the source current loop. As shown by the configuration in schematic block diagram 2. Impedance Extraction of Single-Filament Conductor Loops In this section, mutual impedance computation between a source magnetic dipole and the current loop formed by a pair of conductors with common length L is discussed. The mutual inductance, per unit length, can be computed as: When computing the self-inductance of a loop, the affected conductor loop coincides with the source loop. In such cases, when the center-to-center distance between two conductors is zero, the preferred way to compute mutual impedance is to use the geometric mean distance (GMD). The GMD of a rectangular cross-section conductor with respect to itself is given by:
3. Impedance Extraction of Realistic Multiple-Filament Conductor Bundle In case of wide/thick conductors, with cross-sectional dimensions comparable to the skin depth at the frequency of concern, the computation is performed in one embodiment by dividing each conductor into two or more filaments. Moreover, a signal wire may sometimes have more than one nearby ground wire acting as its return path. In certain embodiments, the collection of a signal wire (decomposed into multiple filaments, f In particular embodiments, the first step in computing the impedance of such bundles composed of multiple loops is to compute the loop impedance matrix. The diagonal elements of the matrix, Z
E. Results In this section, the accuracy and computational efficiency of the exemplary 2D impedance extraction embodiment is demonstrated. The exemplary embodiment is based on the 2D magneto-quasi-static assumption, in the presence of a multi-layer conductive substrate. It should be noted that the impedance computation involves integrals of a highly oscillatory Green's function, shown in Expression (13), and a further integral over the source dipole, shown in Expression (25). Both integrals may have significant cancellations depending on the interconnect geometry. Hence, it is not feasible to directly estimate the error in the impedance computation from the error in the Green's function. To verify the accuracy of the exemplary 2D impedance extraction embodiment, Section II.E.1 shows comparisons with the 3D electromagnetic field solver FastHenry, as well as the commercial full-wave field solver HFSS, for a wide range of realistic VLSI interconnect configurations. The computational efficiency of the exemplary 2D impedance extraction embodiment, due to the analytical expressions for the substrate Green's function, is shown in Section II.E.2 through comparisons with 3D (FastHenry) and with 2D PEEC based computations. Note that in all the examples shown, each conductor is discretized into the same number of filaments with the exemplary embodiment as that with FastHenry or PEEC, in order to capture skin and proximity effects. 1. Accuracy When wide and thick conductors are discretized into multiple filaments to capture skin and proximity effects, the relative positions of the filaments that comprise the conductor loops will not conform to the discrete positions occupied by conductors on individual metal layers. As an example of such a scenario, graph Graphs Next, the network Z-parameter (Z In subsequent paragraphs, the accuracy of the exemplary 2D impedance extraction embodiment disclosed herein is compared with FastHenry for several typical interconnect geometries. Graphs 2. Computational Efficiency The exemplary 2D impedance extraction embodiment disclosed herein is based on analytical expressions for the substrate Green's function, wherein the substrate boundary conditions are implicit. The only filaments that need to be considered in the solution are those corresponding to the interconnects themselves. On the other hand, both FastHenry and the 2D PEEC method used for comparison, are based on the free space Green's function. Hence, the substrate layers are included as explicit conductors. At relevant high frequencies, these layers are typically discretized into a large number of filaments, as shown below, resulting in a large linear system of equations. Table III compares the computation time with FastHenry to that with the exemplary 2D impedance extraction embodiment disclosed herein. The number of filaments for representing the substrate in FastHenry is chosen by progressively increasing the number of segments in the substrate layers until the result stabilizes. It is observed that the accuracy levels achieved with the exemplary 2D impedance extraction embodiment are accompanied by almost two orders of magnitude reduction in computation time. Since FastHenry is applicable to general 3D interconnect geometries, the exemplary 2D impedance extraction embodiment is compared with a 2D PEEC-based computation in Table IV. The number of filaments in the substrate for 2D PEEC are selected to ensure that the filament cross-sections are less than the skin depth at the specified frequency. As the thickness of the low-resistivity top layer of the substrate increases to a few μm, the computation cost with 2D PEEC increases substantially due to the larger number of filaments required. On the other hand, with the exemplary 2D impedance extraction embodiment, a change in the substrate layer thickness only demands evaluation of a new set of substrate images while the impedance computation cost remains constant. Hence, Table IV shows orders of magnitude improvement in computational efficiency by using the exemplary 2D impedance extraction embodiment disclosed herein. Finally, the speedup observed from Monte-Carlo simulations on a large number of randomly generated interconnect geometries are shown in
Embodiments of general methodologies for self and mutual impedance extraction of VLSI interconnects, in two dimensions, in the presence of a multi-layered conductive substrate have been described. Many of the exemplary approaches are based on the Green's function for a magnetic dipole, which naturally leads to current loops giving the correct physical representation for on-chip conductor currents. The relevant regimes of distances and frequencies are also covered. The resulting exemplary expressions (e.g., (20), (21), (25), (29), (31), (32), (33), (35)), as well as those shown in Section II.F below, are simple analytical expressions depending on parameters that can be easily extracted from real exponential least-square fits to known formulae. The suitability of the described embodiments for massive extraction problems is self-evident. For example, embodiments of the disclosed technology are significantly more accurate than the approximate complex image method, more efficient than the RFFM, and much simpler to realize than the DCIM. In addition, a continuous dipole distribution can be employed to compute the magnetic interaction between conductor loops at very small distances from the source current distribution. This approximation allows one to directly apply the dipole Green's function to self and mutual impedance computation. The results show that this methodology can be applied to accurately compute the impedance of realistic wire configurations in cases where the substrate is found to significantly impact interconnect impedance. The saving in computation time as compared to the electromagnetic field solver, FastHenry, is almost two orders of magnitude. F. Analytical Expressions for A In the following equations, the expressions for the freespace terms, A
where, in the previous three equations, A. Introduction For high-frequency VLSI interconnect impedance extraction, current loops formed by a signal wire and its parallel return paths which carry currents in the opposite direction can be considered. The collection of a signal wire and its return paths can be partitioned along their length to form bundles, as shown in the schematic diagram The physical equivalent of a current loop describing on-chip interconnect currents, as shown above, is a magnetic dipole. These magnetic dipoles constitute the sources of magnetic fields that interact with other conductors, and are described below. For on-chip conductors in VLSI circuits, the relevant length scales for conductor bundles (few hundred micrometers) are much smaller than the wavelength at the highest frequency of concern (few millimeters at 100 GHz). Hence, a quasi-static description of the magnetic field is appropriate (this quasi-static assumption is validated below with the comparisons of the results from the exemplary method described herein with results from full-wave field solvers). 1. Vector Potential Green's Function in Integral Form Because on-chip conductors are confined to discrete metal layers in the x-y plane, the current loops they form are planar, although they may have arbitrary orientations, as shown by diagram Consider two opposite currents Iŷ and −Iŷ in the x-y plane, centered at (x′,y′,z′) and separated by an infinitesimal distance a, lying above a multi-layered substrate, as shown in
2. Discrete Complex Images for the Substrate The effect of multi-layered substrate media on the vector potential field due to various sources such as 3D electric and magnetic dipoles, 2D line currents, and 2D magnetic dipoles, have been studied in the published literature. In all cases, the net field at {right arrow over (r)} due to a source located at {right arrow over (r)}′ (where both {right arrow over (r)}, {right arrow over (r)}′ are located in the region above the substrate) is obtained in similar form as shown above: the sum of a primary field due to the source in free space and a secondary field due to the substrate. It is noteworthy that although the particular expressions for the two terms may vary depending on the source, the coefficient χ Although analytical expressions are well-known for the primary field component of the substrate Green's function (38), analytical computation of the entire integral expression is hampered by the coefficient χ Using the above approximation, and noting that the exponentials in Expression (41) readily combine with those in the integrand of Expression (38), the net field in the presence of the substrate takes the general form: 3. Analytical Green's Function for Magnetic Dipole in Free Space Now, for a single current Iŷ in free space (no substrate), the vector potential Green's function in the quasi-static domain is well-known:
Recognizing this simple form of the vector potential Green's function for on-chip interconnect currents in free space, and noting that in the presence of a substrate the Green's function can be approximated by a linear combination of the free space Green's function for the dipole source and that for each of its complex images, the multiple dimension integrals of the kind shown in Expression (38) can be avoided. Convenient analytical expressions can thus be obtained for the substrate Green's function, as shown in the next section. B. An Exemplary Impedance Extraction Method for General VLSI Interconnects in Presence of Multi-Layer Substrate 1. Analytical Magnetic Vector Potential Green's Function for a 3D Magnetic Dipole in Unbounded Space The quasi-static magnetic vector potential at {right arrow over (r)}′ due to a magnetic dipole located at a point {right arrow over (r)} in unbounded/free space (no substrate), is given by:
The vector potential Green's function (G Due to the choice of co-ordinates, the y-component of {right arrow over (p)} is zero in Expression (37). Hence,
Moreover, the cross product in Expression (47) implies that G From the observations above, the vector potential Green's function (in the x-y plane) at a point {right arrow over (r)}=(x,y,z), due to a unit magnetic dipole source located at a point r′=(x′,y′,z′) in unbounded space, can be written as:
Substituting (37) in (47), and with |{right arrow over (p)}|=1, we get:
2. Analytical Magnetic Vector Potential Green's Function for a 3D Magnetic Dipole in the Presence of a Multi-layer Substrate For the vector potential Green's function in the presence of a multi-layer substrate, the modified discrete complex images method explained in Section III.A.2 above can be used to represent the substrate as a series of images of the source dipole (see diagram _{k}/γ_{1}), and multiplying by the linear coefficient β_{k}, thus:
3. Impedance for a Finite Current Loop The Green's function shown above gives the vector potential due to a unit magnitude dipole source located at a point {right arrow over (r)}′=(x′,y′,z′). To find the vector potential at any point {right arrow over (r)}=(x,y,z) due to a finite size current loop, the finite loop can be considered as a superposition of infinitesimally small point sources in the area occupied by the current loop, each having a loop area dx′×dy′ and carrying current I. The co-ordinates of the source (x′,y′,z′) span the rectangular area shown in
For impedance extraction of VLSI interconnects, two-conductor loops are considered as shown in the schematic block diagram For a victim conductor oriented along ŷ extending from (x
All the integrals shown above can be evaluated in closed form. The exact expressions for M
In the presence of a multi-layer substrate, in Expression (56) must be replaced by from Expression (54) to get: Besides Manhattan interconnects which are always inclined at right angles, we are also interested in computing the impedance of inductors, which may comprise conductor segments inclined at arbitrary angle θ. In this case, we choose a co-ordinate system that aligns the source current loop to ŷ. For the victim conductor extending from (x
C. Exemplary Implementations of Impedance Extraction Methodology for VLSI Interconnects 1. Modified Discrete Complex Images for Multi-layer Substrates As explained before, the modified discrete complex images approximation, shown in Expression (30), allows one to represent the effect of the substrate as the combined effect of a series of images of the source magnetic dipole. The advantage of this representation is evident from the convenient analytical expressions for the mutual impedance between conductor currents that have been derived in Section III.B. In Section II above, it was shown that a non-linear least squares fitting approach to compute the complex image parameters, with α a. Variable Projection Method for Non-Linear Least Squares Fitting The search for an accurate set of images (α b. Complex Images Using Variable Projection Algorithm In exemplary embodiments of the disclosed technology, the VP algorithm described above is applied to solve the nonlinear least squares problem to determine the complex images in terms of the best fit parameters α In general, increasing the number of images improves the accuracy of the approximation, while simultaneously increasing the cost of computation. Moreover, a large number of images leads to instabilities that make it difficult to find a good approximation. In certain implementations, choosing K between 5 and 10 is sufficient for an accurate approximation and reasonable computation cost. It has always been observed that K>10 can lead to diminishing returns. It has also been found that the choice of starting values for the parameters α 2. Impedance Computation for Realistic Dimension Interconnects The expressions for self and mutual impedance shown in Section III.B are valid for conductors with uniform cross-sectional current density. For wide/thick conductors, with cross-sectional dimensions comparable to the Cu skin depth at the frequency of concern, the current density is non-uniform due to skin and proximity effects. In such cases, the computation is performed by dividing each conductor into multiple filaments such that piece-wise constant current density can be assumed for each filament. The discretization into filaments of each conductor in a bundle is shown in schematic block diagram In practice, since the loop impedance matrix shown above is large and ill-conditioned, a hierarchical technique can be employed to solve the linear system. As shown in The solution of the linear system proceeds as follows. For each sth sub-block of m D. Results In this section, the accuracy of the exemplary 3D impedance extraction method is demonstrated for a typical substrate configuration in comparison with the 3D electromagnetic field solver FastHenry, which is also based on the magneto-quasistatic (“MQS”) assumption. Note that in all the comparisons shown, each conductor is discretized into the same number of filaments when using the exemplary method as with FastHenry, to capture non-uniform current densities under skin and proximity effects. Also shown are comparisons with the commercial fullwave field solver HFSS to ascertain the validity of the MQS assumption used in the exemplary embodiments disclosed herein. Schematic block diagrams Graph IV. Exemplary Methods for Applying the Disclosed Technology In this section, exemplary methods for applying embodiments of the disclosed technology are disclosed. The disclosed methods are not to be construed as limiting, however, as aspects of the disclosed technology can be applied to an impedance extraction flow in a variety of manners. At At At At The above-described flow should not be construed as limiting in any, however, as in other exemplary embodiments, any subset of these method acts is performed. In still other embodiments, any one or more of the method acts are performed individually or in various other combinations and subcombinations with one another. At At At At At At At At At At At At At At At At At At At At V. Exemplary Network Environments for Applying the Disclosed Techniques Any of the aspects of the technology described above may be performed using a distributed computer network. Having illustrated and described the principles of the illustrated embodiments, it will be apparent to those skilled in the art that the embodiments can be modified in arrangement and detail without departing from such principles. For example, any of the disclosed techniques can be used in conjunction with or in addition to the methods described in U.S. Patent Application Publication No. 2007/0226659 filed on Feb. 8, 2007 and entitled “Extracting High Frequency Impedance in a Circuit Design Using an Electronic Design Automation Tool,” which is hereby incorporated herein by reference. In view of the many possible embodiments, it will be recognized that the illustrated embodiments are only examples and should not be taken as a limitation on the scope of the disclosed technology. Patent Citations
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