|Publication number||US8217473 B2|
|Application number||US 11/192,945|
|Publication date||Jul 10, 2012|
|Filing date||Jul 29, 2005|
|Priority date||Jul 29, 2005|
|Also published as||CN101233073A, CN101233073B, EP1919821A1, US20070128828, WO2007018955A1|
|Publication number||11192945, 192945, US 8217473 B2, US 8217473B2, US-B2-8217473, US8217473 B2, US8217473B2|
|Inventors||Chien-Hua Chen, John Bamber, Henry Kang|
|Original Assignee||Hewlett-Packard Development Company, L.P.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (46), Non-Patent Citations (1), Classifications (7), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Micro electro-mechanical system (MEMS) devices include micro-machine substrates integrated with electronic microcircuits. Such MEMS devices may form, for example, microsensors or microactuators which operate based on, for example, electromagnetic, electrostrictive, thermoelectric, piezoelectric, or piezoresistive effects. MEMS devices are fabricated on insulators or other substrates using microelectronic techniques such as photolithography, vapor deposition, and etching.
Typically, the electrical portion of a MEMS device and the mechanical portion of a MEMS device are fabricated on separate wafers and then bonded together to form the MEMS device. The bonding of the electrical and mechanical portions may be performed at either wafer level processing or at die level processing. At either wafer level processing or die level processing, solder is typically used to bond the electrical portions to the mechanical portions and to provide electrical interconnects between the electrical portions and the mechanical portions to form a MEMS device. During the soldering process, misalignment may occur due to thermal and/or mechanical shifting. This misalignment may result in reduced yields.
For these and other reasons, there is a need for the present invention.
One aspect of the present invention provides a micro electro-mechanical system (MEMS) device. The MEMS device includes an electrical wafer, a mechanical wafer, a plasma treated oxide seal bonding the electrical wafer to the mechanical wafer, and an electrical interconnect between the electrical wafer and the mechanical wafer.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
In one embodiment, plasma treated oxide seal rings 106 enclose solder interconnects 108 and portions of M-wafer 102 and E-wafer 104.
Bonding of M-wafer 102 to E-wafer 104 is implemented at wafer level or die level processing. In one embodiment, plasma treated oxide seal rings 106 bond M-wafer 102 to E-wafer 104 at room temperature such that the two wafers are aligned and locked in place. In one embodiment, plasma treated oxide seal rings 106 bond M-wafer 102 to E-wafer 104 spontaneously upon contact. In one embodiment, plasma treated oxide seal rings 106 also precisely set a gap 110 between M-wafer 102 and E-wafer 104 to a desired value.
In one embodiment, solder interconnects 108 are formed between M-wafer 102 and E-wafer 104 after plasma treated oxide seal rings 106 bond M-wafer 102 to E-wafer 104 and set gap 110 between the wafers. In one embodiment, the bonded M-wafer 102 and E-wafer 104 are annealed to reflow solder material deposited on M-wafer 102 and/or E-wafer 104 to form electrical 3D interconnects 108 between M-wafer 102 and E-wafer 104.
In one embodiment, M-wafer 102 includes micromovers or other suitable micro mechanical devices. In one embodiment, E-wafer 104 includes complimentary metal-oxide-semiconductor (CMOS) circuits or other suitable circuits for interconnecting with the micromovers to form MEMS devices, such as MEMS device 100.
Plasma treated oxide seal rings 106 can provide greatly improved alignment between M-wafer 102 and E-wafer 104 compared to solder bonding techniques. In addition, overall bond strength can be enhanced significantly over solder bonding techniques. The enhanced alignment and bond strength can provide higher process margins and higher yields during manufacturing. Plasma treated oxide seal rings 106 also enable precisely aligned 3D architectures in wafer or die integration and packaging. Furthermore, in one embodiment, hermetic packaging with interconnects is achieved with plasma treated oxide seal rings 106.
In one embodiment, seal rings 106 are treated with plasma, such as an oxygen plasma or nitrogen plasma. This plasma treatment prepares seal rings 106 for immediate bonding on contact with another SiO2 surface or another suitable surface.
M-wafer 102 and E-wafer 104 are then annealed to reflow solder 108 a. The reflowed solder 108 a a provides electrical 3D interconnects 108 between M-wafer 102 and electrical contacts 108 b of E-wafer 104. The combination of the plasma treated oxide seal rings 106 and electrical 3D interconnects 108 bond the aligned M-wafer 102 and E-wafer 104 to form MEMS device 100 illustrated in
Oxide seal rings 158 are patterned on package 153, package 155, or both package 153 and package 155 to obtain the desired bonding points and a desired gap 160. In one embodiment, the oxide seal rings 158 are then plasma treated. The face of chip 152 is aligned with the face of chip 154 and plasma treated oxide seal rings 158 are bonded upon contact. In one embodiment, device 150 is then annealed to reflow the solder to form electrical interconnects 156 between chip 152 and chip 154.
Oxide seal rings 158 are patterned on package 153, package 155, or both package 153 and package 155 to obtain the desired bonding points and a desired gap 160. In one embodiment, the oxide seal rings 158 are then plasma treated. The back of chip 152 is aligned with the face of chip 154 and plasma treated oxide seal rings 158 are bonded upon contact. In one embodiment, device 170 is then annealed to reflow the solder to form electrical interconnects 156 between chip 152 and chip 154.
Embodiments of the invention provide a low temperature plasma bond to tack the wafers or dies in place before implementing the high temperature solder reflow for forming the electrical interconnects. Embodiments of plasma treated oxide seal rings improve the alignment accuracy and substantially eliminate any misalignment due to material expansion, thermal effects, mechanical shift, etc.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
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|1||Transmittal of the International Search Report and the Written Opinion of the International Searching Authority dated Nov. 23, 2006.|
|U.S. Classification||257/414, 257/704, 257/E31.117, 257/730|
|Sep 7, 2005||AS||Assignment|
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, CHIEN-HUA;BAMBER, JOHN;KANG, HENRY;REEL/FRAME:016744/0402
Effective date: 20050729
|Jan 1, 2013||CC||Certificate of correction|
|Dec 29, 2015||FPAY||Fee payment|
Year of fee payment: 4