|Publication number||US8222139 B2|
|Application number||US 12/750,364|
|Publication date||Jul 17, 2012|
|Filing date||Mar 30, 2010|
|Priority date||Mar 30, 2010|
|Also published as||CN102208342A, CN102208342B, US20110244676, US20120258590|
|Publication number||12750364, 750364, US 8222139 B2, US 8222139B2, US-B2-8222139, US8222139 B2, US8222139B2|
|Inventors||Ming-Fa Chen, I-Ching Lin|
|Original Assignee||Taiwan Semiconductor Manufacturing Company, Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (37), Non-Patent Citations (1), Referenced by (4), Classifications (9), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This disclosure relates to integrated circuit fabrication, and more particularly, to chemical mechanical polishing (CMP) processing of a through-silicon via (TSV) and a contact plug simultaneously.
Three-dimensional (3D) wafer-to-wafer vertical stack technology seeks to achieve the long-awaited goal of vertically stacking many layers of active IC devices such as processors, programmable devices and memory devices inside a single chip to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance. One major challenge of 3D interconnects on a single wafer or in a wafer-to-wafer vertical stack is through-via that provides a signal path for high impedance signals to traverse from one side of the wafer to the other. Through-silicon via (TSV) is typically fabricated to provide the through-via filled with a conducting material that pass completely through the layer to contact and connect with the other TSVs and conductors of the bonded layers.
Currently, TSV process forming a copper via passing through a silicon substrate is combined typical IC process. When the TSV process is right after a contact process, an additional chemical mechanical planarization or polishing (CMP) process is needed to polish the excess Cu overburden to provide surface planarity. Chemical corrosion, photo-corrosion, narrow trench corrosion, and galvanic corrosion are reported to be the possible mechanisms of Cu corrosion during CMP. Galvanic corrosion (also referred to as bimetallic corrosion) occurs due to electrochemical incompatibility between two dissimilar metals that are in electrical and ionic contact. Thus, the additional Cu CMP slurry will cause galvanic corrosion to the contact plug made of tungsten (W), resulting tungsten corrosion.
The aforementioned objects, features and advantages of this disclosure will become apparent by referring to the following detailed description of the embodiments with reference to the accompanying drawings, wherein:
This disclosure provides embodiments of CMP processing of metallization structures simultaneously. Embodiments of the metallization structure are applicable in forming a contact plug, a through-silicon via (TSV) structure or others. As used throughout this disclosure, the term “through-silicon via (TSV)” refers to an opening filled with at least a conductive material passing through at least a part of a semiconductor substrate or a silicon-containing substrate. Embodiments provide the use of copper metallization in forming TSVs. As employed throughout this disclosure, copper (Cu) is intended to encompass elemental Cu as well as Cu-based alloys substantially exhibiting the electrical properties of Cu.
Reference will now be made in detail to the present embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness of one embodiment may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, apparatus in accordance with the present disclosure. It is to be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. Further, when a layer is referred to as being on another layer or “on” a substrate, it may be directly on the other layer or on the substrate, or intervening layers may also be present.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.
With reference to
In detail, the substrate 10 is typically silicon (Si), for example, a silicon substrate with or without an epitaxial layer, or a silicon-on-insulator substrate containing a buried insulator layer. The substrate 10 may also be made of gallium arsenide (GaAs), gallium arsenide-phosphide (GaAsP), indium phosphide (InP), gallium aluminum arsenic (GaAlAs), indium gallium phosphide (InGaP). The substrate 10 has a front surface 10 a (e.g., circuit side) and a back surface 10 b (e.g., non-circuit side). The IC component 200 formed in and/or on the front surface 10 a of the substrate 10 may comprise multiple individual circuit elements such as transistors, diodes, resistors, capacitors, inductors, and other active and passive semiconductor devices formed by conventional processes known in the integrated circuit manufacturing art. For example, the IC component 200 is a transistor including a gate and source/drain regions
The ILD layer 12 is formed on the front surface 10 a of the substrate 10 so as to isolate the IC component 200 from a subsequent formation of an interconnection structure. The ILD layer 12 may be a single layer or a multi-layered structure. The ILD layer 12 may be a silicon oxide containing layer formed of doped or undoped silicon oxide by a thermal CVD process or high-density plasma (HDP) process, e.g., undoped silicate glass (USG), phosphorous doped silicate glass (PSG) or borophosphosilicate glass (BPSG). Alternatively, the ILD layer 12 may be formed of doped or P-doped spin-on-glass (SOG), PTEOS, or BPTEOS.
The contact hole 14 is formed in the ILD layer 12 by a dry etching process, exposing a portion of the IC component 200. In an embodiment, following planarization on the ILD layer 12, a dielectric anti-reflective coating (DARC) or/and a bottom anti-reflectance coating (BARC) and a lithographically patterned photoresist layer are provided, which are omitted in the Figures for simplicity and clarity. A dry etching process is then carried out to form the contact holes 14 that pass though the ILD layer 12 so as to expose a contact region of the IC component 200, e.g., a silicide layer positioned over a source/drain region. Then the patterned photoresist and the BARC layer are stripped.
With reference to
With reference to
The TSV opening 18 passes through at least a portion of the substrate 10. The TSV opening 18 may be etched using any suitable etching method including, for example, plasma etch, a chemical wet etch, a laser drill, and/or other processes known in the art. In one embodiment, the etching process includes a deep reactive ion etching (RIE) process to etch the substrate 10. The etching process may be such that the TSV opening 18 is etched from the front surface 10 a to reach approximately tens of micron˜hundreds of micron in depth without passing through the back surface 10 b. The etching process may result in an opening having a vertical sidewall profile or a tapered sidewall profile. In one embodiment, the TSV opening 18 has a depth of approximately 20˜100 um, and a diameter of approximately 1.5˜10 um. The TSV opening 18 has a high aspect ratio between approximately 5 and approximately 10. In some embodiments, the aspect ratio of the TSV opening 18 is greater than 10.
With reference to
The process proceeds to the formation of TSV-filled process. A second conductive material layer 24 is formed on the barrier layer 22 to fill the TSV opening 18. The second conductive material layer 24 includes a low resistivity conductor material selected from the group of conductor materials including, but is not limited to, copper and copper-based alloy. For example, a copper-fill process includes metal seed layer deposition and copper electro plating. The metal seed layer deposition may be formed by physical vapor deposition. Other methods for forming copper seed layer, such as CVD are known in the art. Then the wafer 100 is transferred to a plating tool, such as an electrochemical plating (ECP) tool, and a copper layer is plated on the wafer 100 by the plating process to fill the TSV opening 18. While ECP process is described herein, the embodiment is not limited to ECP deposited metal. Alternatively, the second conductive material layer 24 may include various materials, such as tungsten, aluminum, gold, silver, and the like.
Next, as shown in
This CMP process advantageously removes all of these materials layers 24, 22, 20 and 16 simultaneously at the substantially same material removal rates. Compared with the conventional method of performing two steps of CMP processes for the contact plug process and TSV process respectively, this disclosure provides embodiments of CMP processing of the contact plug and the TSV structure simultaneously to reduce process costs. There is no need to develop new slurry used for the CMP process of the TSV structure, and a step of depositing a CMP stop layer used for the conventional CMP process of the TSV structure can be therefore omitted.
Subsequently, back-end-of-line (BEOL) interconnection technologies will be processed on the wafer 100 to fabricate an interconnection structure including a plurality of interconnection layers and inter-metal dielectric (IMD) layers. Embodiments of the present invention use copper-based conductive materials for forming the interconnection layers. The copper-based conductive material is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium. A standard damascene process may be used with the copper BEOL interconnection.
With reference to
With reference to
With reference to
In some embodiments, a barrier layer 32 is optionally deposited before the formation of the third conductive material layer 30. The barrier layer 32 functions as a diffusion barrier to prevent metal diffusion and as an adhesion layer between metal and dielectric. Refractory metals, refractory metal-nitrides, refractory metal-silicon-nitrides and combinations thereof are typically used for the barrier layer 32. The diffusion barrier layer may include, but is not limited to, a refractory material, TiN, TaN, Ta, Ti, TiSN, TaSN, W, WN, Cr, Nb, Co, Ni, Pt, Ru, Pd, Au, CoP, CoWP, NiP, NiWP, mixtures thereof, or other materials that can inhibit diffusion of copper into the ILD layer 12 by means of PVD, CVD, ALD or electroplating.
Next, as shown in
Compared with the conventional method of performing two steps of metal deposition and two steps of CMP processes for the contact plug process and TSV process respectively, this disclosure provides embodiments of filling the contact hole and the TSV opening with a conductive material layer simultaneously and performing a CMP processing of the contact plug and the TSV structure simultaneously. In addition to the advantages of performing one step of CMP process, the one step of metal-filling process can further reduce process costs.
In the preceding detailed description, the disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications, structures, processes, and changes may be made thereto without departing from the broader spirit and scope of the disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not restrictive. It is understood that the disclosure is capable of using various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.
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|U.S. Classification||438/667, 438/672, 438/675, 257/E21.577|
|Cooperative Classification||H01L21/76898, H01L21/76838|
|European Classification||H01L21/768T, H01L21/768C|
|Mar 30, 2010||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, MING-FA;LIN, I-CHING;REEL/FRAME:024162/0983
Effective date: 20100330
|Dec 30, 2015||FPAY||Fee payment|
Year of fee payment: 4