|Publication number||US8227860 B2|
|Application number||US 12/622,360|
|Publication date||Jul 24, 2012|
|Filing date||Nov 19, 2009|
|Priority date||Feb 28, 2003|
|Also published as||US20100065906|
|Publication number||12622360, 622360, US 8227860 B2, US 8227860B2, US-B2-8227860, US8227860 B2, US8227860B2|
|Inventors||Martin Alter, John Durbin Husher|
|Original Assignee||Micrel, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Referenced by (1), Classifications (24), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present application is a continuation-in-part under 35 U.S.C. 120 of patent application Ser. No. 11/417,457 entitled “Method and System for Vertical DMOS with Slots”, filed on May 4, 2006 now U.S. Pat. No. 7,576,390, which is a divisional of patent application Ser. No. 10/376,773 entitled “Method and System for Vertical DMOS with Slots”, filed Feb. 28, 2003 now U.S. Pat. No. 7,087,491, the contents of each being hereby incorporated by reference.
The present invention relates generally to semiconductor devices, and more particularly, to a vertical DMOS device with low Ron X area.
This approach results in an output transfer curve as shown in
Accordingly, what is needed is a device that overcomes the above-identified problems. The present invention addresses such a need.
A device for providing a vertical DMOS device is disclosed. The device comprises a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures.
This slotted approach results in a dense vertical DMOS device with a low Ron due to the slotted design, an oxide isolated process without any extra steps other than the slots, a lower capacitance, a lower leakage, a smaller die, an improved higher heat transfer, an improved electro-migration, a lower ground resistance and less cross talk. Meanwhile, it eliminates the isolation diffusion and the sinker diffusion with mostly low temperature processing and provides double metal with single metal processing.
The present invention relates generally to semiconductor devices and more particularly to a vertical DMOS device with a low Ron X area product. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
A system and method in accordance with the present invention provides for a Vertical DMOS device in which the pinch off region is eliminated and the quasi saturated region. This results in a more ideal output curve as shown in
In the process described, the general steps taken by the industry in standard epitaxial vertical DMOS are used when proceeding through the cross-section makeup of the STI process. However, in this approach the buried power buss approach described in U.S. patent application Ser. No. 10/034,184, entitled “Buried Power Buss for High Current, High Power Semiconductor Devices and a Method for Providing the Same” and filed on Dec. 28, 2001, includes slots processed at the end of the total process. The slots are oxidized, filled with metal, coated with a dielectric and then receive the standard metal and interconnect mask. Many steps of the standard vertical DMOS and BICMOS are eliminated to simplify the total process. This patent application approach provides additional unique advantages over the conventional approach.
The slots are oxidized and may be filled with poly, or metal which will represent the gate material of the Vertical DMOS. If one wishes to use an approach compatible with CMOS, BiCMOS, or BCD, poly would be used as the gate material. This is to allow for subsequent high temperature diffusions for those approaches. In these approaches where slots are filled with poly one may process CMOS using the source/body diffusions for the P channel and N channel source/drains. For BiCMOS the source/body diffusions may be used as the emitters and bases of the Bipolar devices or one may process as separate entities. For BCD the source/body diffusions may be used or separate diffusions for the Bipolar and CMOS portions or separate diffusions done.
Voltage applied to the poly gates inverts the vertical walls of the P body, which is buried, thus connecting the N Source to the epitaxial and buried layer of the Vertical DMOS (see
The other thing that is unique is that the body no longer needs to be tied to ground. The only reason the body was tied to ground on previous structures was to cut the body off to prevent current flow that would result in NPN action and snap back voltage occurring. This can be seen in
In the structure being described here, there is no extra body. It has been eliminated by design and results in NO bias build up and no snap back voltage. With this shorter structure, the channels formed vertically in the body on all sides of the slot short out the complete body.
This structure eliminates the requirement of an interconnect protruding into the array to short the source to body in the array. Since this is eliminated, there is no space required, thus leaving the array with tighter packing density. This structure, due to the elimination of the extra body length and elimination of the “resistor” portion reduces the active area size, reduces the input capacitance, increases the efficiency and results in a higher frequency device.
It is obvious that the packing density on this type of array is very high. It is only limited by the poly filled slot of 3 um and the area it takes up. Reduction of the slot “B” dimension to 2 um or much less will significantly reduce the array size even further without affecting the operation of the device. This slot can be reduced to 1 um since the poly thickness of 3500 A could easily conform to the sides and this would make for an even tighter array. With the equipment available today the slot dimensions are only limited by the manufacturer's resolution of critical dimensions they are able to resolve and the ability to provide even thinner poly where required in the slots.
The channel length of this device is not determined by a critical masking but is determined by the difference between the “N” diffusion of the source and the “P” diffusion of the body. This is the channel region that is inverted when voltage is applied between gate and ground. This of course could provide very short channels. If the spacing between slots (the active area, dimension D) were to be made 2 um, then any voltage on the poly gates would result in the inversion covering the total body. Channels coming in from all sides would meet resulting in complete activation of the total body regions. The path from source to epi/buried layer would be as wide as the distance between the slots leaving only N type material (after inversion) between the source and the N epitaxial. This would result in no P body material (as there are on present designs used in the industry) to ever cause a problem. At that point the whole array would be active except for the poly. This would result in a very efficient array and result in a very low Ron X area PowerFET. One that is able to carry high currents where required with lower IR drops than the standard methods used in the industry and higher operating voltages and currents.
Forming the Ground Strap, Buried Power Buss, Sinker and Drain
In proceeding directly to the metal structures of the device and eliminating discussion of the CMOS and BiPolar sections of the approach, it is assumed these steps are done as normal up to the contact and metal process and will not be discussed.
The metal process is different, in that, prior to metal, a few thin layers of dielectric are deposited and the places where metal is to be deposited are opened down to nitride. This is followed by a thick layer of TEOS that is approximately 9000 A thick. This is polished and provides a tapered (shallow trench isolation type) structure where the metal will enter the contact areas. Slots are now etched (approximately 3 um) where the ground strap, metal sinker and the power buss are located.
The B portion of
The C portion of
Instead of one big serpentine design we can also make the array of the large PowerFET design 904 with macros as shown in
These metal busses perform several functions. The sinker metal results in (shown with an N type implant that was done just after the slot oxidation) a metal alloy into the silicon at the point where the sinker slots, implant N+ into the bottom of the slots and buried layer intersect to provide a low resistance portion. Since the epi is only 3 um to 7 um thick, depending on the voltage that needs to be supported, the buried layer comes up about 2-3 um and the slot implant anneal almost connects the two. This is followed by a metal that is alloyed giving a low resistance metal sinker portion and reduces the PowerFET's resistance.
The buried power buss approach results in a structure that is a low profile and provides two layers of metal, thus eliminating a need for a second metal. Since the metal is 3.0 to 6.0 um thick, it can carry the high current at the first level of metal. Half of this thickness of metal is all that needs patterning thus eliminating the need for thick metal etching. Since the first deposition is buried in these slots they offer no steps for the second deposition to cross over. This is a major advantage of this approach.
Standard approaches cannot have two thick metals since the step over the first metal will result in the second metal breaking over these steps. With this approach one obtains two thick levels of metal with only one level (the last and thinner one) being patterned by the standard “resist-patterning-etch process, and this second metal does not go over high steps since the first metal is buried in the slots.
Standard approaches require both layers of metal to go through this procedure. Because of this limitation the standard approach uses a thin first layer of metal that is patterned. This is followed by dielectrics, via openings, and a second thick metal which is patterned. This results in the first metal carrying very little current and the second metal carrying the high current. With the approach discussed here, the first deposition is thick metal and carries the high current. The second deposition (as opposed to a complete second metal in the standard approach) is the patterned metal and can be thin and easily routed. Where desired, the thinner metal contacts the thick first layer and results in an even thicker metal. The combination of the two depositions results in a very thick metal capable of carrying even heavier current than the first deposition and more current than any other approach using the same amount of surface area. This approach also eliminates the deposition of a dielectric and the patterning of the vias that occur in the standard dual metal approach. The ground strap is also a “buried structure” and allows grounding to be located at many places in the chip thus allowing additional metal layers if necessary without offering a large step this additional metal to pass over. In cases where we think it is wise we can have the ground strap contact an edge of the serpentine body. This is easily accomplished by having spots where there are no source diffusions covering the body diffusions at the grounding points. This will allow the ground strap to hit both the source edge and the body directly (see
Another advantage of the metal being in a slot relates to a means of eventually providing thicker metal while only having to deposit half that amount. This is done by taking advantage of the fact that you can “fold” the metal in the slots. With a 3 um slot depth and width, one could deposit 1.5 um of metal and have the slots look like 3 um of metal thickness. This would give the grounds, sinkers, and power busses significant metal thickness without needing to deposit or etch thick metal. Eventually one could have 5 um metal slots that would allow 2.5 um of metal deposition resulting in 5 micron thick metal busses for ground and power. This is accomplished by having metal that is conformal. This can be obtained using CVD metal deposition. Another approach is to have metal deposited over the entire wafer followed by resist application and planar etching the resist and the metal in the field, or CMP removal of to remove metal in the field while leaving the metal in the slots. The second deposition results in metal in the slots being very thick and the metal in the field much thinner and this is the metal that is patterned for the interconnects. To provide a structure with sloped metal entering the metal area, I have placed the 9000 A of TEOS process at the beginning of the metalization process. After polishing it leaves a sloped entrance into these metal slot areas as shown in
This approach is very robust for the Vertical DMOS relative to:
Punch through voltage—body concentration gradient results in depletion extending into the epitaxial area rather than the body.
Reach through voltage—distance between body and epitaxial material can be made ample to prevent reach through.
Breakdown voltage and the planar breakdown of the epi to body would be high.
Snap back voltage—The elimination of the extra body length results in snap back being relegated to a non entity. See
Structure can be very robust relative to current carrying capability.
Area of Concern
An area of concern is the voltage across the gate oxide. In the classical vertical DMOS, voltage on the gate oxide is protected by the depletion from the body areas reaching across the current funnel area and thus not allowing high voltage to appear across the gate oxide. Since the design discussed here results in vertical flow of the current and no pinching off of the “funnel” and no JFET actions (all of which have their very good points), it does not have this protection. Considering this, three approaches were reviewed to determine the optimum slot depth relative to the source/body to reduce the voltage across the gate oxide in these slots. These are shown in
Now let's look at the sides of the slot where the P body interfaces with the vertical gate oxide. Case FIG. 10B—where the slot and body end at the same location, will not have a problem. This case has the bottom of the P+ body protecting the gate oxide on the side of the poly slot and voltage on the drain will deplete it partially and the voltage on the poly gate will finish the job. In case
1. Any voltage on the drain will deplete the bottom of the slot and the side of the slot and make it easy for the gate to complete the inversion.
2. Without any drain voltage, when voltage is applied to the gate it will invert the body on the sides and invert the body below the slot. In this case we would have a “channel”, not only on the sides of the slot, but along the bottom and connecting the adjacent body. This would mean we have a continuous channel across the whole bottom of the array and possible a lower Ron X area.
3. With both the gate voltage and drain voltage on, we would have normal operation. In this case the amount of body extending below the slot would be less than a tenth of a micron.
With voltage on the gate there will be current flowing and the voltage across the gate oxide on these sides will be the supply voltage minus any voltage drop in the circuit load, minus any voltage drop in the collector, minus the voltage of the gate. If the supply voltage was 40 volts and the gate voltage was 10 volts, this would probably result in the voltage across this oxide to be about equal to the Ron voltage drop across the PowerFET. This could be very low voltage when used in switching applications and not cause any problems. So, in switching applications type
Therefore it is recommended that the process be done with the body even or slightly below the slot depth as shown in
Unique Approach Using Metal as the Gate Instead of Poly
If metal were used in the slots instead of poly it would restrict processing of the gate using this metal in any early steps in a process where high temperatures would follow. However, it is possible to do the slots and metalization as the last major steps in the processing. In these cases all the diffusions would be done and in place prior to providing the slots. The slots would then be oxidized and implants completed and annealed where needed in the bottom of slots as previously discussed. These slots and their oxide would be used to form metal gates in place of the poly previously discussed for the vertical DMOS. This approach has some advantages relative to the cost for producing this function. One does not need to provide the poly and all the extra processes related to a poly structure. Using the metal gate approach results in less masking steps as well as several major processing steps being eliminated. The combination of eliminating the isolation process, the sinker and drain diffusions, the poly gate process and all it associated steps, and going directed to the metal gate process using the buried power buss process with its dual metal without the dual metal processing, results in a very cost effective approach for a Power FET and other integrated functions.
In one embodiment, the metal layer 1106 comprises tungsten to plug the slot 1100. Tungsten is particularly amenable to insertion using a chemical vapor deposition (CVD) process that may not be possible with other types of metals. Once inserted, excess metal can be removed from the top using a chemical mechanical polishing (CMP) process or a plasma etch technique. Additionally, tugsten has low resistance, and is already used for other metal components in transistors such as contacts and vias.
The polysilicon layer 1104 protects the gate oxide layer 1102 from the metal layer 1106 in providing a pristine connection. Additionally, the polysilicon layer 110 provides an optimal work function value for an appropriate threshold vertical DMOS. More specifically, work function is the first term (i.e., φms) of the Threshold Equation known as V(2φf)=φms+2φf−[Qf/Cs+QB/Cs]. In one embodiment, the polysilicon is inserted with a low pressure CVD process (LPCVD).
The gate oxide layer 1102 interfaces with the input voltage. The gate oxide layer 1102 can be composed of silicon dioxide (SiO2), oxynitride, or the like.
This Process Eliminates:
The space taken up by the body in the large Power FET array
Ground strapping from the body to the source as we know it.
No ground leads into the array.
Highest current for the same surface area consumed.
The sinker process, even though it provides a very good one.
The isolation masking and processing.
The quasi saturation part of the output characteristics. Eliminates the FET type pinching that a vertical DMOS has.
Snap back voltage (sustaining voltage) is eliminated
A buried, gated channel
An array that is very small for the power output
Double channeling for every source drain (Low Ron)
Process capable of high voltages and high currents
No snap back voltage and is not limited by sustaining current
A power buss that provides thick and wide metal while only depositing 1.5-2.0 um of metal for the interconnect to be masked and etched.
A fairly simple and straightforward process that should take less than 15 masking steps in most cases.
Dual metal with single metal processing and simple bussing.
Thick metal to provide low resistance, low loss, excellent heat transfer, extended current before being limited by electro-migration and only requires thin metal processing and etching.
Very low ground resistance
Only high temperature processing after EPI is the deep Pwell that is done prior to most other steps and therefore this turns out to be a low temperature,
well controlled process.
Low capacitance, high frequency of operation.
Inexpensive alternative approach of using a metal gate structure.
All aspects of this approach provide a device with many excellent characteristics. Other than the possible oxide issue discussed for the 10 A approach, this design results in higher voltage applications, higher current applications and an Ron X area that would appear to be as small as any currently in existence.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
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|U.S. Classification||257/335, 257/329, 257/773, 257/330|
|International Classification||H01L31/062, H01L31/113, H01L29/76, H01L23/12, H01L29/94|
|Cooperative Classification||H01L29/0623, H01L29/4236, H01L29/41766, H01L29/1083, H01L29/0878, H01L21/743, H01L29/4925, H01L29/1095, H01L29/0696, H01L29/7813, H01L29/7809|
|European Classification||H01L29/78B2C, H01L29/78B2T, H01L29/49C2, H01L21/74B|
|Nov 19, 2009||AS||Assignment|
Owner name: MICREL, INC.,CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ALTER, MARTIN;HUSHER, JOHN DURBIN;SIGNING DATES FROM 20091105 TO 20091116;REEL/FRAME:023547/0760
Owner name: MICREL, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ALTER, MARTIN;HUSHER, JOHN DURBIN;SIGNING DATES FROM 20091105 TO 20091116;REEL/FRAME:023547/0760
|Jan 25, 2016||FPAY||Fee payment|
Year of fee payment: 4