|Publication number||US8232206 B2|
|Application number||US 12/751,786|
|Publication date||Jul 31, 2012|
|Filing date||Mar 31, 2010|
|Priority date||Apr 8, 2004|
|Also published as||CN1973361A, CN100485876C, DE602005024377D1, EP1733420A2, EP1733420B1, EP2051295A2, EP2051295A3, EP2051295B1, US7005379, US7335935, US7713817, US20050224981, US20060003583, US20080102596, US20100190314, WO2005104190A2, WO2005104190A3|
|Publication number||12751786, 751786, US 8232206 B2, US 8232206B2, US-B2-8232206, US8232206 B2, US8232206B2|
|Inventors||Nishant Sinha, Dinesh Chopra, Fred D. Fishburn|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (25), Classifications (18), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This patent resulted from a continuation application of U.S. patent application Ser. No. 11/968,281, which was filed Jan. 2, 2008, which issued as U.S. Pat. No. 7,713,817, and which is hereby incorporated by reference; which resulted from a divisional application of U.S. patent application Ser. No. 11/188,235, which was filed Jul. 22, 2005, which issued as U.S. Pat. No. 7,335,935, and which is hereby incorporated by reference; which resulted from a divisional application of U.S. patent application Ser. No. 10/822,030, which was filed Apr. 8, 2004, which issued as U.S. Pat. No. 7,005,379; and which is hereby incorporated by reference.
The invention pertains to semiconductor processing methods for forming electrical contacts, and also pertains to semiconductor structures.
Semiconductor fabrication processes frequently involve formation of electrical interconnects within openings. The desired aspect ratio of the openings is increasing for various reasons, including, for example, to compensate for losses in capacitance or inductance. As the aspect ratio increases, it becomes increasingly difficult to conformally fill openings with traditional processes.
A conductive block 14 is formed over base 12. Block 14 can correspond to, for example, a digit line.
An insulative material 16 is formed over base 12 and over block 14. Insulative material 16 can comprise, for example, borophosphosilicate glass (BPSG).
An opening 18 is etched through insulative material 16 to an upper surface of conductive block 14. Opening 18 can be formed utilizing, for example, photolithographic processing to generate a patterned photoresist mask (not shown) which defines a location for opening 18, followed by an etch into material 16 to generate the opening 18, and subsequent removal of the photoresist mask. The opening is shown having vertical sidewalls, but it is to be understood that such is an idealized structure. Frequently the opening will have non-vertical sidewalls due to limitations in etching processes.
A problem that occurs during deposition of one or both of materials 20 and 22 is that the conductive material can grow non-conformally at upper corners proximate opening 18 to form extensions 24. The extensions 24 can ultimately pinch off the top of opening 18 before the opening has been conformally filled with conductive materials 20 and 22. Accordingly, a void 26 remains in the opening. Such void is frequently referred to as a “keyhole”. The shape of the opening 18 and keyhole 26 are shown diagrammatically in
In one aspect, the invention encompasses a semiconductor processing method for forming an electrical contact. A semiconductor substrate is provided. The substrate has a surface suitable for electroless plating, a layer over the surface, and a node supported by the layer. An opening is formed through the layer and to the suitable surface. A periphery of the opening includes an electrically conductive portion of the node. A conductive material is electroless plated within the opening, with the electroless plating being initiated from the suitable surface. The electroless-plated material forms an electrical contact to the node.
In one aspect, the invention encompasses a semiconductor processing method for forming electrical contacts to a capacitor electrode and a digit line. A semiconductor substrate is provided. The substrate supports a digit line and a spacer structure. The digit line comprises a region, and the spacer structure comprises another region. The digit line region has an upper surface, and the spacer structure region has another upper surface. The digit line region upper surface is at about the same elevational height over the substrate as the spacer structure region upper surface. The semiconductor substrate further comprises electrically insulative material over the digit line region and the spacer structure region, and a capacitor electrode supported by the insulative material. Openings are formed through the insulative material. One of the openings is a first opening that extends to the upper surface of the digit line region, and another of the openings is a second opening and extends to the upper surface of the spacer structure region. The second opening has a periphery which includes an electrically conductive portion of the capacitor electrode. A conductive material is electroless plated within the first and second openings. The electroless plating initiates from the upper surfaces of the digit line region and the spacer structure region. The electroless-plated material forms an electrical contact with the digit line in the first opening, and forms an electrical contact with the capacitor electrode in the second opening. The spacer structure can be referred to as a “dummy” structure in particular aspects of the invention to indicate that the structure is an electrical dead-end and thus comprises no electrical purpose. The spacer structure instead has the physical purpose of mimicking the height of the digit line. In other words, the term “dummy structure” is to be understood herein as referring to a structure which is utilized to mimic a physical property of another structure (such as to mimic the height of a digit line structure), and which is circuit inoperable (i.e., which is not part of a current flow path of a circuit). The dummy structure can comprise a single layer or a combination of different layers.
In one aspect, the invention encompasses a semiconductor structure. The structure includes a semiconductor substrate, a digit line supported by the substrate, and a spacer structure supported by the substrate. The digit line can comprise a single layer or multiple layers, and frequently will comprise a stack of TiN/silicon/WSix; similarly, the spacer structure can comprise a single layer or multiple layers. The digit line comprises a first region having an upper surface at a first elevational height over the semiconductor substrate. The spacer structure comprises a second region having an upper surface at an elevational height over the substrate which is about the same as the first elevational height. The spacer structure is a dummy structure. The semiconductor structure includes electrically insulative material supported by the semiconductor substrate. The electrically insulative material is over the digit line and the spacer structure regions. A capacitor structure is supported by the insulative material. The capacitor structure includes a first capacitor electrode, a second capacitor electrode and at least one dielectric material between the first and second capacitor electrodes. A first conductive interconnect extends upwardly from the digit line region and through the insulative material, and a second conductive interconnect extends upwardly from the spacer structure region, through only one of the first and second capacitor electrodes, and through the insulative material. The first and second conductive interconnects are of the same composition as one another.
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
The invention includes methods which utilize electroless plating to form electrical interconnects within openings. An advantage of electroless plating is that such can be conducted to fill an opening from the bottom of the opening to the top, and accordingly can fill high aspect ratio openings without the prior art problem of pinching off a top of the opening during the fill process.
One aspect of the invention is to utilize electroless plating to form interconnects to two or more circuit structures which are at different elevational heights relative to one another.
A capacitor structure 58 is supported by electrically insulative layer 56. Capacitor structure 58 comprises a first capacitor electrode 60, a second capacitor electrode 62, and at least one dielectric material 64 between capacitor electrodes 60 and 62. Capacitor electrodes 60 and 62 can comprise any suitable electrically conductive materials, including, for example, metals, metal compositions, and/or conductively-doped silicon. In particular aspects, electrode 60 corresponds to a storage node of the capacitor and electrode 62 corresponds to a plate electrode of the capacitor. One or both of the capacitor electrodes can, in some aspects, comprise conductively-doped silicon (such as conductively-doped polycrystalline silicon) and/or a metal composition, such as, for example, one or more of TiN, WN and WSi; with the listed compositions being shown in terms of the elements contained therein rather than in terms of a particular stoichiometry of the elements within the compositions.
The dielectric material 64 can comprise any suitable material, including, for example, one or more of silicon dioxide, silicon nitride, and various high-k dielectric materials.
Capacitor storage node 60 is shown electrically connected to a transistor device 69. As is known to persons of ordinary skill in the art, transistor device 69 would typically comprise a gate (not shown) and a pair of source/drain regions (not shown). Storage node 60 would be connected to one of the source/drain regions, and the other of the source/drain regions would be connected to a bit line (or digit line) (not shown). Accordingly, the transistor gate would gatedly connect storage node 60 to the bit line. The capacitor structure 58 thus can be utilized as a memory storage unit of a memory cell. Specifically, the combination of a transistor structure with a capacitor is a typical unit cell of a dynamic random access memory (DRAM) device. A plurality of the capacitors and transistors can be incorporated into a DRAM array, as is known to persons of ordinary skill in the art.
The shown capacitor construction 58 comprises storage node 60 in a container shape, and comprises dielectric material 64 and capacitor plate electrode 62 extending within the container shape of storage node 60. The shown capacitor construction also comprises horizontally-extending segments 66 and 68 laterally adjacent the portions of the materials 64 and 62 within the container opening. Horizontally-extending segments 66 and 68 can be exactly horizontal, can be substantially horizontal, or can simply be horizontal relative to portions of materials 64 and 62 along the sidewalls of the container opening. Capacitor plate electrode 62 has an upper surface 63 which extends along the horizontally-extending segments 66 and 68, and which also extends within the container shape of storage node 60. The illustrated capacitor construction is an exemplary construction, and it is to be understood that numerous other shapes of capacitor constructions can be utilized in various aspects of the invention.
As discussed previously, the term “substrate” is defined herein to be broad enough to encompass any supporting structure or combination of structures, and the term “semiconductor substrate” is broad enough to encompass any combination of structures provided that one of the structures contains a semiconductor material. Accordingly, either base 52 or structure 54 can be considered a substrate in various aspects of the invention, and also the combination of structure 54 and base 52 can be considered a substrate (or semiconductor substrate) in various aspects of the invention. Additionally, capacitor structure 58 can be considered a substrate in various aspects of the invention, and can be considered a semiconductor substrate if either of the electrodes comprises conductively-doped silicon. Further, the combination of capacitor 58 with base 52 can be considered a semiconductor substrate. Also, the combination of capacitor structure 58, layer 56 and base 52 can be considered a semiconductor substrate, as can the combination of capacitor 58, layer 56, structure 54 and base 52.
Although layer 56 is shown comprising a homogeneous composition, it is to be understood that the layer can be replaced with a stack of layers. The stacked layers can have the same composition as one another or different compositions. Also, although the same material 56 is shown over the structure 54 and around the capacitor 58, it is to be understood that different insulative materials can be over the structure 54 than are around the capacitor 58 in some aspects of the invention. Thus, the insulative material over structure 54 can be referred to as a first insulative material and the insulative material proximate the capacitor 58 can be referred to as a second insulative material. In the shown aspect of the invention, the first and second insulative materials are comprised by common layer 56, and in other aspects of the invention the first and second insulative materials can differ from one another. Further, although the material of layer 56 is shown both above and below capacitor 58, it is to be understood that a different insulative material can be over capacitor 58 than is under capacitor 58 in some aspects of the invention. If the insulative material over the capacitor is different than the insulative material under the capacitor, the insulative material under the capacitor can be referred to as a layer supporting the capacitor and the insulative material over the capacitor can be referred to as being supported by the capacitor.
Openings 70 and 72 have a comparable width to one another, but opening 70 is much deeper than is opening 72. For instance, opening 70 can have a depth of about 3 microns and opening 72 can have a depth of about 1 micron in particular aspects of the invention. In other words, a thickness of layer 56 over segment 68 of capacitor structure 58 can be about 1 micron and a thickness of layer 56 over upper surface 55 of conductive structure 54 can be about 3 microns in particular aspects of the invention.
Although layer 56 is shown as a homogeneous material, at least a portion of layer 56 can be replaced by a stack of insulative materials as discussed previously. In such aspects of the invention, at least one of openings 70 and 72 can extend through the stack of insulative materials.
The electroless plating initiates at upper surfaces 55 and 63 of structures 54 and 62, and accordingly conductive material 80 grows within openings 70 and 72 from the bottoms of the openings to the tops of the openings. Such bottom-up growth can uniformly fill the openings.
As is known to persons of ordinary skill in the art, electroless plating initiates from surfaces which are suitable for the electroless plating. A surface suitable for electroless plating is a surface on which the electroless plating self-initiates from a bath rather than requiring a catalyst to initiate. Suitable surfaces can comprise, for example, one or more of palladium, zinc, silver, nickel and cobalt. Thus, surfaces 55 and 63 can be rendered suitable for initiation of electroless plating by forming the surfaces from materials comprising, consisting essentially of, or consisting of one or more of palladium, zinc, silver, nickel and cobalt. In some aspects, surfaces 55 and 63 can comprise compositions suitable for electroless plating prior to formation of layer 56 over the surfaces. Alternatively, surfaces 55 and 63 can be formed of compositions which are not suitable for electroless plating, and which are subsequently activated after formation of openings 70 and 72. The surfaces can be activated by exposing the surfaces to one or more of nickel, cobalt, palladium, zinc and silver to either incorporate one or more of nickel, cobalt, palladium, zinc and silver into the composition of the upper surfaces or to form a layer containing one or more of nickel, cobalt, palladium, zinc and silver over the upper surfaces. Thus, the composition of surfaces 55 and 63 can be, in particular aspects of the invention, unsuitable for electroless plating when layer 56 is formed over the surfaces, and then portions of the surfaces can be rendered suitable for electroless plating after such portions are exposed through openings 70 and 72.
Compositions unsuitable for electroless plating are typically compositions which do not contain at least one of nickel, cobalt, palladium, zinc or silver in sufficient quantity to initiate electroless plating. Compositions suitable for initiation of electroless plating without activation can be referred to as “self-catalyzing” surfaces, and surfaces needing activation to be suitable for initiation of electroless plating can be referred to as “non-self-catalyzing” surfaces.
In particular aspects of the invention, opening 72 will have a depth which is much less than the depth of opening 70. The electroless plating will form about the same amount of material within opening 72 as is formed within opening 70. Accordingly, formation of sufficient material to fill opening 70 will result in a large amount of excess material formed over opening 72. Thus, a large hump of excess material is shown formed over opening 72, and a substantially smaller hump of material is shown formed over opening 70. The disparity in the thickness of excess material 80 over opening 72 relative to the thickness over opening 70 can complicate subsequent processing. Specifically, it can be difficult to remove the excess conductive material by planarization when the thickness of the excess material has a large variation across the upper surface of layer 56. Additionally, if spacing between 70 and 72 is half of the height difference, material 80 overfilling opening 72 can pinch off opening 70 before opening 70 is filled.
The construction 100 of
Structure 102 can be referred to as a “dummy” structure if the structure has no purpose except to space upper conductive surface 105 from base 52. In such aspects, structure 102 is not connected to circuit devices, and ultimately is an electrical dead end for any electrical interconnect that extends to structure 102. In particular aspects of the invention, structure 54 is a digit line and structure 102 is a “dummy” structure that mimics at least the portion of the digit line where an electrical interconnection is ultimately to be formed.
The digit line 54 will extend into and out of the page in the shown cross section of
Structure 102 is shown comprising a stack of materials, and specifically is shown comprising conductive material 104 over an electrically insulative material 106. It is to be understood that structure 102 can comprise any of numerous configurations which can include a conductive material alone, or a conductive material in combination with insulative materials. Further, although conductive material 104 is shown as the uppermost material of the stack of spacer 102, it is to be understood that an electrically insulative cap could be formed over conductive material 104. Ultimately, however, an opening is typically formed which extends to the uppermost conductive surface 105 of structure 102, and accordingly such opening would extend through any insulative cap formed over uppermost surface 105.
Structure 102 is beneath a portion of capacitor 58, and in the shown aspect of the invention is beneath horizontally-extending segment 68 of capacitor plate electrode 62.
Since conductive surfaces 55 and 105 are at about the same elevational height as one another (and preferably are at an identical elevational height within the tolerances of a semiconductor fabrication process), openings 120 and 122 will be about the same depth as one another (and preferably will be at an identical depth to one another within the limitations of tolerances associated with a particular fabrication process).
In particular aspects of the invention, upper surface 105 can be considered a portion of a semiconductor substrate. Further, surface 105 will ultimately be suitable for electroless plating. When surface 105 is suitable for electroless plating, the combination of structure 102 and semiconductor base 52 can be considered a semiconductor substrate having the surface 105 suitable for electroless plating. Layer 62 can be considered an electrically conductive node, and accordingly opening 122 can be considered to be formed through the electrically conductive node and to the surface 105 suitable for electroless plating.
Upper surfaces 55 and 105 can be formed to be suitable for initiating electroless plating by patterning materials 54 and 104 from compositions suitable for electroless plating and/or by activating upper surfaces of materials 54 and 104 after formation of openings 120 and 122. Accordingly, upper surfaces 55 and 105 can be suitable for electroless plating prior to provision of layer 56; or can be rendered suitable by activation occurring after formation layer 56, and specifically after formation of openings 120 and 122 extending through layer 56. In preferred aspects, surface 105 of material 104 is identical in composition to surface 55 of material 54. In such aspects, surfaces 55 and 105 can comprise one or more of palladium, zinc, silver, nickel and cobalt. It can be preferred that surfaces 55 and 105 comprise one or both of nickel and cobalt in particular semiconductor processing applications.
The conductive material within openings 120 and 122 forms conductive interconnects 130 and 132, respectively. Conductive interconnect 130 extends to structure 54. As discussed previously, structure 54 can comprise a digit line, and accordingly conductive interconnect 130 can be utilized for interconnecting the digit line to other circuitry (not shown). Conductive interconnect 132 extends to capacitor plate electrode, and can thus be utilized for connecting plate electrode 62 to other circuitry (not shown). Conductive interconnect 132 also extends to conductive material 104. However, in typical processing conductive material 104 will be electrically isolated from any circuitry other than conductive interconnect 132, and accordingly will be an electrical dead-end (or terminus).
Various modifications can be made to the shown aspect of the invention, as will be understood by persons of ordinary skill in the art. For instance, although conductive interconnect 132 is shown extending through both dielectric material 64 and capacitor electrode 62, the invention can encompass other aspects (not shown) in which capacitor electrode 62 extends beyond dielectric material 64, and in which the interconnect extends only through capacitor electrode 62 rather than through both capacitor 62 and dielectric material 64. As another example of a modification that can be incorporated into aspects of the invention, interconnect 132 can be formed to be adjacent an end of electrode 62 so that the conductive interconnect 132 is formed beside electrode 62, rather than through the electrode. As another example, processing of the present invention can be utilized to form electrical connection to a node 62 other than a capacitor electrode.
The structure of
The conductive interconnects 130 and 132 can be formed in relatively high-aspect ratio openings, with such openings being formed to any suitable depth, including, for example, depths of greater than or equal to about 3 microns. Thus, layer 56 can have a thickness of at least about 3 microns in the vicinity proximate the shown region of digit line 54, and can also comprise a thickness of at least about 3 microns proximate the shown region of spacer structure 102.
Although capacitor 58 and digit line 54 are shown adjacent one another in the aspect of the invention described with reference to
As described with reference to
After the activation of surface 63, the electroless plating can be continued so that conductive material 80 fills opening 70, and also fills opening 72. Since the openings 70 and 72 were approximately the same depth as one another at the initiation of the second stage of the electroless plating (i.e., at the process stage of
The processing of
Initially, a semiconductor substrate 52 is provided, with such substrate supporting an electrically insulative material 56 and a pair of electrical nodes 54 and 62. Nodes 54 and 62 can be referred to as a first node and a second node, respectively. A first opening 70 extends through the electrically insulative material to the first node and a second opening 72 extends through the electrically insulative material to the second node at the processing stage of
The second surface is then activated to render the second surface suitable for electroless plating. Subsequently, a second conductive material is electroless plated within the first and second openings to form the construction of
Processor device 406 can correspond to a processor module, and associated memory utilized with the module can comprise teachings of the present invention.
Memory device 408 can correspond to a memory module. For example, single in-line memory modules (SIMMs) and dual in-line memory modules (DIMMs) may be used in the implementation which utilize the teachings of the present invention. The memory device can be incorporated into any of a variety of designs which provide different methods of reading from and writing to memory cells of the device. One such method is the page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell array and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed.
An alternate type of device is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on a memory bus. Other alternative types of devices include SDRAM, DDR SDRAM, SLDRAM, VRAM and Direct RDRAM, as well as others such as SRAM or Flash memories.
Memory device 408 can comprise memory formed in accordance with one or more aspects of the present invention.
The memory device 802 receives control signals 824 from the processor 822 over wiring or metallization lines. The memory device 802 is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device 802 has been simplified to help focus on the invention. At least one of the processor 822 or memory device 802 can include a memory construction of the type described previously in this disclosure.
The various illustrated systems of this disclosure are intended to provide a general understanding of various applications for the circuitry and structures of the present invention, and are not intended to serve as a complete description of all the elements and features of an electronic system using memory cells in accordance with aspects of the present invention. One of ordinary skill in the art will understand that the various electronic systems can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device(s).
Applications for memory cells can include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
It is noted that relative elevational relationships are utilized to describe the locations of various features to one another (e.g., upward, downward, etc are utilized) within this disclosure. It is to be understood that such terms are used to express relative relations between the components only, and not to indicate a relationship of the components relative to an external frame of reference. Thus, for example, a feature described herein as projecting upwardly relative to another feature may in fact appear to extend downwardly to a viewer in an external frame of reference relative to the feature.
In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5169680||Mar 11, 1992||Dec 8, 1992||Intel Corporation||Electroless deposition for IC fabrication|
|US5464653||Dec 18, 1990||Nov 7, 1995||Bull S.A.||Method for interconnection of metal layers of the multilayer network of an electronic board, and the resultant board|
|US5950102 *||Feb 3, 1997||Sep 7, 1999||Industrial Technology Research Institute||Method for fabricating air-insulated multilevel metal interconnections for integrated circuits|
|US6344413 *||Feb 12, 1998||Feb 5, 2002||Motorola Inc.||Method for forming a semiconductor device|
|US6395599 *||Mar 9, 1998||May 28, 2002||Fujitsu Limited||Method for fabricating semiconductor storage device|
|US6784067 *||Nov 26, 2002||Aug 31, 2004||Oki Electric Industry Co, Ltd.||Method of manufacturing semiconductor device|
|US7713817 *||Jan 2, 2008||May 11, 2010||Micron Technology, Inc.||Methods of forming semiconductor structures|
|US20010022369 *||May 15, 2001||Sep 20, 2001||Takuya Fukuda||Semiconductor integrated circuit device|
|US20020017673 *||Jul 13, 2001||Feb 14, 2002||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device with capacitor electrodes and method of manufacturing thereof|
|US20020096701||Jan 31, 2002||Jul 25, 2002||Hitachi, Ltd.||Semiconductor device and process for manufacturing the same|
|US20020153614||Jun 12, 2002||Oct 24, 2002||Fujitsu Limited||Semiconductor storage device and method for fabricating the same|
|US20030096498||Nov 15, 2002||May 22, 2003||Dinesh Chopra||Method of providing a structure using self-aligned features|
|US20040257902||Jul 6, 2004||Dec 23, 2004||Grynkewich Gregory W.||Magnetoresistive random access memory device structures and methods for fabricating the same|
|US20050017338||Jun 8, 2004||Jan 27, 2005||Seiko Epson Corporation||Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument|
|US20050074959||Oct 1, 2003||Apr 7, 2005||International Business Machines Corporation||Novel integration of wire bond pad with Ni/Au metallization|
|US20050104228||Nov 13, 2003||May 19, 2005||Rigg Sidney B.||Microelectronic devices, methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices|
|US20050176199||Jul 15, 2003||Aug 11, 2005||Kabushiki Kaisha Toshiba||Semiconductor memory device and method of fabricating the same|
|US20050186777||Jan 3, 2005||Aug 25, 2005||Kirby Kyle K.||Methods of fabricating interconnects for semiconductor components|
|US20070076509||Sep 7, 2006||Apr 5, 2007||Guobiao Zhang||Three-Dimensional Mask-Programmable Read-Only Memory|
|EP0382298A1||Feb 2, 1990||Aug 16, 1990||Philips Electronics N.V.||Method of manufacturing a semiconductor device using electroless metallisation|
|JP2002110784A||Title not available|
|JPH03190136A||Title not available|
|JPH06315443A||Title not available|
|JPH10242418A||Title not available|
|WO2005009781A1||Jul 22, 2004||Feb 3, 2005||Conti Temic Microelectronic Gmbh||Pressure measuring method and device|
|U.S. Classification||438/678, 438/597|
|International Classification||H01L21/44, H01L21/768, H01L21/288|
|Cooperative Classification||H01L21/76879, H01L27/10855, H01L23/522, H01L21/288, H01L2924/0002, H01L21/76816, H01L27/10888|
|European Classification||H01L27/108M4B2C, H01L21/288, H01L21/768C4B, H01L27/108M4D4, H01L21/768B2L, H01L23/522|
|Jan 13, 2016||FPAY||Fee payment|
Year of fee payment: 4
|May 12, 2016||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001
Effective date: 20160426
|Jun 2, 2016||AS||Assignment|
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426