|Publication number||US8237272 B2|
|Application number||US 12/706,086|
|Publication date||Aug 7, 2012|
|Filing date||Feb 16, 2010|
|Priority date||Feb 16, 2010|
|Also published as||CN102163588A, CN102163588B, US20110198747|
|Publication number||12706086, 706086, US 8237272 B2, US 8237272B2, US-B2-8237272, US8237272 B2, US8237272B2|
|Inventors||Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu|
|Original Assignee||Taiwan Semiconductor Manufacturing Company, Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (34), Referenced by (1), Classifications (46), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This disclosure relates generally to semiconductor bump processes, and more particularly to a structure and methods for forming conductive pillars.
Flip chip technology plays an important role in the packaging of semiconductor devices. A flip chip microelectronic assembly includes a direct electrical connection of face down electronic components onto substrates, such as circuit boards, using solder bumps as the interconnects. The use of flip chip packaging has dramatically grown as a result of the flip chips advantages in size, performance and flexibility over other packaging methods.
Recently, conductive pillar technology has been developed. Instead of using solder bumps, electronic components are connected to substrates by means of copper pillars. The copper pillar technology achieves a finer pitch with a lower probability of bump |bridging|, reduces the capacitance load of the circuits and allows the electronic components to perform at higher frequencies.
More recently, through-silicon vias (TSV) have arisen as a method of increasing the density of interconnected electronic components. TSV allow for shorter interconnects by forming an interconnect in the z-axis. The interconnect is created through a substrate (e.g. wafer), by forming a via extending from a front surface to a back surface of the substrate. TSV are also useful in forming interconnects for stacked wafers, stacked die, and/or combinations thereof.
However, combining of conductive pillar technology with through-silicon via (TSV) technology presents a number of challenges. In conventional processes, through-silicon vias are formed to extend from the front surface of the substrate into a predetermined depth in the substrate. The conductive pillars are formed on the front surface of the substrate. The through silicon vias are exposed by polishing the back surface of the substrate using CMP. The pressure applied to the back surface is transferred through the pillars on the front surface. But if the pillars are not evenly distributed across the front surface, the pressure applied to the back will not be evenly distributed, result in non-uniform polishing of the back surface. The non-uniform polishing can result in TSVs of varying length, and an uneven backside surface. The non-uniform backside surface would adversely influence subsequent lithography processes on the backside.
Accordingly, what is needed in the art is a formation method for combining conductive pillars with through-silicon vias, so that both the reliability of the manufacturing process and the high degree of integration can be satisfied.
Various embodiments of the present disclosure may be used to moderate the shortcomings of the conventional pillar manufacturing processes. For example, the various embodiments may reduce the depth uniformity of the backside substrate during chemical mechanical polish.
The disclosure will be described with reference to embodiments thereof as illustrated in the accompanying figures. It should be understood that the drawings are for illustrative purposes and are therefore not drawn to scale.
The making and using of illustrative embodiments are discussed in detail below. It should be appreciated, however, that the disclosure provides many concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.
The term “substrate” as described herein, generally refers to a semiconductor substrate on which various layers and devices are formed. The substrate is originally part of a wafer, which is subsequently divided into a plurality of dies, with each die containing a single semiconductor component. The substrate may include silicon or compound semiconductors, such as GaAs, InP, Si/Ge, or SiC. Examples of layers may include dielectric layers, doped layers, metal layers, polysilicon layers and via plugs that may connect one layer to one or more layers.
Thereafter, a wet or dry etching process may be performed to from recesses in the new second surface 129 to allow the TSVs 111 to protrude from the new second surface 129 of the substrate 100. The through-silicon vias (TSV) 111 provide electrical connection for the first semiconductor component 102 to other components.
Although the present embodiments and the advantages of the present embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5391917||May 10, 1993||Feb 21, 1995||International Business Machines Corporation||Multiprocessor module packaging|
|US5510298||Sep 12, 1994||Apr 23, 1996||Texas Instruments Incorporated||Method of interconnect in an integrated circuit|
|US5767001||May 2, 1994||Jun 16, 1998||Siemens Aktiengesellschaft||Process for producing semiconductor components between which contact is made vertically|
|US5998292||Nov 12, 1997||Dec 7, 1999||International Business Machines Corporation||Method for making three dimensional circuit integration|
|US6184060||May 22, 1998||Feb 6, 2001||Trusi Technologies Llc||Integrated circuits and methods for their fabrication|
|US6322903||Dec 6, 1999||Nov 27, 2001||Tru-Si Technologies, Inc.||Package of integrated circuits and vertical integration|
|US6448168||Apr 14, 2000||Sep 10, 2002||Intel Corporation||Method for distributing a clock on the silicon backside of an integrated circuit|
|US6465892||Apr 13, 2000||Oct 15, 2002||Oki Electric Industry Co., Ltd.||Interconnect structure for stacked semiconductor device|
|US6472293||Nov 30, 2001||Oct 29, 2002||Oki Electric Industry Co., Ltd.||Method for manufacturing an interconnect structure for stacked semiconductor device|
|US6538333||Jun 11, 2002||Mar 25, 2003||Chartered Semiconductor Manufacturing Ltd.||Three dimensional IC package module|
|US6599778||Dec 19, 2001||Jul 29, 2003||International Business Machines Corporation||Chip and wafer integration process using vertical connections|
|US6639303||Dec 17, 1999||Oct 28, 2003||Tru-Si Technolgies, Inc.||Integrated circuits and methods for their fabrication|
|US6664129||Dec 12, 2002||Dec 16, 2003||Tri-Si Technologies, Inc.||Integrated circuits and methods for their fabrication|
|US6693361||Nov 16, 2000||Feb 17, 2004||Tru-Si Technologies, Inc.||Packaging of integrated circuits and vertical integration|
|US6740582||Apr 26, 2002||May 25, 2004||Tru-Si Technologies, Inc.||Integrated circuits and methods for their fabrication|
|US6800930||Jul 31, 2002||Oct 5, 2004||Micron Technology, Inc.||Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies|
|US6841883||Mar 31, 2003||Jan 11, 2005||Micron Technology, Inc.||Multi-dice chip scale semiconductor components and wafer level methods of fabrication|
|US6882030||Jan 28, 2002||Apr 19, 2005||Tru-Si Technologies, Inc.||Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate|
|US6924551||May 28, 2003||Aug 2, 2005||Intel Corporation||Through silicon via, folded flex microelectronic package|
|US6962867||Dec 10, 2003||Nov 8, 2005||Microntechnology, Inc.||Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof|
|US6962872||Aug 31, 2004||Nov 8, 2005||International Business Machines Corporation||High density chip carrier with integrated passive devices|
|US7030481||Dec 9, 2002||Apr 18, 2006||Internation Business Machines Corporation||High density chip carrier with integrated passive devices|
|US7049170||Dec 17, 2003||May 23, 2006||Tru-Si Technologies, Inc.||Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities|
|US7060601||Dec 17, 2003||Jun 13, 2006||Tru-Si Technologies, Inc.||Packaging substrates for integrated circuits and soldering methods|
|US7071546||Mar 12, 2003||Jul 4, 2006||Alfred E. Mann Foundation For Scientific Research||Space-saving packaging of electronic circuits|
|US7111149||Jul 7, 2003||Sep 19, 2006||Intel Corporation||Method and apparatus for generating a device ID for stacked devices|
|US7122912||Jan 25, 2005||Oct 17, 2006||Nec Electronics Corporation||Chip and multi-chip semiconductor device using thereof and method for manufacturing same|
|US7157787||May 26, 2004||Jan 2, 2007||Intel Corporation||Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices|
|US7193308||Sep 22, 2004||Mar 20, 2007||Seiko Epson Corporation||Intermediate chip module, semiconductor device, circuit board, and electronic device|
|US7262495||Oct 7, 2004||Aug 28, 2007||Hewlett-Packard Development Company, L.P.||3D interconnect with protruding contacts|
|US7297574||Jun 17, 2005||Nov 20, 2007||Infineon Technologies Ag||Multi-chip device and method for producing a multi-chip device|
|US7335972||Nov 13, 2003||Feb 26, 2008||Sandia Corporation||Heterogeneously integrated microsystem-on-a-chip|
|US7355273||Apr 20, 2005||Apr 8, 2008||Micron Technology, Inc.||Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods|
|US20100171226 *||Dec 29, 2009||Jul 8, 2010||Texas Instruments, Inc.||Ic having tsv arrays with reduced tsv induced stress|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US9502640||Nov 3, 2015||Nov 22, 2016||International Business Machines Corporation||Structure and method to reduce shorting in STT-MRAM device|
|U.S. Classification||257/737, 257/734, 257/700, 438/106, 257/714, 257/686, 438/110, 438/108, 438/109, 257/698|
|Cooperative Classification||H01L2924/19041, H01L24/16, H01L2924/10329, H01L21/6836, H01L2924/01033, H01L2924/30105, H01L24/14, H01L2224/11462, H01L2924/00013, H01L21/76898, H01L24/13, H01L24/11, H01L2924/01032, H01L2924/01078, H01L2924/01013, H01L2924/01029, H01L2224/13139, H01L2224/13144, H01L23/481, H01L2924/01005, H01L2924/01079, H01L2221/6834, H01L2924/014, H01L23/522, H01L2224/13147, H01L2924/01047, H01L2224/13124, H01L2224/13111, H01L23/5256|
|European Classification||H01L21/683T2, H01L23/525F, H01L21/768T, H01L23/522, H01L23/48J, H01L24/14|
|Apr 14, 2010||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KUO, HUNG-JUI;LIU, CHUNG-SHI;YU, CHEN-HUA;REEL/FRAME:024232/0645
Effective date: 20100223
|Jan 20, 2016||FPAY||Fee payment|
Year of fee payment: 4