US8633078B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
US8633078B2
US8633078B2 US13/240,470 US201113240470A US8633078B2 US 8633078 B2 US8633078 B2 US 8633078B2 US 201113240470 A US201113240470 A US 201113240470A US 8633078 B2 US8633078 B2 US 8633078B2
Authority
US
United States
Prior art keywords
region
substrate
gate pattern
forming
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US13/240,470
Other versions
US20120108023A1 (en
Inventor
Kwan-Yong Lim
Chung-Geun Koh
Sang-Bom Kang
Ui-hui Kwon
Hyun-Jung Lee
Tae-Ouk Kwon
Seok-Hoon Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIM, KWAN-YONG, KANG, SANG-BOM, KIM, SEOK-HOON, KOH, CHUNG-GEUN, KWON, TAE-OUK, KWON, UI-HUI, LEE, HYUN-JUNG
Publication of US20120108023A1 publication Critical patent/US20120108023A1/en
Application granted granted Critical
Publication of US8633078B2 publication Critical patent/US8633078B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7847—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a reduced leakage current and improved channel conductivity, and a method for manufacturing the semiconductor device.
  • a semiconductor increases discrete devices such as a metal oxide semiconductor (MOS) transistor.
  • MOS metal oxide semiconductor
  • a channel region located under the gate becomes shorter.
  • One mechanism for increasing the mobility of carriers is to induce compressive stress to a channel region to thereby increase hole mobility in the channel, while inducing tensile stress to the channel region to improve electron mobility in the channel region.
  • the stress memorization technique is one technique that has recently been used to induce stress to a channel, which may, however, result in an increase of leakage current.
  • Embodiments of the present invention include a semiconductor device having a reduced leakage current and improved channel conductivity, as well as a method for manufacturing a semiconductor device having a reduced leakage current and improved channel conductivity.
  • a semiconductor device including a gate pattern is formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate is formed at one side of the gate pattern.
  • a method for manufacturing a semiconductor device includes forming a gate pattern on a substrate, forming a mask on the substrate at one side of the gate pattern, forming an amorphous region by implanting impurities into the substrate, removing the mask, and forming a recrystallized region by forming a stress liner on the substrate to cover the gate pattern and crystallizing the amorphous region.
  • the mobility of carriers can be enhanced by increasing stress applied to a channel.
  • the mobility of carriers can be more effectively enhanced by inducing more stress from a source region than from a drain region.
  • characteristics of the semiconductor device can be more enhanced by reducing a leakage current generated in the drain region.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a flow chart showing process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIGS. 3A to 3H are cross-sectional views showing process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • Embodiments described herein will be described referring to plan views and/or cross-sectional views by way of ideal schematic views of the invention. Accordingly, the exemplary views may be modified depending on manufacturing technologies and/or tolerances. Therefore, the embodiments of the invention are not limited to those shown in the views, but include modifications in configuration formed on the basis of manufacturing processes. Therefore, regions exemplified in figures have schematic properties; and shapes of regions shown in figures are exemplary and are not intended to limit aspects of the invention.
  • FIG. 1 provides a cross-sectional view of the semiconductor device.
  • the semiconductor device may include a gate pattern 120 , a recrystallized region 130 , a source region 142 and a drain region 143 .
  • the semiconductor device may further include a gate spacer 124 and a lightly doped drain (LDD) region 141 .
  • LDD lightly doped drain
  • the gate pattern 120 is formed on a substrate 110 , and a channel region is formed under the gate pattern 120 to allow a current to flow therethrough.
  • the substrate 110 may be a rigid substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a gallium arsenic substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, and a display glass substrate.
  • the substrate 110 may be a flexible plastic substrate made of, for example, polyimide, polyester, polycarbonate (PC), polyethersulfone (PES), polymethyl methacrylate (PMMA), or polyethylene naphthalate (PEN), polyethylene terephthalate (PET).
  • the gate pattern 120 may include a gate insulating layer 121 and a gate electrode 122 .
  • a hard mask layer that protects the gate electrode 122 may be formed on the gate electrode 122 .
  • the hard mask layer may be formed of silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON), but is not limited thereto.
  • the gate insulating layer 121 may include a silicon oxide (e.g., SiO 2 ) layer, a silicon nitride (e.g., Si 3 N 4 ) layer, SiON, Ge x O y N z , Ge x Si y O z , a high-k dielectric material or a combination thereof, or a stacked layer having these materials sequentially stacked.
  • the high-k dielectric material may include, but not limited to, HfO 2 , ZrO 2 , Al 2 O 3 , Ta 2 O 5 , hafnium silicate, zirconium silicate, a combination thereof.
  • the gate electrode 122 may be formed of, but not limited to, a single layer of poly-Si, poly-SiGe, doped poly-Si, a metal such as Ta, TaN, TaSiN, TiN, Mo, Ru, Ni, or NiSi, or a metal silicide, or a stacked layer having these materials sequentially stacked.
  • a metal such as Ta, TaN, TaSiN, TiN, Mo, Ru, Ni, or NiSi, or a metal silicide, or a stacked layer having these materials sequentially stacked.
  • the gate electrode 122 is formed of a metal or a metal silicide, low resistance can be realized with a fine line width, and doping impurities are not necessary.
  • the gate spacer 124 is formed on sidewalls of the gate pattern 120 and protects the gate electrode 122 .
  • the gate spacer 124 may have a single-layered structure formed of silicon nitride or a silicon oxide or a multilayered structure including a combination of a silicon nitride layer and a silicon oxide layer.
  • FIG. 1 illustrates that the gate spacer 124 includes a first spacer 124 a and a second spacer 124 b .
  • the first spacer 124 a may be formed of a silicon oxide layer
  • the second spacer 124 b may be formed of a silicon nitride layer.
  • the recrystallized region 130 is formed at one side of the substrate 110 in view of the gate pattern 120 . That is to say, the recrystallized region 130 is asymmetrically formed only at one side of the substrate 110 in view of the gate pattern 120 .
  • the recrystallized region 130 applies tensile stress or compressive stress to the channel region to thereby enhance carrier mobility in the channel region.
  • the recrystallized region 130 has a stacking fault defect.
  • the stacking fault defect may occur when locations of atomic layers are changed or part of a continuous layer is added or removed due to stress applied to an amorphous region in the course of recrystallizing the amorphous region. Due to the stacking fault defect, the stress applied by recrystallizing is retained at a recrystallized lattice even after the stress is eliminated, and compressive stress or tensile stress is applied to the channel region. As shown in FIG. 1 , the stacking fault defect may be formed such that it becomes closer to the gate pattern 120 (that is, in a direction indicated by an arrow ‘C’) downwardly in the substrate 110 .
  • the LDD region 141 is formed by implanting low concentration impurity ions into the substrate on opposite sides of the gate pattern 120 .
  • the LDD region 141 relaxes electric fields in the source region 142 and the drain region 143 and reduces leakage current.
  • the impurities may be implanted by an ion implantation process.
  • n-type impurities e.g., P, As, or the like
  • NMOS negative metal oxide semiconductor
  • PMOS positive metal oxide semiconductor
  • a portion of the LDD region 141 on the source region 142 is formed in the recrystallized region 130 , which is formed in the substrate 110 on one side of the gate pattern 120
  • the source region 142 and the drain region 143 are spaced apart from each other in view of the gate pattern 120 and the gate spacer 124 , and are formed by implanting heavily doped impurities using the gate pattern 120 and the gate spacer 124 as masks.
  • an n-type dopant such as phosphorus (P) or arsenic (As) may be implanted; and for a PMOS region, a p-type dopant such as boron (B) or gallium (Ga) may be implanted.
  • the source region 142 or the drain region 143 may be formed in the recrystallized region 130 .
  • the source region 142 formed in the recrystallized region 130 may have a stacking fault defect.
  • the drain region 143 is spaced apart from and faces the source region 142 in view of the gate pattern 120 while having no stacking fault defect.
  • the mobility of carriers can be enhanced by applying stress to the channel region.
  • an end-of-range (EOR) defect may be generated around an amorphous region in the course of amorphizing the substrate 110 before crystallization, and gate-induced drain leakage (GIDL) may occur to the drain region 143 .
  • the EOR defect may increase the GIDL.
  • the source region 142 with a stacking fault defect can enhance the carrier mobility by increasing the stress applied to the channel region, while the drain region 143 without a stacking fault defect can reduce leakage current.
  • Each of the source region 142 and the drain region 143 may have an elevated structure raised from the substrate 110 .
  • the elevated source and drain structures may have shallow junction structures (with a projected range, R p ) formed on a top surface of the substrate 10 by injecting impurities. Accordingly, undesired degradation of the device characteristics due to a short channel effect can be overcome.
  • FIG. 2 is a flow chart showing the process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIGS. 3A to 3H are cross-sectional views of the semiconductor device being manufactured with the process steps of FIG. 2 .
  • a method for manufacturing the semiconductor device may include forming a gate pattern (step S 10 ), forming a mask (step S 20 ), asymmetrically amorphizing (step S 30 ), removing the mask (step S 40 ) and recrystallizing (step S 50 ).
  • the method for manufacturing the semiconductor device may further include forming an LDD region (step S 60 ) and forming source and drain regions (step S 70 ).
  • the device is shown after step S 10 , when a gate pattern 120 , including a gate insulating layer 121 and a gate electrode 122 , is formed on a substrate 110 .
  • an insulating layer for forming a gate insulating layer 121 and a layer for forming a gate electrode 122 are sequentially formed on the substrate 110 and patterned, thereby forming the gate pattern 120 having a stacked structure with the gate insulating layer 121 and the gate electrode 122 sequentially stacked.
  • a hard mask layer (not shown) may be formed on the gate electrode 122 , it may be skipped as demanded by one skilled in the art.
  • an insulating layer formed of a silicon oxide layer or a silicon nitride layer that is part of a gate spacer 124 may further be formed on sidewalls of the gate pattern 120 .
  • the device is shown after step S 20 , when a mask 131 is formed on the substrate 110 at one side of the gate pattern 120 .
  • the mask 131 prevents impurities from being implanted into the substrate 110 below the mask 131 and being amorphized.
  • a hard mask layer or a photoresist layer is deposited to cover either side of the substrate 110 at opposite sides of the gate pattern 120 .
  • the mask 131 is formed of a hard mask layer or a photoresist.
  • the hard mask layer may be formed of an insulating layer, and the photoresist layer may be formed of any photoresist that is generally used in the art.
  • step S 30 the device is shown in step S 30 , as an amorphous region 130 a is formed by implanting impurities into the substrate 110 .
  • the impurity ions permeate into interstices of a crystal lattice, so that a crystalline region is changed into the amorphous region 130 a .
  • the ion implantation process may be performed by a generally known method, and non-limiting examples of the impurities may include Si, Ge, Sb, In, As, P, BF 2 , Xe and Ar.
  • One side of the substrate 110 in view of the gate pattern 120 is covered by the mask 131 .
  • amorphization asymmetrically occurs only at a region of the substrate that is not covered by the mask 131 .
  • the impurities may be implanted in a direction perpendicular to the substrate 110 , as indicated by A (as shown, the impurities A are implanted in a direction perpendicular to the substantially planar exposed surface of the amorphous region 130 a ), or may be implanted at a predetermined angle ( ⁇ ) of inclination, as indicated by B, with respect to the direction perpendicular to the substrate.
  • ⁇ angle of inclination
  • the predetermined angle ( ⁇ ) may be in a range of 10 to 40 degrees, more particularly in a range of 20 to 30 degrees.
  • the amorphous region 130 a may be formed close to the channel region, and impurity ions may be implanted without interference considering a distance between gate patterns 120 .
  • step S 40 the device is shown after step S 40 , when the mask 131 , which was formed on the substrate 110 only to one side of the gate pattern 120 , is removed.
  • amorphization is performed only on the substrate 110 at one side of the gate pattern 120 , where the mask 131 is not formed, by an ion implantation process, as discussed above; and the mask 131 is then removed.
  • the mask 131 may be removed by ashing and cleaning.
  • the device is shown during step S 50 , when a stress liner 132 is formed on the entire surface of the substrate 110 to cover the gate pattern 120 , and the amorphous region 130 a is recrystallized to form a recrystallized region 130 .
  • the stress liner 132 is deposited on the entire surface of the substrate 110 by chemical vapor deposition (CVD) to cover the gate pattern 120 and annealed, thereby recrystallizing the amorphous region 130 a in the substrate 110 into a solid phase epitaxy.
  • CVD chemical vapor deposition
  • the stress liner 132 may be made of a material having a thermal expansion coefficient that differs from that of the material that forms the substrate 110 .
  • the stress liner 132 may be made of a material capable of applying tensile stress to the channel region.
  • the stress liner 132 may be made of a material capable of applying compressive stress to the channel region.
  • the stress liner 132 may be formed of a silicon nitride (Si x N y ) layer using a low-pressure chemical vapor deposition (LPCVD) process.
  • LPCVD low-pressure chemical vapor deposition
  • the stress liner 132 may be formed of silicon carbide (SiC) using a plasma-enhanced chemical vapor deposition (PECVD) process.
  • the annealing may include, but is not limited to, spike annealing, rapid thermal annealing, and the like, which may be quickly performed.
  • the annealing performed in the presence of the stress liner 132 brings about crystallization to the solid phase epitaxy in the amorphous region 130 a .
  • a stacking fault defect may occur when part of a continuous layer is added or removed while crystals of the amorphous region 130 a regrow. Accordingly, the stress applied to the amorphous region 130 by the stress liner 132 is retained in the recrystallized region 130 even after the stress liner 132 is eliminated, thereby applying stress to the channel region and increasing the channel conductivity.
  • the stacking fault defect is formed such that it becomes closer to the gate pattern (that is, in a direction indicated by an arrow ‘C’) downwardly in the substrate 110 .
  • the amorphous region is formed much closer to the channel region and the stacking fault defect is formed much closer to the channel region, thereby further enhancing stress applied to the channel region.
  • the stress liner 132 is completely removed by, for example, etching.
  • a silicon oxide layer (not shown) covering the entire surface of the substrate 110 may be formed. The silicon oxide layer may serve as an etch stop layer when etching the stress liner 132 , and is also completely removed after recrystallization.
  • FIG. 3G which shows the device after step S 60 , when a lightly doped drain (LDD) region 141 is formed by implanting impurities into the substrate 110 at opposing sides of the gate pattern 120 .
  • LDD lightly doped drain
  • the LDD region 141 is formed by performing an ion implantation process on the substrate 110 using the gate pattern 120 as a mask.
  • an n-type dopant such as phosphorus (P) or arsenic (As)
  • P phosphorus
  • As arsenic
  • a p-type dopant such as boron (B) or gallium (Ga)
  • B boron
  • Ga gallium
  • the LDD region 141 reduces an electric field between the source region 142 and the drain region 143 and reduces leakage current. Formation of the LDD region 141 is optional; as the channel length is reduced, however, forming an LDD region is advantageous.
  • FIG. 3H which shows the device after step S 70 , when the source region 142 and the drain region 143 are formed by implanting impurities into the substrate 110 at opposing sides of the gate pattern 120 and the gate spacer 124 .
  • a first spacer-forming insulating layer and a second spacer-forming insulating layer are sequentially formed on sidewalls of the gate pattern 120 and etched, thereby forming the gate spacer 124 including a first spacer 124 a and a second spacer 124 b .
  • impurities are implanted into the entire surface of the substrate 110 by performing an ion implantation process using the gate pattern 120 and the gate spacer 124 as masks, thereby forming the source region 142 and the drain region 143 .
  • the first spacer 124 a may be formed of a silicon oxide layer and the second spacer 124 b may be formed of a silicon nitride layer.
  • the source region 142 is formed in the recrystallized region 130 and the drain region 143 is formed in a non-recrystallized region spaced apart from and facing the source region 142 with respect to the gate pattern 120 .
  • an end-of-range (EOR) defect may be generated around the amorphous region 130 a .
  • the EOR defect may also be generated around the LDD region 141 , providing the drain region 143 with further increased gate-induced drain leakage (GIDL).
  • GIDL gate-induced drain leakage
  • the drain region 143 may not be formed in the recrystallized region 130 , thereby suppressing the leakage current from increasing.
  • the source region 142 plays an important role in enhancing the mobility of carriers.
  • the source region 142 is formed in the recrystallized region 130 , thereby increasing stress applied to the channel region.
  • leakage current can be reduced and channel conductivity can be improved.

Abstract

A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority from Korean Patent Application No. 10-2010-0106302 filed on Oct. 28, 2010 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119; the entire contents of this priority application are herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a reduced leakage current and improved channel conductivity, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
Research is under way to increase the operation speed and packing density of semiconductor devices. A semiconductor increases discrete devices such as a metal oxide semiconductor (MOS) transistor. As an integration degree of the semiconductor device is increased, scaling down a gate of the MOS transistor is becoming a major challenge. In addition, a channel region located under the gate becomes shorter.
Accordingly, various methods are investigated to enhance channel conductivity by increasing the mobility of carriers in a channel region with respect to a predetermined channel length. One mechanism for increasing the mobility of carriers is to induce compressive stress to a channel region to thereby increase hole mobility in the channel, while inducing tensile stress to the channel region to improve electron mobility in the channel region.
The stress memorization technique (SMT) is one technique that has recently been used to induce stress to a channel, which may, however, result in an increase of leakage current.
SUMMARY OF THE INVENTION
Embodiments of the present invention include a semiconductor device having a reduced leakage current and improved channel conductivity, as well as a method for manufacturing a semiconductor device having a reduced leakage current and improved channel conductivity.
According to an aspect of the present invention, a semiconductor device including a gate pattern is formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate is formed at one side of the gate pattern.
According to another aspect of the present invention, a method for manufacturing a semiconductor device includes forming a gate pattern on a substrate, forming a mask on the substrate at one side of the gate pattern, forming an amorphous region by implanting impurities into the substrate, removing the mask, and forming a recrystallized region by forming a stress liner on the substrate to cover the gate pattern and crystallizing the amorphous region.
As described above, the mobility of carriers can be enhanced by increasing stress applied to a channel. In addition, the mobility of carriers can be more effectively enhanced by inducing more stress from a source region than from a drain region. Further, characteristics of the semiconductor device can be more enhanced by reducing a leakage current generated in the drain region.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other features and advantages of the present invention will become more apparent by describing in detail embodiments thereof with reference to the attached drawings in which:
FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a flow chart showing process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention; and
FIGS. 3A to 3H are cross-sectional views showing process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
 DETAILED DESCRIPTION
Advantages and features of the present invention and methods of accomplishing the same may be understood more readily by reference to the following detailed description of exemplary embodiments and the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present invention will only be defined by the appended claims. In the drawings, the thickness of layers and regions are exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Spatially relative terms, such as “below,” “beneath,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. Like numbers refer to like elements throughout.
As used herein, the singular forms, “a”, “an” and “the,” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be further understood that the terms, “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Embodiments described herein will be described referring to plan views and/or cross-sectional views by way of ideal schematic views of the invention. Accordingly, the exemplary views may be modified depending on manufacturing technologies and/or tolerances. Therefore, the embodiments of the invention are not limited to those shown in the views, but include modifications in configuration formed on the basis of manufacturing processes. Therefore, regions exemplified in figures have schematic properties; and shapes of regions shown in figures are exemplary and are not intended to limit aspects of the invention.
Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1, which provides a cross-sectional view of the semiconductor device.
Referring to FIG. 1, the semiconductor device may include a gate pattern 120, a recrystallized region 130, a source region 142 and a drain region 143. The semiconductor device may further include a gate spacer 124 and a lightly doped drain (LDD) region 141.
The gate pattern 120 is formed on a substrate 110, and a channel region is formed under the gate pattern 120 to allow a current to flow therethrough.
The substrate 110 may be a rigid substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a gallium arsenic substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, and a display glass substrate. Alternatively, the substrate 110 may be a flexible plastic substrate made of, for example, polyimide, polyester, polycarbonate (PC), polyethersulfone (PES), polymethyl methacrylate (PMMA), or polyethylene naphthalate (PEN), polyethylene terephthalate (PET).
The gate pattern 120 may include a gate insulating layer 121 and a gate electrode 122. Although not shown in FIG. 1, a hard mask layer that protects the gate electrode 122 may be formed on the gate electrode 122. The hard mask layer may be formed of silicon nitride (Si3N4) or silicon oxynitride (SiON), but is not limited thereto.
The gate insulating layer 121 may include a silicon oxide (e.g., SiO2) layer, a silicon nitride (e.g., Si3N4) layer, SiON, GexOyNz, GexSiyOz, a high-k dielectric material or a combination thereof, or a stacked layer having these materials sequentially stacked. Here, the high-k dielectric material may include, but not limited to, HfO2, ZrO2, Al2O3, Ta2O5, hafnium silicate, zirconium silicate, a combination thereof.
The gate electrode 122 may be formed of, but not limited to, a single layer of poly-Si, poly-SiGe, doped poly-Si, a metal such as Ta, TaN, TaSiN, TiN, Mo, Ru, Ni, or NiSi, or a metal silicide, or a stacked layer having these materials sequentially stacked. In a case where the gate electrode 122 is formed of a metal or a metal silicide, low resistance can be realized with a fine line width, and doping impurities are not necessary.
The gate spacer 124 is formed on sidewalls of the gate pattern 120 and protects the gate electrode 122. The gate spacer 124 may have a single-layered structure formed of silicon nitride or a silicon oxide or a multilayered structure including a combination of a silicon nitride layer and a silicon oxide layer. FIG. 1 illustrates that the gate spacer 124 includes a first spacer 124 a and a second spacer 124 b. In detail, the first spacer 124 a may be formed of a silicon oxide layer, and the second spacer 124 b may be formed of a silicon nitride layer.
The recrystallized region 130 is formed at one side of the substrate 110 in view of the gate pattern 120. That is to say, the recrystallized region 130 is asymmetrically formed only at one side of the substrate 110 in view of the gate pattern 120. The recrystallized region 130 applies tensile stress or compressive stress to the channel region to thereby enhance carrier mobility in the channel region.
The recrystallized region 130 has a stacking fault defect. The stacking fault defect may occur when locations of atomic layers are changed or part of a continuous layer is added or removed due to stress applied to an amorphous region in the course of recrystallizing the amorphous region. Due to the stacking fault defect, the stress applied by recrystallizing is retained at a recrystallized lattice even after the stress is eliminated, and compressive stress or tensile stress is applied to the channel region. As shown in FIG. 1, the stacking fault defect may be formed such that it becomes closer to the gate pattern 120 (that is, in a direction indicated by an arrow ‘C’) downwardly in the substrate 110.
The closer to the channel region the stacking fault defect is formed, the more effectively the stress is applied to the channel region.
The LDD region 141 is formed by implanting low concentration impurity ions into the substrate on opposite sides of the gate pattern 120. The LDD region 141 relaxes electric fields in the source region 142 and the drain region 143 and reduces leakage current.
The impurities may be implanted by an ion implantation process. For example, n-type impurities (e.g., P, As, or the like) may be implanted for a negative metal oxide semiconductor (NMOS) device; and p-type impurities (e.g., B, BF2, Ga, or the like), may be implanted for a positive metal oxide semiconductor (PMOS) device.
A portion of the LDD region 141 on the source region 142 is formed in the recrystallized region 130, which is formed in the substrate 110 on one side of the gate pattern 120
The source region 142 and the drain region 143 are spaced apart from each other in view of the gate pattern 120 and the gate spacer 124, and are formed by implanting heavily doped impurities using the gate pattern 120 and the gate spacer 124 as masks. For an NMOS region, an n-type dopant such as phosphorus (P) or arsenic (As) may be implanted; and for a PMOS region, a p-type dopant such as boron (B) or gallium (Ga) may be implanted.
The source region 142 or the drain region 143 may be formed in the recrystallized region 130. The source region 142 formed in the recrystallized region 130 may have a stacking fault defect. The drain region 143 is spaced apart from and faces the source region 142 in view of the gate pattern 120 while having no stacking fault defect.
In a case where the source region 142 or the drain region 143 is formed in the recrystallized region 130 having compressive stress or tensile stress retained in a lattice structure, the mobility of carriers can be enhanced by applying stress to the channel region. However, an end-of-range (EOR) defect may be generated around an amorphous region in the course of amorphizing the substrate 110 before crystallization, and gate-induced drain leakage (GIDL) may occur to the drain region 143. The EOR defect may increase the GIDL. In embodiments of the semiconductor device, the source region 142 with a stacking fault defect can enhance the carrier mobility by increasing the stress applied to the channel region, while the drain region 143 without a stacking fault defect can reduce leakage current.
Each of the source region 142 and the drain region 143 may have an elevated structure raised from the substrate 110. The elevated source and drain structures may have shallow junction structures (with a projected range, Rp) formed on a top surface of the substrate 10 by injecting impurities. Accordingly, undesired degradation of the device characteristics due to a short channel effect can be overcome.
Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2 and 3A to 3H. FIG. 2 is a flow chart showing the process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 3A to 3H are cross-sectional views of the semiconductor device being manufactured with the process steps of FIG. 2.
Referring to FIG. 2, a method for manufacturing the semiconductor device may include forming a gate pattern (step S10), forming a mask (step S20), asymmetrically amorphizing (step S30), removing the mask (step S40) and recrystallizing (step S50). The method for manufacturing the semiconductor device may further include forming an LDD region (step S60) and forming source and drain regions (step S70).
Referring to FIG. 3A, the device is shown after step S10, when a gate pattern 120, including a gate insulating layer 121 and a gate electrode 122, is formed on a substrate 110.
In detail, an insulating layer for forming a gate insulating layer 121 and a layer for forming a gate electrode 122 are sequentially formed on the substrate 110 and patterned, thereby forming the gate pattern 120 having a stacked structure with the gate insulating layer 121 and the gate electrode 122 sequentially stacked.
Although a hard mask layer (not shown) may be formed on the gate electrode 122, it may be skipped as demanded by one skilled in the art. In order to protect the gate pattern 120, an insulating layer formed of a silicon oxide layer or a silicon nitride layer that is part of a gate spacer 124 may further be formed on sidewalls of the gate pattern 120.
Referring to FIG. 3B, the device is shown after step S20, when a mask 131 is formed on the substrate 110 at one side of the gate pattern 120. The mask 131 prevents impurities from being implanted into the substrate 110 below the mask 131 and being amorphized.
In detail, a hard mask layer or a photoresist layer is deposited to cover either side of the substrate 110 at opposite sides of the gate pattern 120. The mask 131 is formed of a hard mask layer or a photoresist. The hard mask layer may be formed of an insulating layer, and the photoresist layer may be formed of any photoresist that is generally used in the art.
Referring to FIG. 3C, the device is shown in step S30, as an amorphous region 130 a is formed by implanting impurities into the substrate 110.
In detail, if impurity ions are implanted on the substrate 110 using an ion implantation process, the impurity ions permeate into interstices of a crystal lattice, so that a crystalline region is changed into the amorphous region 130 a. The ion implantation process may be performed by a generally known method, and non-limiting examples of the impurities may include Si, Ge, Sb, In, As, P, BF2, Xe and Ar.
One side of the substrate 110 in view of the gate pattern 120 is covered by the mask 131. Thus, amorphization asymmetrically occurs only at a region of the substrate that is not covered by the mask 131.
During amorphization, the impurities may be implanted in a direction perpendicular to the substrate 110, as indicated by A (as shown, the impurities A are implanted in a direction perpendicular to the substantially planar exposed surface of the amorphous region 130 a), or may be implanted at a predetermined angle (α) of inclination, as indicated by B, with respect to the direction perpendicular to the substrate. In the latter case, an amorphous region 130 a′ is formed much closer to a channel region, thereby further enhancing stress applied to the channel region.
The predetermined angle (α) may be in a range of 10 to 40 degrees, more particularly in a range of 20 to 30 degrees. When the predetermined angle (α) is in a range of 10 to 40 degrees, the amorphous region 130 a may be formed close to the channel region, and impurity ions may be implanted without interference considering a distance between gate patterns 120.
Referring to FIG. 3D, the device is shown after step S40, when the mask 131, which was formed on the substrate 110 only to one side of the gate pattern 120, is removed.
In detail, amorphization is performed only on the substrate 110 at one side of the gate pattern 120, where the mask 131 is not formed, by an ion implantation process, as discussed above; and the mask 131 is then removed. The mask 131 may be removed by ashing and cleaning.
Referring to FIGS. 3E and 3F, the device is shown during step S50, when a stress liner 132 is formed on the entire surface of the substrate 110 to cover the gate pattern 120, and the amorphous region 130 a is recrystallized to form a recrystallized region 130.
In detail, the stress liner 132 is deposited on the entire surface of the substrate 110 by chemical vapor deposition (CVD) to cover the gate pattern 120 and annealed, thereby recrystallizing the amorphous region 130 a in the substrate 110 into a solid phase epitaxy.
In order to apply stress to the amorphous region 130 a in the substrate 110, the stress liner 132 may be made of a material having a thermal expansion coefficient that differs from that of the material that forms the substrate 110. In a case where the channel region below the gate pattern 120 has p-type impurity ions, the stress liner 132 may be made of a material capable of applying tensile stress to the channel region. In a case where the channel region below the gate pattern 120 has n-type impurity ions, the stress liner 132 may be made of a material capable of applying compressive stress to the channel region. In detail, for an NMOS, for example, the stress liner 132 may be formed of a silicon nitride (SixNy) layer using a low-pressure chemical vapor deposition (LPCVD) process. For a PMOS, the stress liner 132 may be formed of silicon carbide (SiC) using a plasma-enhanced chemical vapor deposition (PECVD) process.
The annealing may include, but is not limited to, spike annealing, rapid thermal annealing, and the like, which may be quickly performed.
As described above, the annealing performed in the presence of the stress liner 132 brings about crystallization to the solid phase epitaxy in the amorphous region 130 a. A stacking fault defect may occur when part of a continuous layer is added or removed while crystals of the amorphous region 130 a regrow. Accordingly, the stress applied to the amorphous region 130 by the stress liner 132 is retained in the recrystallized region 130 even after the stress liner 132 is eliminated, thereby applying stress to the channel region and increasing the channel conductivity.
The stacking fault defect is formed such that it becomes closer to the gate pattern (that is, in a direction indicated by an arrow ‘C’) downwardly in the substrate 110.
In addition, during the amorphization, if impurity ions are implanted at a predetermined angle of inclination such that some of the impurity ions extend under the gate pattern 120 (in the orientation shown) as impurity ions penetrate the substrate 110; consequently, the amorphous region is formed much closer to the channel region and the stacking fault defect is formed much closer to the channel region, thereby further enhancing stress applied to the channel region.
After the recrystallized region 130 having a stacking fault defect is formed, the stress liner 132 is completely removed by, for example, etching. In addition, before forming the stress liner 132, a silicon oxide layer (not shown) covering the entire surface of the substrate 110 may be formed. The silicon oxide layer may serve as an etch stop layer when etching the stress liner 132, and is also completely removed after recrystallization.
Referring to FIG. 3G, which shows the device after step S60, when a lightly doped drain (LDD) region 141 is formed by implanting impurities into the substrate 110 at opposing sides of the gate pattern 120.
In detail, the LDD region 141 is formed by performing an ion implantation process on the substrate 110 using the gate pattern 120 as a mask. In a case of an NMOS, an n-type dopant, such as phosphorus (P) or arsenic (As), may be used as the impurity, and in a case of a PMOS, a p-type dopant, such as boron (B) or gallium (Ga), may be used as the impurity.
The LDD region 141 reduces an electric field between the source region 142 and the drain region 143 and reduces leakage current. Formation of the LDD region 141 is optional; as the channel length is reduced, however, forming an LDD region is advantageous.
Referring to FIG. 3H, which shows the device after step S70, when the source region 142 and the drain region 143 are formed by implanting impurities into the substrate 110 at opposing sides of the gate pattern 120 and the gate spacer 124.
In detail, a first spacer-forming insulating layer and a second spacer-forming insulating layer are sequentially formed on sidewalls of the gate pattern 120 and etched, thereby forming the gate spacer 124 including a first spacer 124 a and a second spacer 124 b. Then, impurities are implanted into the entire surface of the substrate 110 by performing an ion implantation process using the gate pattern 120 and the gate spacer 124 as masks, thereby forming the source region 142 and the drain region 143. Here, the first spacer 124 a may be formed of a silicon oxide layer and the second spacer 124 b may be formed of a silicon nitride layer.
In particular embodiments, the source region 142 is formed in the recrystallized region 130 and the drain region 143 is formed in a non-recrystallized region spaced apart from and facing the source region 142 with respect to the gate pattern 120.
In step S30, an end-of-range (EOR) defect may be generated around the amorphous region 130 a. The EOR defect may also be generated around the LDD region 141, providing the drain region 143 with further increased gate-induced drain leakage (GIDL). Thus, the drain region 143 may not be formed in the recrystallized region 130, thereby suppressing the leakage current from increasing. Meanwhile, the source region 142 plays an important role in enhancing the mobility of carriers. The source region 142 is formed in the recrystallized region 130, thereby increasing stress applied to the channel region.
As described above, according to the semiconductor device and the method for manufacturing the same, leakage current can be reduced and channel conductivity can be improved.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. It is therefore desired that the present embodiments be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than the foregoing description to indicate the scope of the invention.

Claims (14)

What is claimed is:
1. A method for manufacturing a semiconductor device, comprising:
forming a gate pattern on a substrate, wherein a channel region is formed under the gate pattern,
forming a mask on a portion of the substrate at one side of the gate pattern, then
forming an amorphous region by implanting impurities into an unmasked portion of the substrate, then
removing the mask, and
forming a recrystallized region by forming a stress liner on the substrate to cover the gate pattern and crystallizing the amorphous region, wherein the stress liner is formed of a material that applies compressive stress or tensile stress to the channel region.
2. The method of claim 1, wherein the impurities are implanted in a direction perpendicular to the substrate.
3. The method of claim 1, wherein the impurities are implanted at a predetermined angle with respect to the direction perpendicular to the substrate.
4. The method of claim 3, wherein the predetermined angle is in a range of 10 to 40 degrees.
5. The method of claim 3, wherein the impurities are implanted at a predetermined angle such that, when the semiconductor device is oriented with the gate pattern at the top of the device, the impurities extend under the gate pattern in the substrate.
6. The method of claim 5, wherein the mask includes a photoresist layer.
7. The method of claim 1, wherein the stress liner includes a silicon nitride layer.
8. The method of claim 1, further comprising forming a source region and a drain region by removing the stress liner and implanting impurities using the gate pattern as a mask.
9. The method of claim 8, wherein the source region is formed in the recrystallized region.
10. The method of claim 8, wherein the amorphous region is crystallized by annealing.
11. The method of claim 1, wherein a stacking fault defect is formed such that it becomes closer to the gate pattern in a horizontal direction at greater depths downwardly in the substrate, when the substrate is oriented with the gate pattern at the top, while the amorphous region is crystallized.
12. A method for manufacturing a semiconductor device, comprising:
forming a gate pattern on a crystalline semiconductor substrate, wherein a channel region is formed under the gate pattern,
forming an amorphous region in the semiconductor substrate at one side of the gate pattern while maintaining a crystalline region at an opposite side of the gate pattern,
forming a stress liner on the semiconductor substrate and the gate pattern,
forming a recrystallized region by crystallizing the amorphous region in the presence of the stress liner, and
forming a source region in the recrystallized region, wherein the stress liner is formed of a material that applies compressive stress or tensile stress to the channel region.
13. The method of claim 12, wherein the amorphous region is formed by implanting impurities into the semiconductor substrate.
14. The method of claim 12, wherein a stacking fault defect is formed in the recrystallized region.
US13/240,470 2010-10-28 2011-09-22 Method for manufacturing semiconductor device Active 2031-12-12 US8633078B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020100106302A KR101714613B1 (en) 2010-10-28 2010-10-28 Semiconductor device and manufacturing method thereof
KR10-2010-0106302 2010-10-28

Publications (2)

Publication Number Publication Date
US20120108023A1 US20120108023A1 (en) 2012-05-03
US8633078B2 true US8633078B2 (en) 2014-01-21

Family

ID=45997213

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/240,470 Active 2031-12-12 US8633078B2 (en) 2010-10-28 2011-09-22 Method for manufacturing semiconductor device

Country Status (2)

Country Link
US (1) US8633078B2 (en)
KR (1) KR101714613B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10892263B2 (en) 2018-06-15 2021-01-12 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064888B2 (en) * 2013-06-28 2015-06-23 Globalfoundries Inc. Forming tunneling field-effect transistor with stacking fault and resulting device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0547794A (en) 1991-08-08 1993-02-26 Fujitsu Ltd Fabrication of semiconductor device
US5675166A (en) * 1995-07-07 1997-10-07 Motorola, Inc. FET with stable threshold voltage and method of manufacturing the same
US7410876B1 (en) 2007-04-05 2008-08-12 Freescale Semiconductor, Inc. Methodology to reduce SOI floating-body effect
US20090130817A1 (en) * 2007-11-16 2009-05-21 Angelo Pinto Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a dsb substrate
US20090298249A1 (en) 2008-05-30 2009-12-03 Jan Hoentschel Drive current increase in transistors by asymmetric amorphization implantation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0547794A (en) 1991-08-08 1993-02-26 Fujitsu Ltd Fabrication of semiconductor device
US5675166A (en) * 1995-07-07 1997-10-07 Motorola, Inc. FET with stable threshold voltage and method of manufacturing the same
US7410876B1 (en) 2007-04-05 2008-08-12 Freescale Semiconductor, Inc. Methodology to reduce SOI floating-body effect
US20090130817A1 (en) * 2007-11-16 2009-05-21 Angelo Pinto Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a dsb substrate
US20090298249A1 (en) 2008-05-30 2009-12-03 Jan Hoentschel Drive current increase in transistors by asymmetric amorphization implantation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10892263B2 (en) 2018-06-15 2021-01-12 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor device

Also Published As

Publication number Publication date
US20120108023A1 (en) 2012-05-03
KR101714613B1 (en) 2017-03-10
KR20120044800A (en) 2012-05-08

Similar Documents

Publication Publication Date Title
US7838887B2 (en) Source/drain carbon implant and RTA anneal, pre-SiGe deposition
US10720529B2 (en) Source/drain junction formation
CN108461394B (en) Method for manufacturing semiconductor device using stress memorization technology and semiconductor device
US8507958B2 (en) Transistor and method for forming the same
US8377784B2 (en) Method for fabricating a semiconductor device
US8927374B2 (en) Semiconductor device and fabrication method thereof
US8653560B2 (en) Semiconductor device and fabrication method thereof
US8361895B2 (en) Ultra-shallow junctions using atomic-layer doping
US20060234455A1 (en) Structures and methods for forming a locally strained transistor
US7772676B2 (en) Strained semiconductor device and method of making same
US20140264348A1 (en) Asymmetric Cyclic Desposition Etch Epitaxy
US9786565B2 (en) Semiconductor device and method of manufacturing the semiconductor device
KR101811713B1 (en) Methods of forming cmos transistors using tensile stress layers and hydrogen plasma treatment
US9209269B2 (en) Semiconductor structure and method for manufacturing the same
US8361868B2 (en) Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation
US20090142892A1 (en) Method of fabricating semiconductor device having thin strained relaxation buffer pattern and related device
US9099412B2 (en) Selective laser anneal on semiconductor material
US9059201B2 (en) Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation
US8633078B2 (en) Method for manufacturing semiconductor device
WO2015051563A1 (en) Mosfet structure and manufacturing method thereof
US20080197428A1 (en) Gate Electrode Structure, MOS Field Effect Transistors and Methods of Manufacturing the Same
KR101178016B1 (en) Advanced transistors with structured low dopant channels

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIM, KWAN-YONG;KOH, CHUNG-GEUN;KANG, SANG-BOM;AND OTHERS;SIGNING DATES FROM 20110527 TO 20110610;REEL/FRAME:026950/0420

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8