Automatic wafer die sorting machine for transistors and integrated cir- cuits
US D205962 S
Description (OCR text may contain errors)
AUTOMATIC WAFER DIE SORTING MACHINE FOR TRANSISTORS AND INTEGRATED CIR- CUITS David A. Glenn, Cuperfino, Calif., assignor to Electroglas, Inc., Menlo Park, Calif., a corporation of California Filed Aug. 5, 1965, Ser. No. 86,469
Term of patent 14 years (Cl. D551) Des. 205,962
Patented Oct. 11, 1966 Des. 205,962
PAGE 2 Fig. 2
FIGURE 1 is a prospective view of an automatic wafer die sorting machine for transistors and integrated circuits, showing my new design.
FIGURE 2 is a side elevational view looking from the left hand side of the machine shown in FIGURE 1.
The undisclosed rear portion of the machine shown in FIGURE 1 is unornamented.
The ornamental design for the automatic wafer die sorting machine for transistors and integrated circuits, as shown and described.
References Cited by the Examiner UNITED STATES PATENTS D. 189,969 3/1961 Ohtake D26-5 D. 199,697 12/1964 Maier D57-1 2,999,587 9/1961 Campbell 20981 X 3,198,330 8/1965 Wiesler 209-81 X OTHER REFERENCES Laboratory Reporter, Fisher Scientific, July 1964, cover page electron microscope.
WALLACE R. BURKE, Examiner.
BERNARD ANSHER, Assistant Examiner.