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Publication numberUSD259560 S
Publication typeGrant
Application numberUS 06/006,200
Publication dateJun 16, 1981
Filing dateJan 24, 1979
Priority dateJul 28, 1978
Publication number006200, 06006200, US D259560 S, US D259560S, US-S-D259560, USD259560 S, USD259560S
InventorsHidetoshi Mochizuki, Keizo Otsuki, Hideki Kosaka, Gen Murakami
Original AssigneeHitachi, Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor
US D259560 S
Abstract  available in
Images(3)
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Claims(1)
  1. The ornamental design for a semiconductor, as shown and described.
Description

FIG. 1 is a right side, top and front perspective view of a semiconductor showing our new design;

FIG. 2 is a rear elevational view thereof;

FIG. 3 is a left side view thereof;

FIG. 4 is a bottom view thereof;

FIG. 5 is a right side, top and front perspective view of a semiconductor showing another embodiment of our new design;

FIG. 6 is a bottom view thereof;

FIG. 7 is a right side, top and front perspective view of a semiconductor showing another embodiment of our new design;

FIG. 8 is a bottom view thereof;

FIG. 9 is a right side, top and front perspective view of a semiconductor showing another embodiment of our new design;

FIG. 10 is a bottom view thereof;

FIG. 11 is a right side, top and front perspective view of a semiconductor showing another embodiment of our new design;

FIG. 12 is a bottom view thereof.

Non-Patent Citations
Reference
1Electronics, 10-13-1977, p. 9, Semiconductor.
2Electronics, 10-27-1977, p. 9, Integrated Circuit Package, (square).
3Electronics, 11-24-1977, p. 145, Integrated Circuit Housing (bottom right).
4Electronics, 3-17-1977, front cover-LSI Package (top right).
Classifications
U.S. ClassificationD13/182