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Publication numberUSD261760 S
Publication typeGrant
Application numberUS 05/972,583
Publication dateNov 10, 1981
Filing dateDec 22, 1978
Publication number05972583, 972583, US D261760 S, US D261760S, US-S-D261760, USD261760 S, USD261760S
InventorsDaniel F. Dlugos
Original AssigneePitney Bowes Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electronic postal rate memory
US D261760 S
Images(2)
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Claims(1)
  1. The ornamental design for an electronic postal rate memory, as shown and described.
Description

FIG. 1 is a perspective view of an electronic postal rate memory showing my new design;

FIG. 2 is a front elevational view thereof on a reduced scale;

FIG. 3 is a top plan view thereof on a reduced scale;

FIG. 4 is a bottom view thereof on a reduced scale;

FIG. 5 is a rear elevatioal view thereof on a reduced scale;

FIG. 6 is a left side elevational view thereof on a reduced scale;

FIG. 7 is a right side elevational view thereof on a reduced scale.

Non-Patent Citations
Reference
1Electronics, 2-17-77, p. 22-Circuit Board with Ejector Handle.
2Electronics, 4-28-77, p. 99, top right, Memory Board.
3Vero Bulletin, 6-71, Card Ejector.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8649820Nov 7, 2011Feb 11, 2014Blackberry LimitedUniversal integrated circuit card apparatus and related methods
Classifications
U.S. ClassificationD14/438, D13/182