US D262962 S
FIG. 1 is a top plan view of a silicon wafer emitter electrode configuration showing my new design.
FIGS. 2 and 3 are end and side elevational views respectively of the electrode configuration.
This is a design for the characteristic features of emitter electrode configurations deposited on a silicon wafer with the electrodes delineated by the black areas in FIG. 1. The wafer is shown in broken lines for illustration purposes only.