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Publication numberUSD319629 S
Publication typeGrant
Application numberUS 07/181,253
Publication dateSep 3, 1991
Filing dateApr 13, 1988
Publication number07181253, 181253, US D319629 S, US D319629S, US-S-D319629, USD319629 S, USD319629S
InventorsTerutomi Hasegawa, Nobumichi Goto
Original AssigneeIbiden Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor substrate with conducting pattern
US D319629 S
Images(3)
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Claims(1)
  1. The ornamental design for a semiconductor substrate with conducting pattern, as shown.
Description

FIG. 1 is a top perspective view of a semi-conductor mounting device showing our new design;

FIG. 2 is a bottom perspective view thereof;

FIG. 3 is a right side elevational view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a rear elevational view thereof; and

FIG. 6 is a front elevational view thereof;

FIG. 7 is a top plan view thereof; and

FIG. 8 is a bottom plan view thereof.

Non-Patent Citations
Reference
1Electronic Design, p. 190, dtd 10-16-86, Disc Controller Pictured Thereon.
2Electronic Design, p. 7, dtd 10-16-86, NCR IC Package Pictured Thereon.
3Electronics, p. 131, dtd 8-7-86, CMOS Chip Pictured Thereon.
4Electronics, p. 7, Feb. 24, 1986, by Fujitsu Microelectronics, Inc.
Classifications
U.S. ClassificationD13/182