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Publication numberUSD319814 S
Publication typeGrant
Application numberUS 07/181,262
Publication dateSep 10, 1991
Filing dateApr 13, 1988
Publication number07181262, 181262, US D319814 S, US D319814S, US-S-D319814, USD319814 S, USD319814S
InventorsTerutomi Hasegawa, Nobumichi Goto
Original AssigneeIbiden Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semi-conductor substrate with conducting pattern
US D319814 S
Abstract  available in
Images(3)
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Claims(1)
  1. The ornamental design for a semi-conductor substrate with conductor pattern, as shown.
Description

FIG. 1 is a top perspective view of a semi-conductor substrate with conducting pattern shwoing our new design;

FIG. 2 is a bottom perspective view thereof;

FIG. 3 is a right side elevational view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a rear elevational view thereof; and

FIG. 6 is a front elevational view thereof.

FIG. 7 is a top plan view thereof; and

FIG. 8 is a bottom plan view thereof.

Non-Patent Citations
Reference
1Electronic Design, p. 190, dtd 10-16-86, Disc Controll picured thereon.
2Electronic Design, p. 7, dtd 10-16-86, NCR 1C package pictured thereon.
3Electronics, p. 131, dtd 8-7-86, CMOS chip pictured thereon.
4Electronics, p. 7, Feb. 24, 1986, by Fujitsu Microelectronics, Inc.
Classifications
U.S. ClassificationD13/182