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Publication numberUSD396211 S
Publication typeGrant
Application numberUS 29/068,462
Publication dateJul 21, 1998
Filing dateMar 3, 1997
Priority dateSep 9, 1996
Publication number068462, 29068462, US D396211 S, US D396211S, US-S-D396211, USD396211 S, USD396211S
InventorsYoshinari Enomoto, Satomi Kajiwara
Original AssigneeFuji Electric Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integrated circuit device
US D396211 S
Abstract  available in
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  1. The ornamental design for an integrated circuit device, as shown.

FIG. 1 is a perspective view of the top, front and left side of an integrated circuit device showing our new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a bottom plan view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a right side elevational view thereof;

FIG. 6 is a front elevational view thereof; and,

FIG. 7 is a rear elevational view thereof.

U.S. ClassificationD13/182