Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.


  1. Advanced Patent Search
Publication numberUSD416236 S
Publication typeGrant
Application numberUS 29/093,046
Publication dateNov 9, 1999
Filing dateSep 2, 1998
Publication number093046, 29093046, US D416236 S, US D416236S, US-S-D416236, USD416236 S, USD416236S
InventorsKazuhiro Kobayashi, Masayoshi Shiraishi, Osamu Tanabe
Original AssigneeCitizen Electronics Co., Ltd., Seiko Instruments Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integrated circuit package
US D416236 S
Abstract  available in
Previous page
Next page
  1. The ornamental design for an integrated circuit package, as shown and described.

FIG. 1 is a front elevational view of an integrated circuit package showing our new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a bottom plan view thereof;

FIG. 4 is a right elevational view thereof, the left side being the same in appearance as the right side;

FIG. 5 is a top, front, right perspective view thereof; and,

FIG. 6 is a bottom, rear, right perspective view thereof.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
USD668658 *Nov 15, 2011Oct 9, 2012Connectblue AbModule
USD668659 *Nov 15, 2011Oct 9, 2012Connectblue AbModule
USD680119 *Nov 15, 2011Apr 16, 2013Connectblue AbModule
USD680545 *Nov 15, 2011Apr 23, 2013Connectblue AbModule
USD689053 *Nov 15, 2011Sep 3, 2013Connectblue AbModule
USD692896 *Nov 15, 2011Nov 5, 2013Connectblue AbModule
USD731990 *Oct 17, 2012Jun 16, 2015Nok CorporationIntegrated circuit tag
U.S. ClassificationD13/182